* [PATCH v4 1/2] arm64: perf: Add support caps in sysfs
@ 2020-07-21 7:44 Shaokun Zhang
2020-07-21 7:44 ` [PATCH v4 2/2] arm64: perf: Expose some new events via sysfs Shaokun Zhang
2020-07-21 8:21 ` [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Will Deacon
0 siblings, 2 replies; 12+ messages in thread
From: Shaokun Zhang @ 2020-07-21 7:44 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Shaokun Zhang, Mark Rutland, Will Deacon
ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
like STALL_SLOT etc, are related to it. Let's add a caps directory to
/sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
PMMIR_EL1 registers in this entry. The user programs can get the slots
from sysfs directly.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
ChangeLog in v4:
* Address Will's comments.
ChangeLog in v3:
* Fix one typo in patch3
ChangeLog in v2:
* Add caps entry in sysfs
* Fix the PMU events typos
* Add one new patch to correct event ID in sysfs
arch/arm64/include/asm/sysreg.h | 2 +
arch/arm64/kernel/perf_event.c | 125 ++++++++++++++++++++++++++++------------
include/linux/perf/arm_pmu.h | 1 +
3 files changed, 91 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 463175f80341..56c45a9207c7 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -321,6 +321,8 @@
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
+#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
+
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4d7879484cec..ed0012979271 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -277,6 +277,51 @@ static struct attribute_group armv8_pmuv3_format_attr_group = {
.attrs = armv8_pmuv3_format_attrs,
};
+static int armv8pmu_get_pmu_version(void)
+{
+ int pmuver;
+ u64 dfr0;
+
+ dfr0 = read_sysreg(id_aa64dfr0_el1);
+ pmuver = cpuid_feature_extract_unsigned_field(dfr0,
+ ID_AA64DFR0_PMUVER_SHIFT);
+
+ return pmuver;
+}
+
+static umode_t
+armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
+ int unused)
+{
+ int pmuver = armv8pmu_get_pmu_version();
+
+ if (pmuver >= ID_AA64DFR0_PMUVER_8_4)
+ return attr->mode;
+
+ return 0;
+}
+
+static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", slots);
+}
+
+static DEVICE_ATTR_RO(slots);
+
+static struct attribute *armv8_pmuv3_caps_attrs[] = {
+ &dev_attr_slots.attr,
+ NULL,
+};
+
+static struct attribute_group armv8_pmuv3_caps_attr_group = {
+ .name = "caps",
+ .attrs = armv8_pmuv3_caps_attrs,
+ .is_visible = armv8pmu_caps_attr_is_visible,
+};
+
/*
* Perf Events' indices
*/
@@ -940,14 +985,11 @@ static void __armv8pmu_probe_pmu(void *info)
{
struct armv8pmu_probe_info *probe = info;
struct arm_pmu *cpu_pmu = probe->pmu;
- u64 dfr0;
u64 pmceid_raw[2];
u32 pmceid[2];
int pmuver;
- dfr0 = read_sysreg(id_aa64dfr0_el1);
- pmuver = cpuid_feature_extract_unsigned_field(dfr0,
- ID_AA64DFR0_PMUVER_SHIFT);
+ pmuver = armv8pmu_get_pmu_version();
if (pmuver == 0xf || pmuver == 0)
return;
@@ -994,7 +1036,8 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
int (*map_event)(struct perf_event *event),
const struct attribute_group *events,
- const struct attribute_group *format)
+ const struct attribute_group *format,
+ const struct attribute_group *caps)
{
int ret = armv8pmu_probe_pmu(cpu_pmu);
if (ret)
@@ -1019,104 +1062,112 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
events : &armv8_pmuv3_events_attr_group;
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
format : &armv8_pmuv3_format_attr_group;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
+ caps : &armv8_pmuv3_caps_attr_group;
return 0;
}
+static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
+ int (*map_event)(struct perf_event *event))
+{
+ return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
+}
+
static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_pmuv3",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
+ armv8_pmuv3_map_event);
}
static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a34",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
+ armv8_pmuv3_map_event);
}
static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
- armv8_a53_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
+ armv8_a53_map_event);
}
static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53",
- armv8_a53_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
+ armv8_a53_map_event);
}
static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
+ armv8_pmuv3_map_event);
}
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
- armv8_a57_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
+ armv8_a57_map_event);
}
static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a65",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
+ armv8_pmuv3_map_event);
}
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
- armv8_a57_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
+ armv8_a57_map_event);
}
static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73",
- armv8_a73_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
+ armv8_a73_map_event);
}
static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
+ armv8_pmuv3_map_event);
}
static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
+ armv8_pmuv3_map_event);
}
static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a77",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
+ armv8_pmuv3_map_event);
}
static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_neoverse_e1",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
+ armv8_pmuv3_map_event);
}
static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_neoverse_n1",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
+ armv8_pmuv3_map_event);
}
static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
- armv8_thunder_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
+ armv8_thunder_map_event);
}
static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan",
- armv8_vulcan_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
+ armv8_vulcan_map_event);
}
static const struct of_device_id armv8_pmu_of_device_ids[] = {
diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
index 5b616dde9a4c..1e129b57d51a 100644
--- a/include/linux/perf/arm_pmu.h
+++ b/include/linux/perf/arm_pmu.h
@@ -73,6 +73,7 @@ enum armpmu_attr_groups {
ARMPMU_ATTR_GROUP_COMMON,
ARMPMU_ATTR_GROUP_EVENTS,
ARMPMU_ATTR_GROUP_FORMATS,
+ ARMPMU_ATTR_GROUP_CAPS,
ARMPMU_NR_ATTR_GROUPS
};
--
2.7.4
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 2/2] arm64: perf: Expose some new events via sysfs
2020-07-21 7:44 [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Shaokun Zhang
@ 2020-07-21 7:44 ` Shaokun Zhang
2020-07-21 8:21 ` [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Will Deacon
1 sibling, 0 replies; 12+ messages in thread
From: Shaokun Zhang @ 2020-07-21 7:44 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Shaokun Zhang, Mark Rutland, Will Deacon
Some new PMU events can been detected by PMCEID1_EL0, but it can't
be listed, Let's expose these through sysfs.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
arch/arm64/include/asm/perf_event.h | 27 +++++++++++++++++++++++++++
arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
index e7765b62c712..2c2d7dbe8a02 100644
--- a/arch/arm64/include/asm/perf_event.h
+++ b/arch/arm64/include/asm/perf_event.h
@@ -72,6 +72,13 @@
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
+#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
+#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
+#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
/* Statistical profiling extension microarchitectural events */
#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
@@ -79,6 +86,26 @@
#define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
#define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
+/* AMUv1 architecture events */
+#define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004
+#define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005
+
+/* long-latency read miss events */
+#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006
+#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
+#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A
+#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
+
+/* additional latency from alignment events */
+#define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020
+#define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021
+#define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022
+
+/* Armv8.5 Memory Tagging Extension events */
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
+
/* ARMv8 recommended implementation defined event types */
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index ed0012979271..ecb897d7a17a 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -222,10 +222,29 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
+ ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
+ ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
+ ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
+ ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
+ ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
+ ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
+ ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
+ ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
+ ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
+ ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
+ ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
+ ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
+ ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
NULL,
};
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v4 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 7:44 [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Shaokun Zhang
2020-07-21 7:44 ` [PATCH v4 2/2] arm64: perf: Expose some new events via sysfs Shaokun Zhang
@ 2020-07-21 8:21 ` Will Deacon
2020-07-21 9:08 ` Shaokun Zhang
2020-07-21 10:49 ` [PATCH v5 " Shaokun Zhang
1 sibling, 2 replies; 12+ messages in thread
From: Will Deacon @ 2020-07-21 8:21 UTC (permalink / raw)
To: Shaokun Zhang; +Cc: Mark Rutland, linux-arm-kernel
On Tue, Jul 21, 2020 at 03:44:47PM +0800, Shaokun Zhang wrote:
> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
> like STALL_SLOT etc, are related to it. Let's add a caps directory to
> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
> PMMIR_EL1 registers in this entry. The user programs can get the slots
> from sysfs directly.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
> ChangeLog in v4:
> * Address Will's comments.
>
> ChangeLog in v3:
> * Fix one typo in patch3
>
> ChangeLog in v2:
> * Add caps entry in sysfs
> * Fix the PMU events typos
> * Add one new patch to correct event ID in sysfs
>
> arch/arm64/include/asm/sysreg.h | 2 +
> arch/arm64/kernel/perf_event.c | 125 ++++++++++++++++++++++++++++------------
> include/linux/perf/arm_pmu.h | 1 +
> 3 files changed, 91 insertions(+), 37 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 463175f80341..56c45a9207c7 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -321,6 +321,8 @@
> #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
> #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
>
> +#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
> +
> #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
> #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 4d7879484cec..ed0012979271 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -277,6 +277,51 @@ static struct attribute_group armv8_pmuv3_format_attr_group = {
> .attrs = armv8_pmuv3_format_attrs,
> };
>
> +static int armv8pmu_get_pmu_version(void)
> +{
> + int pmuver;
> + u64 dfr0;
> +
> + dfr0 = read_sysreg(id_aa64dfr0_el1);
> + pmuver = cpuid_feature_extract_unsigned_field(dfr0,
> + ID_AA64DFR0_PMUVER_SHIFT);
> +
> + return pmuver;
> +}
> +
> +static umode_t
> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
> + int unused)
> +{
> + int pmuver = armv8pmu_get_pmu_version();
> +
> + if (pmuver >= ID_AA64DFR0_PMUVER_8_4)
> + return attr->mode;
> +
> + return 0;
> +}
> +
> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
I'm still worried that this might trigger an UNDEF and panic the kernel
if STALL_SLOTS is not supported. The Arm ARM isn't clear about the
behaviour, so I think we have to assume the worst and check that STALL_SLOTS
is supported as well in armv8pmu_caps_attr_is_visible().
In other words, I think we have to check PMCEID1_EL0 as well as
AA64DFR0_EL1.
Will
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 8:21 ` [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Will Deacon
@ 2020-07-21 9:08 ` Shaokun Zhang
2020-07-21 10:49 ` [PATCH v5 " Shaokun Zhang
1 sibling, 0 replies; 12+ messages in thread
From: Shaokun Zhang @ 2020-07-21 9:08 UTC (permalink / raw)
To: Will Deacon; +Cc: Mark Rutland, linux-arm-kernel
Hi Will,
在 2020/7/21 16:21, Will Deacon 写道:
> On Tue, Jul 21, 2020 at 03:44:47PM +0800, Shaokun Zhang wrote:
>> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
>> like STALL_SLOT etc, are related to it. Let's add a caps directory to
>> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
>> PMMIR_EL1 registers in this entry. The user programs can get the slots
>> from sysfs directly.
>>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> ---
>> ChangeLog in v4:
>> * Address Will's comments.
>>
>> ChangeLog in v3:
>> * Fix one typo in patch3
>>
>> ChangeLog in v2:
>> * Add caps entry in sysfs
>> * Fix the PMU events typos
>> * Add one new patch to correct event ID in sysfs
>>
>> arch/arm64/include/asm/sysreg.h | 2 +
>> arch/arm64/kernel/perf_event.c | 125 ++++++++++++++++++++++++++++------------
>> include/linux/perf/arm_pmu.h | 1 +
>> 3 files changed, 91 insertions(+), 37 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 463175f80341..56c45a9207c7 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -321,6 +321,8 @@
>> #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
>> #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
>>
>> +#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
>> +
>> #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
>> #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
>>
>> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
>> index 4d7879484cec..ed0012979271 100644
>> --- a/arch/arm64/kernel/perf_event.c
>> +++ b/arch/arm64/kernel/perf_event.c
>> @@ -277,6 +277,51 @@ static struct attribute_group armv8_pmuv3_format_attr_group = {
>> .attrs = armv8_pmuv3_format_attrs,
>> };
>>
>> +static int armv8pmu_get_pmu_version(void)
>> +{
>> + int pmuver;
>> + u64 dfr0;
>> +
>> + dfr0 = read_sysreg(id_aa64dfr0_el1);
>> + pmuver = cpuid_feature_extract_unsigned_field(dfr0,
>> + ID_AA64DFR0_PMUVER_SHIFT);
>> +
>> + return pmuver;
>> +}
>> +
>> +static umode_t
>> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
>> + int unused)
>> +{
>> + int pmuver = armv8pmu_get_pmu_version();
>> +
>> + if (pmuver >= ID_AA64DFR0_PMUVER_8_4)
>> + return attr->mode;
>> +
>> + return 0;
>> +}
>> +
>> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
>> + char *buf)
>> +{
>> + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
>
> I'm still worried that this might trigger an UNDEF and panic the kernel
> if STALL_SLOTS is not supported. The Arm ARM isn't clear about the
> behaviour, so I think we have to assume the worst and check that STALL_SLOTS
Got it.
> is supported as well in armv8pmu_caps_attr_is_visible().
>
> In other words, I think we have to check PMCEID1_EL0 as well as
In fact, I did this in v4, but I removed it when I did more check on SLOTS
meaning that I have replied in v3 thread. I will add it in next version.
Thanks,
Shaokun
> AA64DFR0_EL1.
>
> Will
>
> .
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 8:21 ` [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Will Deacon
2020-07-21 9:08 ` Shaokun Zhang
@ 2020-07-21 10:49 ` Shaokun Zhang
2020-07-21 10:49 ` [PATCH v5 2/2] arm64: perf: Expose some new events via sysfs Shaokun Zhang
` (3 more replies)
1 sibling, 4 replies; 12+ messages in thread
From: Shaokun Zhang @ 2020-07-21 10:49 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Shaokun Zhang, Mark Rutland, Will Deacon
ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
like STALL_SLOT etc, are related to it. Let's add a caps directory to
/sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
PMMIR_EL1 registers in this entry. The user programs can get the slots
from sysfs directly.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
ChangeLog in v5:
* Add check STALL_SLOT in PMCEID1_EL0
ChangeLog in v4:
* Address Will's comments.
ChangeLog in v3:
* Fix one typo in patch3
ChangeLog in v2:
* Add caps entry in sysfs
* Fix the PMU events typos
* Add one new patch to correct event ID in sysfs
arch/arm64/include/asm/sysreg.h | 2 +
arch/arm64/kernel/perf_event.c | 127 ++++++++++++++++++++++++++++------------
include/linux/perf/arm_pmu.h | 1 +
3 files changed, 93 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 463175f80341..56c45a9207c7 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -321,6 +321,8 @@
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
+#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
+
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4d7879484cec..1be042e1e565 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -277,6 +277,53 @@ static struct attribute_group armv8_pmuv3_format_attr_group = {
.attrs = armv8_pmuv3_format_attrs,
};
+static int armv8pmu_get_pmu_version(void)
+{
+ int pmuver;
+ u64 dfr0;
+
+ dfr0 = read_sysreg(id_aa64dfr0_el1);
+ pmuver = cpuid_feature_extract_unsigned_field(dfr0,
+ ID_AA64DFR0_PMUVER_SHIFT);
+
+ return pmuver;
+}
+
+static umode_t
+armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
+ int unused)
+{
+ int pmuver = armv8pmu_get_pmu_version();
+ u32 pmceid1 = read_sysreg(pmceid1_el0);
+
+ /* Check the PMU version is >= v8.4 and STALL_SLOT is implemented */
+ if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid1 & BIT(31)))
+ return attr->mode;
+
+ return 0;
+}
+
+static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", slots);
+}
+
+static DEVICE_ATTR_RO(slots);
+
+static struct attribute *armv8_pmuv3_caps_attrs[] = {
+ &dev_attr_slots.attr,
+ NULL,
+};
+
+static struct attribute_group armv8_pmuv3_caps_attr_group = {
+ .name = "caps",
+ .attrs = armv8_pmuv3_caps_attrs,
+ .is_visible = armv8pmu_caps_attr_is_visible,
+};
+
/*
* Perf Events' indices
*/
@@ -940,14 +987,11 @@ static void __armv8pmu_probe_pmu(void *info)
{
struct armv8pmu_probe_info *probe = info;
struct arm_pmu *cpu_pmu = probe->pmu;
- u64 dfr0;
u64 pmceid_raw[2];
u32 pmceid[2];
int pmuver;
- dfr0 = read_sysreg(id_aa64dfr0_el1);
- pmuver = cpuid_feature_extract_unsigned_field(dfr0,
- ID_AA64DFR0_PMUVER_SHIFT);
+ pmuver = armv8pmu_get_pmu_version();
if (pmuver == 0xf || pmuver == 0)
return;
@@ -994,7 +1038,8 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
int (*map_event)(struct perf_event *event),
const struct attribute_group *events,
- const struct attribute_group *format)
+ const struct attribute_group *format,
+ const struct attribute_group *caps)
{
int ret = armv8pmu_probe_pmu(cpu_pmu);
if (ret)
@@ -1019,104 +1064,112 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
events : &armv8_pmuv3_events_attr_group;
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
format : &armv8_pmuv3_format_attr_group;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
+ caps : &armv8_pmuv3_caps_attr_group;
return 0;
}
+static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
+ int (*map_event)(struct perf_event *event))
+{
+ return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
+}
+
static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_pmuv3",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
+ armv8_pmuv3_map_event);
}
static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a34",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
+ armv8_pmuv3_map_event);
}
static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
- armv8_a53_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
+ armv8_a53_map_event);
}
static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53",
- armv8_a53_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
+ armv8_a53_map_event);
}
static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
+ armv8_pmuv3_map_event);
}
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
- armv8_a57_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
+ armv8_a57_map_event);
}
static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a65",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
+ armv8_pmuv3_map_event);
}
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
- armv8_a57_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
+ armv8_a57_map_event);
}
static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73",
- armv8_a73_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
+ armv8_a73_map_event);
}
static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
+ armv8_pmuv3_map_event);
}
static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
+ armv8_pmuv3_map_event);
}
static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cortex_a77",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
+ armv8_pmuv3_map_event);
}
static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_neoverse_e1",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
+ armv8_pmuv3_map_event);
}
static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_neoverse_n1",
- armv8_pmuv3_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
+ armv8_pmuv3_map_event);
}
static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
- armv8_thunder_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
+ armv8_thunder_map_event);
}
static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
{
- return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan",
- armv8_vulcan_map_event, NULL, NULL);
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
+ armv8_vulcan_map_event);
}
static const struct of_device_id armv8_pmu_of_device_ids[] = {
diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
index 5b616dde9a4c..1e129b57d51a 100644
--- a/include/linux/perf/arm_pmu.h
+++ b/include/linux/perf/arm_pmu.h
@@ -73,6 +73,7 @@ enum armpmu_attr_groups {
ARMPMU_ATTR_GROUP_COMMON,
ARMPMU_ATTR_GROUP_EVENTS,
ARMPMU_ATTR_GROUP_FORMATS,
+ ARMPMU_ATTR_GROUP_CAPS,
ARMPMU_NR_ATTR_GROUPS
};
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 2/2] arm64: perf: Expose some new events via sysfs
2020-07-21 10:49 ` [PATCH v5 " Shaokun Zhang
@ 2020-07-21 10:49 ` Shaokun Zhang
2020-07-21 11:56 ` [PATCH v5 1/2] arm64: perf: Add support caps in sysfs Will Deacon
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Shaokun Zhang @ 2020-07-21 10:49 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Shaokun Zhang, Mark Rutland, Will Deacon
Some new PMU events can been detected by PMCEID1_EL0, but it can't
be listed, Let's expose these through sysfs.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
arch/arm64/include/asm/perf_event.h | 27 +++++++++++++++++++++++++++
arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
index e7765b62c712..2c2d7dbe8a02 100644
--- a/arch/arm64/include/asm/perf_event.h
+++ b/arch/arm64/include/asm/perf_event.h
@@ -72,6 +72,13 @@
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
+#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
+#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
+#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
/* Statistical profiling extension microarchitectural events */
#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
@@ -79,6 +86,26 @@
#define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
#define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
+/* AMUv1 architecture events */
+#define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004
+#define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005
+
+/* long-latency read miss events */
+#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006
+#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
+#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A
+#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
+
+/* additional latency from alignment events */
+#define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020
+#define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021
+#define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022
+
+/* Armv8.5 Memory Tagging Extension events */
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
+
/* ARMv8 recommended implementation defined event types */
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 1be042e1e565..f959252ce39a 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -222,10 +222,29 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
+ ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
+ ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
+ ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
+ ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
+ ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
+ ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
+ ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
+ ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
+ ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
+ ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
+ ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
+ ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
+ ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
NULL,
};
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 10:49 ` [PATCH v5 " Shaokun Zhang
2020-07-21 10:49 ` [PATCH v5 2/2] arm64: perf: Expose some new events via sysfs Shaokun Zhang
@ 2020-07-21 11:56 ` Will Deacon
2020-07-22 2:25 ` Shaokun Zhang
2020-07-21 12:07 ` Will Deacon
2020-07-21 12:17 ` Mark Rutland
3 siblings, 1 reply; 12+ messages in thread
From: Will Deacon @ 2020-07-21 11:56 UTC (permalink / raw)
To: Shaokun Zhang; +Cc: Mark Rutland, linux-arm-kernel
Hi Shaokun,
On Tue, Jul 21, 2020 at 06:49:32PM +0800, Shaokun Zhang wrote:
> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
> like STALL_SLOT etc, are related to it. Let's add a caps directory to
> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
> PMMIR_EL1 registers in this entry. The user programs can get the slots
> from sysfs directly.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
> ChangeLog in v5:
> * Add check STALL_SLOT in PMCEID1_EL0
Thanks. I was just about to apply this, but then I realised that it's
completely broken for big.LITTLE :( One CPU might have PMMIR_EL1, but
another might not and so code such as:
> +static umode_t
> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
> + int unused)
> +{
> + int pmuver = armv8pmu_get_pmu_version();
> + u32 pmceid1 = read_sysreg(pmceid1_el0);
> +
> + /* Check the PMU version is >= v8.4 and STALL_SLOT is implemented */
> + if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid1 & BIT(31)))
> + return attr->mode;
> +
> + return 0;
> +}
> +
> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", slots);
> +}
Is dangerous if you can migrate between the two functions.
So I think what we need to do is use the cpu_pmu structure to stash the
PMMIR_EL1 register during probe, setting it to zero for CPUs without it,
and then you can just report that value on slots_show(), getting rid of
armv8pmu_caps_attr_is_visible() entirely.
Does that make sense? Sorry I didn't spot this earlier.
Will
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 10:49 ` [PATCH v5 " Shaokun Zhang
2020-07-21 10:49 ` [PATCH v5 2/2] arm64: perf: Expose some new events via sysfs Shaokun Zhang
2020-07-21 11:56 ` [PATCH v5 1/2] arm64: perf: Add support caps in sysfs Will Deacon
@ 2020-07-21 12:07 ` Will Deacon
2020-07-21 12:24 ` Mark Rutland
2020-07-21 12:17 ` Mark Rutland
3 siblings, 1 reply; 12+ messages in thread
From: Will Deacon @ 2020-07-21 12:07 UTC (permalink / raw)
To: Shaokun Zhang, linux-arm-kernel
Cc: Mark Rutland, catalin.marinas, kernel-team, Will Deacon
On Tue, 21 Jul 2020 18:49:32 +0800, Shaokun Zhang wrote:
> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
> like STALL_SLOT etc, are related to it. Let's add a caps directory to
> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
> PMMIR_EL1 registers in this entry. The user programs can get the slots
> from sysfs directly.
Applied to will (for-next/perf), thanks!
(Please note that I only applied the second patch)
[2/2] arm64: perf: Expose some new events via sysfs
https://git.kernel.org/will/c/55fdc1f44cd6
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 10:49 ` [PATCH v5 " Shaokun Zhang
` (2 preceding siblings ...)
2020-07-21 12:07 ` Will Deacon
@ 2020-07-21 12:17 ` Mark Rutland
2020-07-22 2:32 ` Shaokun Zhang
3 siblings, 1 reply; 12+ messages in thread
From: Mark Rutland @ 2020-07-21 12:17 UTC (permalink / raw)
To: Shaokun Zhang; +Cc: Will Deacon, linux-arm-kernel
On Tue, Jul 21, 2020 at 06:49:32PM +0800, Shaokun Zhang wrote:
> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
> like STALL_SLOT etc, are related to it. Let's add a caps directory to
> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
> PMMIR_EL1 registers in this entry. The user programs can get the slots
> from sysfs directly.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
[...]
> +static int armv8pmu_get_pmu_version(void)
> +{
> + int pmuver;
> + u64 dfr0;
> +
> + dfr0 = read_sysreg(id_aa64dfr0_el1);
> + pmuver = cpuid_feature_extract_unsigned_field(dfr0,
> + ID_AA64DFR0_PMUVER_SHIFT);
> +
> + return pmuver;
> +}
> +
> +static umode_t
> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
> + int unused)
> +{
> + int pmuver = armv8pmu_get_pmu_version();
> + u32 pmceid1 = read_sysreg(pmceid1_el0);
> +
> + /* Check the PMU version is >= v8.4 and STALL_SLOT is implemented */
> + if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid1 & BIT(31)))
> + return attr->mode;
> +
> + return 0;
> +}
> +
> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", slots);
> +}
You'll need to use the snapshots of these fields we take at probe time;
it's not safe to use read_sysreg() here as on a system with
heterogeneous CPUs this code can be running on one CPU while it's
printing information for another CPU.
Mark.
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 12:07 ` Will Deacon
@ 2020-07-21 12:24 ` Mark Rutland
0 siblings, 0 replies; 12+ messages in thread
From: Mark Rutland @ 2020-07-21 12:24 UTC (permalink / raw)
To: Will Deacon; +Cc: Shaokun Zhang, catalin.marinas, kernel-team, linux-arm-kernel
On Tue, Jul 21, 2020 at 01:07:24PM +0100, Will Deacon wrote:
> On Tue, 21 Jul 2020 18:49:32 +0800, Shaokun Zhang wrote:
> > ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
> > like STALL_SLOT etc, are related to it. Let's add a caps directory to
> > /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
> > PMMIR_EL1 registers in this entry. The user programs can get the slots
> > from sysfs directly.
>
> Applied to will (for-next/perf), thanks!
>
> (Please note that I only applied the second patch)
>
> [2/2] arm64: perf: Expose some new events via sysfs
> https://git.kernel.org/will/c/55fdc1f44cd6
FWIW, that looks good to me.
Mark.
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 11:56 ` [PATCH v5 1/2] arm64: perf: Add support caps in sysfs Will Deacon
@ 2020-07-22 2:25 ` Shaokun Zhang
0 siblings, 0 replies; 12+ messages in thread
From: Shaokun Zhang @ 2020-07-22 2:25 UTC (permalink / raw)
To: Will Deacon; +Cc: Mark Rutland, linux-arm-kernel
Hi Will,
在 2020/7/21 19:56, Will Deacon 写道:
> Hi Shaokun,
>
> On Tue, Jul 21, 2020 at 06:49:32PM +0800, Shaokun Zhang wrote:
>> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
>> like STALL_SLOT etc, are related to it. Let's add a caps directory to
>> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
>> PMMIR_EL1 registers in this entry. The user programs can get the slots
>> from sysfs directly.
>>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> ---
>> ChangeLog in v5:
>> * Add check STALL_SLOT in PMCEID1_EL0
>
> Thanks. I was just about to apply this, but then I realised that it's
> completely broken for big.LITTLE :( One CPU might have PMMIR_EL1, but
My bad, I miss it completely.
> another might not and so code such as:
>
>> +static umode_t
>> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
>> + int unused)
>> +{
>> + int pmuver = armv8pmu_get_pmu_version();
>> + u32 pmceid1 = read_sysreg(pmceid1_el0);
>> +
>> + /* Check the PMU version is >= v8.4 and STALL_SLOT is implemented */
>> + if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid1 & BIT(31)))
>> + return attr->mode;
>> +
>> + return 0;
>> +}
>> +
>> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
>> + char *buf)
>> +{
>> + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
>> +
>> + return snprintf(buf, PAGE_SIZE, "%d\n", slots);
>> +}
>
> Is dangerous if you can migrate between the two functions.
>
> So I think what we need to do is use the cpu_pmu structure to stash the
> PMMIR_EL1 register during probe, setting it to zero for CPUs without it,
> and then you can just report that value on slots_show(), getting rid of
Got it.
> armv8pmu_caps_attr_is_visible() entirely.
>
Do we need to check whether PMMIR_EL1 register is !0 and return attr->mode?
If not, it shall remove it completely.
> Does that make sense? Sorry I didn't spot this earlier.
>
Thanks Will's detailed explanation, I will do it soon.
Shaokun,
> Will
>
> .
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/2] arm64: perf: Add support caps in sysfs
2020-07-21 12:17 ` Mark Rutland
@ 2020-07-22 2:32 ` Shaokun Zhang
0 siblings, 0 replies; 12+ messages in thread
From: Shaokun Zhang @ 2020-07-22 2:32 UTC (permalink / raw)
To: Mark Rutland; +Cc: Will Deacon, linux-arm-kernel
Hi Mark,
在 2020/7/21 20:17, Mark Rutland 写道:
> On Tue, Jul 21, 2020 at 06:49:32PM +0800, Shaokun Zhang wrote:
>> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
>> like STALL_SLOT etc, are related to it. Let's add a caps directory to
>> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
>> PMMIR_EL1 registers in this entry. The user programs can get the slots
>> from sysfs directly.
>>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>
> [...]
>
>> +static int armv8pmu_get_pmu_version(void)
>> +{
>> + int pmuver;
>> + u64 dfr0;
>> +
>> + dfr0 = read_sysreg(id_aa64dfr0_el1);
>> + pmuver = cpuid_feature_extract_unsigned_field(dfr0,
>> + ID_AA64DFR0_PMUVER_SHIFT);
>> +
>> + return pmuver;
>> +}
>> +
>> +static umode_t
>> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
>> + int unused)
>> +{
>> + int pmuver = armv8pmu_get_pmu_version();
>> + u32 pmceid1 = read_sysreg(pmceid1_el0);
>> +
>> + /* Check the PMU version is >= v8.4 and STALL_SLOT is implemented */
>> + if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid1 & BIT(31)))
>> + return attr->mode;
>> +
>> + return 0;
>> +}
>> +
>> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
>> + char *buf)
>> +{
>> + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
>> +
>> + return snprintf(buf, PAGE_SIZE, "%d\n", slots);
>> +}
>
> You'll need to use the snapshots of these fields we take at probe time;
Ok,
> it's not safe to use read_sysreg() here as on a system with
> heterogeneous CPUs this code can be running on one CPU while it's
Apologies, I did not realize it at the beginning and will fix it in next
version.
Thanks,
Shaokun
> printing information for another CPU.
>
> Mark.
>
> .
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-07-22 2:34 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-21 7:44 [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Shaokun Zhang
2020-07-21 7:44 ` [PATCH v4 2/2] arm64: perf: Expose some new events via sysfs Shaokun Zhang
2020-07-21 8:21 ` [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Will Deacon
2020-07-21 9:08 ` Shaokun Zhang
2020-07-21 10:49 ` [PATCH v5 " Shaokun Zhang
2020-07-21 10:49 ` [PATCH v5 2/2] arm64: perf: Expose some new events via sysfs Shaokun Zhang
2020-07-21 11:56 ` [PATCH v5 1/2] arm64: perf: Add support caps in sysfs Will Deacon
2020-07-22 2:25 ` Shaokun Zhang
2020-07-21 12:07 ` Will Deacon
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2020-07-22 2:32 ` Shaokun Zhang
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