From: CK Hu <ck.hu@mediatek.com>
To: <yongqiang.niu@mediatek.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Bibby.Hsieh@mediatek.com, airlied@linux.ie,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
yt.shen@mediatek.com, robh+dt@kernel.org,
linux-mediatek@lists.infradead.org, p.zabel@pengutronix.de,
matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 03/25] drm/mediatek: add mutex mod into ddp private data
Date: Thu, 28 Mar 2019 09:33:56 +0800 [thread overview]
Message-ID: <1553736836.18612.12.camel@mtksdaap41> (raw)
In-Reply-To: <1553667561-25447-4-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:18 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> mutex0 MOD register offset not always 0x2C.
> for mt8183, that offset will be 0x30,
> add this regsiter offset into private data
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 53 +++++++++++++++++++++++++---------
> 1 file changed, 39 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 579ce28..7f0d46e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -41,10 +41,12 @@
> #define DISP_REG_CONFIG_DSI_SEL 0x050
> #define DISP_REG_CONFIG_DPI_SEL 0x064
>
> +#define MT2701_DISP_MUTEX0_MOD0 0x2C
Lower case, 0x2c.
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> -#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> +#define DISP_REG_MUTEX_MOD(data, n) ((data)->mutex_mod_reg + 0x20 * (n))
Why not just define as:
#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 *
(n))
The mutex_mod_reg inside a structure or not is decided by the caller.
> #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
> #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
>
> @@ -147,12 +149,17 @@ struct mtk_disp_mutex {
> bool claimed;
> };
>
> +struct mtk_ddp_data {
> + const unsigned int *mutex_mod;
> + unsigned int mutex_mod_reg;
const
Regards,
cK
> +};
> +
> struct mtk_ddp {
> struct device *dev;
> struct clk *clk;
> void __iomem *regs;
> struct mtk_disp_mutex mutex[10];
> - const unsigned int *mutex_mod;
> + const struct mtk_ddp_data *data;
> };
>
> static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -202,6 +209,21 @@ struct mtk_ddp {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const struct mtk_ddp_data mt2701_ddp_driver_data = {
> + .mutex_mod = mt2701_mutex_mod,
> + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
> +};
> +
> +static const struct mtk_ddp_data mt2712_ddp_driver_data = {
> + .mutex_mod = mt2712_mutex_mod,
> + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
> +};
> +
> +static const struct mtk_ddp_data mt8173_ddp_driver_data = {
> + .mutex_mod = mt8173_mutex_mod,
> + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
> +};
> +
> static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next,
> unsigned int *addr)
> @@ -464,15 +486,15 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> reg = MUTEX_SOF_DPI1;
> break;
> default:
> - if (ddp->mutex_mod[id] < 32) {
> - offset = DISP_REG_MUTEX_MOD(mutex->id);
> + if (ddp->data->mutex_mod[id] < 32) {
> + offset = DISP_REG_MUTEX_MOD(ddp->data, mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> - reg |= 1 << ddp->mutex_mod[id];
> + reg |= 1 << ddp->data->mutex_mod[id];
> writel_relaxed(reg, ddp->regs + offset);
> } else {
> offset = DISP_REG_MUTEX_MOD2(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> - reg |= 1 << (ddp->mutex_mod[id] - 32);
> + reg |= 1 << (ddp->data->mutex_mod[id] - 32);
> writel_relaxed(reg, ddp->regs + offset);
> }
> return;
> @@ -502,15 +524,15 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
> break;
> default:
> - if (ddp->mutex_mod[id] < 32) {
> - offset = DISP_REG_MUTEX_MOD(mutex->id);
> + if (ddp->data->mutex_mod[id] < 32) {
> + offset = DISP_REG_MUTEX_MOD(ddp->data, mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> - reg &= ~(1 << ddp->mutex_mod[id]);
> + reg &= ~(1 << ddp->data->mutex_mod[id]);
> writel_relaxed(reg, ddp->regs + offset);
> } else {
> offset = DISP_REG_MUTEX_MOD2(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> - reg &= ~(1 << (ddp->mutex_mod[id] - 32));
> + reg &= ~(1 << (ddp->data->mutex_mod[id] - 32));
> writel_relaxed(reg, ddp->regs + offset);
> }
> break;
> @@ -585,7 +607,7 @@ static int mtk_ddp_probe(struct platform_device *pdev)
> return PTR_ERR(ddp->regs);
> }
>
> - ddp->mutex_mod = of_device_get_match_data(dev);
> + ddp->data = of_device_get_match_data(dev);
>
> platform_set_drvdata(pdev, ddp);
>
> @@ -598,9 +620,12 @@ static int mtk_ddp_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id ddp_driver_dt_match[] = {
> - { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
> - { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
> - { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
> + { .compatible = "mediatek,mt2701-disp-mutex",
> + .data = &mt2701_ddp_driver_data},
> + { .compatible = "mediatek,mt2712-disp-mutex",
> + .data = &mt2712_ddp_driver_data},
> + { .compatible = "mediatek,mt8173-disp-mutex",
> + .data = &mt8173_ddp_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
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next prev parent reply other threads:[~2019-03-28 1:34 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 6:18 [PATCH v2 00/25] add drm support for MT8183 yongqiang.niu
2019-03-27 6:18 ` [PATCH v2 01/25] arm64: dts: add display nodes for mt8183 yongqiang.niu
2019-03-28 3:18 ` CK Hu
2019-03-27 6:18 ` [PATCH v2 02/25] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-03-27 9:39 ` CK Hu
2019-03-31 6:42 ` Rob Herring
2019-03-27 6:18 ` [PATCH v2 03/25] drm/mediatek: add mutex mod into ddp private data yongqiang.niu
2019-03-28 1:33 ` CK Hu [this message]
2019-03-27 6:19 ` [PATCH v2 04/25] drm/mediatek: add mutex sof " yongqiang.niu
2019-03-28 3:02 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 05/25] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-03-28 3:37 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 06/25] drm/mediatek: redefine mtk_ddp_sout_sel yongqiang.niu
2019-04-11 6:09 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 07/25] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-04-11 5:30 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 08/25] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-04-11 5:57 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 09/25] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-04-11 10:42 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 10/25] drm/mediatek: add commponent OVL0_2L yongqiang.niu
2019-04-11 6:14 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 11/25] drm/mediatek: add component OVL1_2L yongqiang.niu
2019-03-27 6:19 ` [PATCH v2 12/25] drm/mediatek: add component DITHER yongqiang.niu
2019-04-11 6:28 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 13/25] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-04-11 6:48 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 14/25] drm/medaitek: add layer_nr " yongqiang.niu
2019-04-11 10:57 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 15/25] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-04-11 11:01 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 16/25] drm/mediatek: add ddp write register common api yongqiang.niu
2019-04-11 11:15 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 17/25] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-04-16 7:38 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 18/25] drm/mediatek: add RDMA fifo size error handle yongqiang.niu
2019-04-16 8:00 ` CK Hu
2019-04-16 8:37 ` Yongqiang Niu
2019-04-16 11:31 ` YT Shen
2019-03-27 6:19 ` [PATCH v2 19/25] drm/mediatek: add function mtk_ddp_comp_get_type yongqiang.niu
2019-03-27 6:19 ` [PATCH v2 20/25] drm/mediatek: add ovl0/ovl0_2l usecase yongqiang.niu
2019-04-16 8:20 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 21/25] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
2019-04-11 10:33 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 22/25] drm/mediatek: adjust ddp clock control flow yongqiang.niu
2019-04-16 8:24 ` CK Hu
2019-05-28 5:35 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 23/25] drm/mediatek: add vmap support for mediatek drm yongqiang.niu
2019-04-16 8:30 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 24/25] drm/mediatek: respect page offset for PRIME mmap calls yongqiang.niu
2019-04-16 8:33 ` CK Hu
2019-05-28 5:35 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 25/25] drm/mediatek: enable allow_fb_modifiers for mediatek drm yongqiang.niu
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