* [PATCH/RFT] arm64: dts: renesas: r8a77990: Fix register range of display node
@ 2019-06-09 12:43 Yoshihiro Kaneko
2019-06-11 12:30 ` Simon Horman
0 siblings, 1 reply; 5+ messages in thread
From: Yoshihiro Kaneko @ 2019-06-09 12:43 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Magnus Damm, Simon Horman, Geert Uytterhoeven, linux-arm-kernel
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Since the R8A77990 SoC uses DU{0,1}, the range from the base address to
the 0x4000 address is used.
This patch fixed it.
Fixes: 13ee2bfc5444 ("arm64: dts: renesas: r8a77990: Add display output support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
This patch is based on the devel branch of Simon Horman's renesas tree.
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 547e970..9b15da1 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1760,7 +1760,7 @@
du: display@feb00000 {
compatible = "renesas,du-r8a77990";
- reg = <0 0xfeb00000 0 0x80000>;
+ reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
--
1.9.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH/RFT] arm64: dts: renesas: r8a77990: Fix register range of display node
2019-06-09 12:43 [PATCH/RFT] arm64: dts: renesas: r8a77990: Fix register range of display node Yoshihiro Kaneko
@ 2019-06-11 12:30 ` Simon Horman
2019-06-11 14:02 ` Laurent Pinchart
0 siblings, 1 reply; 5+ messages in thread
From: Simon Horman @ 2019-06-11 12:30 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-renesas-soc, Magnus Damm, Laurent Pinchart,
Geert Uytterhoeven, linux-arm-kernel
+ Laurent
On Sun, Jun 09, 2019 at 09:43:18PM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> Since the R8A77990 SoC uses DU{0,1}, the range from the base address to
> the 0x4000 address is used.
> This patch fixed it.
>
> Fixes: 13ee2bfc5444 ("arm64: dts: renesas: r8a77990: Add display output support")
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Is a similar fix also appropriate for D3 (r8a77995)
And a variant that reduces the register size to 0x5000
for M3-W (r8a77965).
> ---
>
> This patch is based on the devel branch of Simon Horman's renesas tree.
>
> arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> index 547e970..9b15da1 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -1760,7 +1760,7 @@
>
> du: display@feb00000 {
> compatible = "renesas,du-r8a77990";
> - reg = <0 0xfeb00000 0 0x80000>;
> + reg = <0 0xfeb00000 0 0x40000>;
> interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 724>,
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH/RFT] arm64: dts: renesas: r8a77990: Fix register range of display node
2019-06-11 12:30 ` Simon Horman
@ 2019-06-11 14:02 ` Laurent Pinchart
2019-06-12 12:11 ` Simon Horman
0 siblings, 1 reply; 5+ messages in thread
From: Laurent Pinchart @ 2019-06-11 14:02 UTC (permalink / raw)
To: Simon Horman
Cc: Laurent Pinchart, Yoshihiro Kaneko, Magnus Damm,
linux-renesas-soc, Geert Uytterhoeven, linux-arm-kernel
Hello,
On Tue, Jun 11, 2019 at 02:30:27PM +0200, Simon Horman wrote:
> + Laurent
>
> On Sun, Jun 09, 2019 at 09:43:18PM +0900, Yoshihiro Kaneko wrote:
> > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> >
> > Since the R8A77990 SoC uses DU{0,1}, the range from the base address to
> > the 0x4000 address is used.
> > This patch fixed it.
> >
> > Fixes: 13ee2bfc5444 ("arm64: dts: renesas: r8a77990: Add display output support")
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>
> Thanks,
>
> This looks fine to me but I will wait to see if there are other reviews
> before applying.
>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Is a similar fix also appropriate for D3 (r8a77995)
Yes it is.
> And a variant that reduces the register size to 0x5000
> for M3-W (r8a77965).
M3-W has registers at 0xfeb60000. You could reduce the size from
0x80000 to 0x70000 but I don't think it's worth it.
> > ---
> >
> > This patch is based on the devel branch of Simon Horman's renesas tree.
> >
> > arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > index 547e970..9b15da1 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > @@ -1760,7 +1760,7 @@
> >
> > du: display@feb00000 {
> > compatible = "renesas,du-r8a77990";
> > - reg = <0 0xfeb00000 0 0x80000>;
> > + reg = <0 0xfeb00000 0 0x40000>;
> > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&cpg CPG_MOD 724>,
--
Regards,
Laurent Pinchart
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH/RFT] arm64: dts: renesas: r8a77990: Fix register range of display node
2019-06-11 14:02 ` Laurent Pinchart
@ 2019-06-12 12:11 ` Simon Horman
2019-06-16 11:27 ` Yoshihiro Kaneko
0 siblings, 1 reply; 5+ messages in thread
From: Simon Horman @ 2019-06-12 12:11 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Laurent Pinchart, Yoshihiro Kaneko, Magnus Damm,
linux-renesas-soc, Geert Uytterhoeven, linux-arm-kernel
On Tue, Jun 11, 2019 at 05:02:52PM +0300, Laurent Pinchart wrote:
> Hello,
>
> On Tue, Jun 11, 2019 at 02:30:27PM +0200, Simon Horman wrote:
> > + Laurent
> >
> > On Sun, Jun 09, 2019 at 09:43:18PM +0900, Yoshihiro Kaneko wrote:
> > > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > >
> > > Since the R8A77990 SoC uses DU{0,1}, the range from the base address to
> > > the 0x4000 address is used.
> > > This patch fixed it.
> > >
> > > Fixes: 13ee2bfc5444 ("arm64: dts: renesas: r8a77990: Add display output support")
> > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> >
> > Thanks,
> >
> > This looks fine to me but I will wait to see if there are other reviews
> > before applying.
> >
> > Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Thanks, I have applied this for inclusion in v5.3.
> > Is a similar fix also appropriate for D3 (r8a77995)
>
> Yes it is.
Nice.
Kaneko-san, could you prepare a patch?
> > And a variant that reduces the register size to 0x5000
> > for M3-W (r8a77965).
>
> M3-W has registers at 0xfeb60000. You could reduce the size from
> 0x80000 to 0x70000 but I don't think it's worth it.
Got it, lets leave M3-W as is.
...
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH/RFT] arm64: dts: renesas: r8a77990: Fix register range of display node
2019-06-12 12:11 ` Simon Horman
@ 2019-06-16 11:27 ` Yoshihiro Kaneko
0 siblings, 0 replies; 5+ messages in thread
From: Yoshihiro Kaneko @ 2019-06-16 11:27 UTC (permalink / raw)
To: Simon Horman
Cc: Laurent Pinchart, Magnus Damm, Linux-Renesas, Geert Uytterhoeven,
Laurent Pinchart, Linux ARM
Hi Simon-san,
2019年6月12日(水) 21:12 Simon Horman <horms@verge.net.au>:
>
> On Tue, Jun 11, 2019 at 05:02:52PM +0300, Laurent Pinchart wrote:
> > Hello,
> >
> > On Tue, Jun 11, 2019 at 02:30:27PM +0200, Simon Horman wrote:
> > > + Laurent
> > >
> > > On Sun, Jun 09, 2019 at 09:43:18PM +0900, Yoshihiro Kaneko wrote:
> > > > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > >
> > > > Since the R8A77990 SoC uses DU{0,1}, the range from the base address to
> > > > the 0x4000 address is used.
> > > > This patch fixed it.
> > > >
> > > > Fixes: 13ee2bfc5444 ("arm64: dts: renesas: r8a77990: Add display output support")
> > > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> > >
> > > Thanks,
> > >
> > > This looks fine to me but I will wait to see if there are other reviews
> > > before applying.
> > >
> > > Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> >
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>
> Thanks, I have applied this for inclusion in v5.3.
>
> > > Is a similar fix also appropriate for D3 (r8a77995)
> >
> > Yes it is.
>
> Nice.
>
> Kaneko-san, could you prepare a patch?
Got it, will do.
Regards,
Kaneko
>
> > > And a variant that reduces the register size to 0x5000
> > > for M3-W (r8a77965).
> >
> > M3-W has registers at 0xfeb60000. You could reduce the size from
> > 0x80000 to 0x70000 but I don't think it's worth it.
>
> Got it, lets leave M3-W as is.
>
> ...
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2019-06-09 12:43 [PATCH/RFT] arm64: dts: renesas: r8a77990: Fix register range of display node Yoshihiro Kaneko
2019-06-11 12:30 ` Simon Horman
2019-06-11 14:02 ` Laurent Pinchart
2019-06-12 12:11 ` Simon Horman
2019-06-16 11:27 ` Yoshihiro Kaneko
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