From: <yongqiang.niu@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4, 33/33] drm/mediatek: add support for mediatek SOC MT8183
Date: Tue, 9 Jul 2019 06:34:13 +0800 [thread overview]
Message-ID: <1562625253-29254-34-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1562625253-29254-1-git-send-email-yongqiang.niu@mediatek.com>
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
This patch add support for mediatek SOC MT8183
1.ovl_2l share driver with ovl
2.rdma1 share drive with rdma0, but fifo size is different
3.add mt8183 mutex private data, and mmsys private data
4.add mt8183 main and external path module for crtc create
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 12 ++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 69 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++++++++++++++++++++
5 files changed, 147 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 7e99827..cd2b928 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -381,11 +381,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
.fmt_rgb565_is_0 = true,
};
+static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+};
+
+static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 2,
+ .fmt_rgb565_is_0 = true,
+};
+
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = &mt2701_ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = &mt8173_ovl_driver_data},
+ { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = &mt8183_ovl_driver_data},
+ { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = &mt8183_ovl_2l_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index b0a5cff..5d62588 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -336,11 +336,23 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
.fifo_size = SZ_8K,
};
+static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
+ .fifo_size = 5 * SZ_1K,
+};
+
+static const struct mtk_disp_rdma_data mt8183_rdma1_driver_data = {
+ .fifo_size = SZ_2K,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = &mt8173_rdma_driver_data},
+ { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = &mt8183_rdma_driver_data},
+ { .compatible = "mediatek,mt8183-disp-rdma1",
+ .data = &mt8183_rdma1_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index c4d8ecb..b5bb794 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -41,19 +41,31 @@
#define DISP_REG_CONFIG_DSI_SEL 0x050
#define DISP_REG_CONFIG_DPI_SEL 0x064
+#define MT8183_DISP_OVL0_MOUT_EN 0xf00
#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
#define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
#define MT8183_DISP_PATH0_SEL_IN 0xf24
+#define MT8183_DISP_DSI0_SEL_IN 0xf2c
+#define MT8183_DISP_DPI0_SEL_IN 0xf30
+#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
+#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
#define DITHER0_MOUT_IN_DSI0 BIT(0)
#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
#define DSI0_SEL_IN_RDMA0 0x1
+#define MT8183_DSI0_SEL_IN_RDMA1 0x3
+#define MT8183_DPI0_SEL_IN_RDMA0 0x1
+#define MT8183_DPI0_SEL_IN_RDMA1 0x2
+#define MT8183_RDMA0_SOUT_COLOR0 0x1
+#define MT8183_RDMA1_SOUT_DSI0 0x1
#define MT2701_DISP_MUTEX0_MOD0 0x2c
#define MT2701_DISP_MUTEX0_SOF0 0x30
+#define MT8183_DISP_MUTEX0_MOD0 0x30
+#define MT8183_DISP_MUTEX0_SOF0 0x2c
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
@@ -64,6 +76,18 @@
#define INT_MUTEX BIT(1)
+#define MT8183_MUTEX_MOD_DISP_RDMA0 0
+#define MT8183_MUTEX_MOD_DISP_RDMA1 1
+#define MT8183_MUTEX_MOD_DISP_OVL0 9
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
+#define MT8183_MUTEX_MOD_DISP_WDMA0 12
+#define MT8183_MUTEX_MOD_DISP_COLOR0 13
+#define MT8183_MUTEX_MOD_DISP_CCORR0 14
+#define MT8183_MUTEX_MOD_DISP_AAL0 15
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
+#define MT8183_MUTEX_MOD_DISP_DITHER0 17
+
#define MT8173_MUTEX_MOD_DISP_OVL0 11
#define MT8173_MUTEX_MOD_DISP_OVL1 12
#define MT8173_MUTEX_MOD_DISP_RDMA0 13
@@ -113,6 +137,10 @@
#define MUTEX_SOF_DSI2 5
#define MUTEX_SOF_DSI3 6
+#define MT8183_MUTEX_SOF_DPI0 2
+#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6)
+#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+
#define OVL0_MOUT_EN_COLOR0 0x1
#define OD_MOUT_EN_RDMA0 0x1
#define OD1_MOUT_EN_RDMA1 BIT(16)
@@ -248,6 +276,20 @@ struct mtk_mmsys_reg_data {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
+static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
+ [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
+ [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
+};
+
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -258,6 +300,12 @@ struct mtk_mmsys_reg_data {
[DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
+ [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
+ [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
+};
+
static const struct mtk_ddp_data mt2701_ddp_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -279,6 +327,13 @@ struct mtk_mmsys_reg_data {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
};
+static const struct mtk_ddp_data mt8183_ddp_driver_data = {
+ .mutex_mod = mt8183_mutex_mod,
+ .mutex_sof = mt8183_mutex_sof,
+ .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+};
+
const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = {
.ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN,
.dsi0_sel_in = DISP_REG_CONFIG_DSI_SEL,
@@ -295,6 +350,18 @@ struct mtk_mmsys_reg_data {
.dsi0_sel_in_rdma1 = DSI0_SEL_IN_RDMA1,
};
+const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data = {
+ .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN,
+ .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN,
+ .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0,
+ .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN,
+ .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0,
+ .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN,
+ .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1,
+ .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN,
+ .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1,
+};
+
static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
@@ -742,6 +809,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
.data = &mt2712_ddp_driver_data},
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = &mt8173_ddp_driver_data},
+ { .compatible = "mediatek,mt8183-disp-mutex",
+ .data = &mt8183_ddp_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
index 43dabb6..0befb1c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
@@ -23,6 +23,7 @@
extern const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data;
extern const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data;
+extern const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data;
void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
const struct mtk_mmsys_reg_data *reg_data,
enum mtk_ddp_comp_id cur,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5f94259..3d41e353 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -192,6 +192,24 @@ static int mtk_atomic_commit(struct drm_device *drm,
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_OVL_2L0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -219,6 +237,14 @@ static int mtk_atomic_commit(struct drm_device *drm,
.reg_data = &mt8173_mmsys_reg_data,
};
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
+ .main_path = mt8183_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
+ .ext_path = mt8183_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .reg_data = &mt8183_mmsys_reg_data,
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -414,12 +440,22 @@ static void mtk_drm_unbind(struct device *dev)
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8183-disp-rdma1",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
+ { .compatible = "mediatek,mt8183-disp-ccorr",
+ .data = (void *)MTK_DISP_CCORR },
{ .compatible = "mediatek,mt2701-disp-color",
.data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-color",
@@ -428,22 +464,30 @@ static void mtk_drm_unbind(struct device *dev)
.data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8183-disp-dither",
+ .data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8183-dsi",
+ .data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt2701-dpi",
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8173-dpi",
.data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8183-dpi",
+ .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8183-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
@@ -519,6 +563,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
*/
if (comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_OVL ||
+ comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DSI ||
comp_type == MTK_DPI) {
@@ -623,6 +668,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
.data = &mt2712_mmsys_driver_data},
{ .compatible = "mediatek,mt8173-mmsys",
.data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-display",
+ .data = &mt8183_mmsys_driver_data},
{ }
};
--
1.8.1.1.dirty
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prev parent reply other threads:[~2019-07-08 22:47 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-08 22:33 [PATCH v4, 00/33] add drm support for MT8183 yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 01/33] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-07-17 3:22 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 02/33] dt-bindings: mediatek: add ovl_2l description " yongqiang.niu
2019-07-24 20:15 ` Rob Herring
2019-07-08 22:33 ` [PATCH v4, 03/33] dt-bindings: mediatek: add ccorr " yongqiang.niu
2019-07-17 3:37 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 04/33] dt-bindings: mediatek: add dither " yongqiang.niu
2019-07-17 3:40 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 05/33] dt-bindings: mediatek: add RDMA1 " yongqiang.niu
2019-07-24 20:16 ` Rob Herring
2019-07-25 3:20 ` CK Hu
2019-07-25 22:23 ` Rob Herring
2019-07-08 22:33 ` [PATCH v4, 06/33] dt-bindings: mediatek: add mutex " yongqiang.niu
2019-07-16 23:59 ` Ryan Case
2019-07-08 22:33 ` [PATCH v4, 07/33] arm64: dts: add display nodes for mt8183 yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 08/33] drm/mediatek: add mutex mod into ddp private data yongqiang.niu
2019-07-17 5:22 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 09/33] drm/mediatek: add mutex mod register offset " yongqiang.niu
2019-07-17 5:23 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 10/33] drm/mediatek: add mutex sof " yongqiang.niu
2019-07-17 5:28 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 11/33] drm/mediatek: add mutex sof register offset " yongqiang.niu
2019-07-17 5:31 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 12/33] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-07-17 5:35 ` CK Hu
2019-08-29 12:39 ` Yongqiang Niu
2019-07-08 22:33 ` [PATCH v4, 13/33] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-07-17 5:46 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 14/33] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 15/33] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 16/33] drm/mediatek: add commponent OVL_2L0 yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 17/33] drm/mediatek: add component OVL_2L1 yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 18/33] drm/mediatek: add component DITHER yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 19/33] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 20/33] drm/medaitek: add layer_nr " yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 21/33] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-07-17 5:53 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 22/33] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-07-17 5:58 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 23/33] drm/mediatek: add ovl0/ovl_2l0 usecase yongqiang.niu
2019-07-16 23:13 ` Ryan Case
2019-07-17 6:47 ` CK Hu
2019-08-29 13:15 ` Yongqiang Niu
2019-07-08 22:34 ` [PATCH v4, 24/33] drm/mediatek: distinguish ovl and ovl_2l by layer_nr yongqiang.niu
2019-07-17 6:55 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 25/33] drm/mediatek: add clock property check before get it yongqiang.niu
2019-07-17 7:01 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 26/33] drm/mediatek: add connection from OVL0 to OVL_2L0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 27/33] drm/mediatek: add connection from RDMA0 to COLOR0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 28/33] drm/mediatek: add connection from RDMA1 to DSI0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 29/33] drm/mediatek: add connection from OVL_2L0 to RDMA0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 30/33] drm/mediatek: add connection from OVL_2L1 to RDMA1 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 31/33] drm/mediatek: add connection from DITHER0 to DSI0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 32/33] drm/mediatek: add connection from RDMA0 " yongqiang.niu
2019-07-08 22:34 ` yongqiang.niu [this message]
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