From: Dong Aisheng <aisheng.dong@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Dong Aisheng <aisheng.dong@nxp.com>,
devicetree@vger.kernel.org, dongas86@gmail.com,
catalin.marinas@arm.com, will.deacon@arm.com,
oliver.graute@gmail.com, robh+dt@kernel.org, linux-imx@nxp.com,
kernel@pengutronix.de, fabio.estevam@nxp.com,
Mark Rutland <mark.rutland@arm.com>,
shawnguo@kernel.org
Subject: [PATCH V3 05/15] arm64: dts: imx8: add conn lpcg clocks
Date: Thu, 12 Sep 2019 23:30:42 +0800 [thread overview]
Message-ID: <1568302252-28066-6-git-send-email-aisheng.dong@nxp.com> (raw)
In-Reply-To: <1568302252-28066-1-git-send-email-aisheng.dong@nxp.com>
Add conn lpcg clocks
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Oliver Graute <oliver.graute@kococonnector.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* update to use clock-indices property instead of bit-offset property
v1->v2:
* Use old SCU clock binding temporarily to avoid build warning due to SCU
clock cell will be changed to 2.
* add power domain propertyv1->v2:
---
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 103 +++++++++++++++++++++++-
1 file changed, 100 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index e5f6041..0a0e479 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -4,15 +4,33 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
+#include <dt-bindings/firmware/imx/rsrc.h>
+
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
- conn_lpcg: clock-controller@5b200000 {
- reg = <0x5b200000 0xb0000>;
- #clock-cells = <1>;
+ conn_axi_clk: clock-conn-axi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <333333333>;
+ clock-output-names = "conn_axi_clk";
+ };
+
+ conn_ahb_clk: clock-conn-ahb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <166666666>;
+ clock-output-names = "conn_ahb_clk";
+ };
+
+ conn_ipg_clk: clock-conn-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <83333333>;
+ clock-output-names = "conn_ipg_clk";
};
usdhc1: mmc@5b010000 {
@@ -92,4 +110,83 @@ conn_subsys: bus@5b000000 {
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};
+
+ /* LPCG clocks */
+ conn_lpcg: clock-controller-legacy@5b200000 {
+ reg = <0x5b200000 0xb0000>;
+ #clock-cells = <1>;
+ };
+
+ sdhc0_lpcg: clock-controller@5b200000 {
+ reg = <0x5b200000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_SDHC0_CLK>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "sdhc0_lpcg_per_clk",
+ "sdhc0_lpcg_ipg_clk",
+ "sdhc0_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_0>;
+ };
+
+ sdhc1_lpcg: clock-controller@5b210000 {
+ reg = <0x5b210000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_SDHC1_CLK>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "sdhc1_lpcg_per_clk",
+ "sdhc1_lpcg_ipg_clk",
+ "sdhc1_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_1>;
+ };
+
+ sdhc2_lpcg: clock-controller@5b220000 {
+ reg = <0x5b220000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_SDHC2_CLK>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "sdhc2_lpcg_per_clk",
+ "sdhc2_lpcg_ipg_clk",
+ "sdhc2_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_2>;
+ };
+
+ enet0_lpcg: clock-controller@5b230000 {
+ reg = <0x5b230000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
+ <&clk IMX_CONN_ENET0_ROOT_CLK>,
+ <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet0_ipg_root_clk",
+ "enet0_tx_clk",
+ "enet0_ahb_clk",
+ "enet0_ipg_clk",
+ "enet0_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_ENET_0>;
+ };
+
+ enet1_lpcg: clock-controller@5b240000 {
+ reg = <0x5b240000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
+ <&clk IMX_CONN_ENET1_ROOT_CLK>,
+ <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet1_ipg_root_clk",
+ "enet1_tx_clk",
+ "enet1_ahb_clk",
+ "enet1_ipg_clk",
+ "enet1_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ };
};
--
2.7.4
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next prev parent reply other threads:[~2019-09-12 15:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-12 15:30 [PATCH V3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 01/15] arm64: dts: imx8qxp: add fallback compatible string for scu pd Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 02/15] arm64: dts: imx8qxp: move scu pd node before scu clock node Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 03/15] arm64: dts: imx8qxp: orginize dts in subsystems Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 04/15] arm64: dts: imx8: add lsio lpcg clocks Dong Aisheng
2019-09-12 15:30 ` Dong Aisheng [this message]
2019-09-12 15:30 ` [PATCH V3 06/15] arm64: dts: imx8: add adma " Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 07/15] arm64: dts: imx8: switch to two cell scu clock binding Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 08/15] arm64: dts: imx8: switch to new lpcg " Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 09/15] arm64: dts: imx8qm: add lsio ss support Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 10/15] arm64: dts: imx8qm: add conn " Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 11/15] arm64: dts: imx8: split adma ss into dma and audio ss Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 12/15] arm64: dts: imx8qm: add dma ss support Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 13/15] arm64: dts: imx: add imx8qm common dts file Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 14/15] arm64: dts: imx: add imx8qm mek support Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 15/15] arm64: defconfig: " Dong Aisheng
2019-09-13 12:16 ` [PATCH V3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Oliver Graute
2019-09-13 16:43 ` Aisheng Dong
2019-09-16 11:22 ` Oliver Graute
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