[PATCH 0/9] Add SoC serial number support for i.MX6/7 SoCs

[PATCH 0/9] Add SoC serial number support for i.MX6/7 SoCs

[Anson Huang]

i.MX6/7 SoCs have 64-bit unique ID stored in OCOTP bank 0, word 1/2,
read them out as SoC serial number which can be used from userspace:

root@imx7dsabresd:~# cat /sys/devices/soc0/serial_number
0000028FF618B953

Add support for i.MX6Q/6DL/6SL/6SX/6SLL/6UL/6ULL/6ULZ/7D, as they have
same unique ID layout in OCOTP.

Anson Huang (9):
  ARM: imx: Add serial number support for i.MX6Q
  ARM: imx: Add serial number support for i.MX6DL
  ARM: imx: Add serial number support for i.MX6SLL
  ARM: imx: Add serial number support for i.MX6ULL
  ARM: imx: Add serial number support for i.MX6UL
  ARM: imx: Add serial number support for i.MX6ULZ
  ARM: imx: Add serial number support for i.MX6SL
  ARM: imx: Add serial number support for i.MX6SX
  ARM: imx: Add serial number support for i.MX7D

 arch/arm/mach-imx/cpu.c | 38 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

-- 
2.7.4


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[PATCH 1/9] ARM: imx: Add serial number support for i.MX6Q

[Anson Huang]

i.MX6Q has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx6qpdlsolox:~# cat /sys/devices/soc0/serial_number
240F31D4E1FDFCA7

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 0b137ee..3293c1d 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -1,15 +1,20 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <linux/err.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/regmap.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
 
 #include "hardware.h"
 #include "common.h"
 
+#define OCOTP_UID_H	0x420
+#define OCOTP_UID_L	0x410
+
 unsigned int __mxc_cpu_type;
 static unsigned int imx_soc_revision;
 
@@ -76,9 +81,13 @@ void __init imx_aips_allow_unprivileged_access(
 struct device * __init imx_soc_device_init(void)
 {
 	struct soc_device_attribute *soc_dev_attr;
+	const char *ocotp_compat = NULL;
 	struct soc_device *soc_dev;
 	struct device_node *root;
+	struct regmap *ocotp;
 	const char *soc_id;
+	u64 soc_uid = 0;
+	u32 val;
 	int ret;
 
 	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
@@ -128,6 +137,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6SX";
 		break;
 	case MXC_CPU_IMX6Q:
+		ocotp_compat = "fsl,imx6q-ocotp";
 		soc_id = "i.MX6Q";
 		break;
 	case MXC_CPU_IMX6UL:
@@ -153,18 +163,36 @@ struct device * __init imx_soc_device_init(void)
 	}
 	soc_dev_attr->soc_id = soc_id;
 
+	if (ocotp_compat) {
+		ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat);
+		if (IS_ERR(ocotp))
+			pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat);
+
+		regmap_read(ocotp, OCOTP_UID_H, &val);
+		soc_uid = val;
+		regmap_read(ocotp, OCOTP_UID_L, &val);
+		soc_uid <<= 32;
+		soc_uid |= val;
+	}
+
 	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
 					   (imx_soc_revision >> 4) & 0xf,
 					   imx_soc_revision & 0xf);
 	if (!soc_dev_attr->revision)
 		goto free_soc;
 
+	soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
+	if (!soc_dev_attr->serial_number)
+		goto free_rev;
+
 	soc_dev = soc_device_register(soc_dev_attr);
 	if (IS_ERR(soc_dev))
-		goto free_rev;
+		goto free_serial_number;
 
 	return soc_device_to_device(soc_dev);
 
+free_serial_number:
+	kfree(soc_dev_attr->serial_number);
 free_rev:
 	kfree(soc_dev_attr->revision);
 free_soc:
-- 
2.7.4


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[PATCH 2/9] ARM: imx: Add serial number support for i.MX6DL

[Anson Huang]

i.MX6DL has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx6qpdlsolox:~# cat /sys/devices/soc0/serial_number
706519D4D72D7859

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 3293c1d..54e5ab3 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -131,6 +131,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6SL";
 		break;
 	case MXC_CPU_IMX6DL:
+		ocotp_compat = "fsl,imx6q-ocotp";
 		soc_id = "i.MX6DL";
 		break;
 	case MXC_CPU_IMX6SX:
-- 
2.7.4


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[PATCH 3/9] ARM: imx: Add serial number support for i.MX6SLL

[Anson Huang]

i.MX6SLL has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx6sll:~# cat /sys/devices/soc0/serial_number
E766F1D25EC2D286

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 54e5ab3..f41ad93 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -151,6 +151,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6ULZ";
 		break;
 	case MXC_CPU_IMX6SLL:
+		ocotp_compat = "fsl,imx6sll-ocotp";
 		soc_id = "i.MX6SLL";
 		break;
 	case MXC_CPU_IMX7D:
-- 
2.7.4


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[PATCH 4/9] ARM: imx: Add serial number support for i.MX6ULL

[Anson Huang]

i.MX6ULL has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx6ul7d:~# cat /sys/devices/soc0/serial_number
39323198138A8620

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index f41ad93..cdb9d6d 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -145,6 +145,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6UL";
 		break;
 	case MXC_CPU_IMX6ULL:
+		ocotp_compat = "fsl,imx6ul-ocotp";
 		soc_id = "i.MX6ULL";
 		break;
 	case MXC_CPU_IMX6ULZ:
-- 
2.7.4


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[PATCH 5/9] ARM: imx: Add serial number support for i.MX6UL

[Anson Huang]

i.MX6UL has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx6ul7d:~# cat /sys/devices/soc0/serial_number
6738495762ACE932

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index cdb9d6d..1e8150e 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -142,6 +142,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6Q";
 		break;
 	case MXC_CPU_IMX6UL:
+		ocotp_compat = "fsl,imx6ul-ocotp";
 		soc_id = "i.MX6UL";
 		break;
 	case MXC_CPU_IMX6ULL:
-- 
2.7.4


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[PATCH 6/9] ARM: imx: Add serial number support for i.MX6ULZ

[Anson Huang]

i.MX6ULZ has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx6ul7d:~# cat /sys/devices/soc0/serial_number
8797AEF098CAB901

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 1e8150e..1274b52 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -150,6 +150,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6ULL";
 		break;
 	case MXC_CPU_IMX6ULZ:
+		ocotp_compat = "fsl,imx6ul-ocotp";
 		soc_id = "i.MX6ULZ";
 		break;
 	case MXC_CPU_IMX6SLL:
-- 
2.7.4


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[PATCH 7/9] ARM: imx: Add serial number support for i.MX6SL

[Anson Huang]

i.MX6SL has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx6sl:~# cat /sys/devices/soc0/serial_number
897BC6578FEAB980

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 1274b52..eb65eff 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -128,6 +128,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX53";
 		break;
 	case MXC_CPU_IMX6SL:
+		ocotp_compat = "fsl,imx6sl-ocotp";
 		soc_id = "i.MX6SL";
 		break;
 	case MXC_CPU_IMX6DL:
-- 
2.7.4


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[PATCH 8/9] ARM: imx: Add serial number support for i.MX6SX

[Anson Huang]

i.MX6SX has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx6qpdlsolox:~# cat /sys/devices/soc0/serial_number
986540983AE87921

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index eb65eff..17cfa86 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -136,6 +136,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6DL";
 		break;
 	case MXC_CPU_IMX6SX:
+		ocotp_compat = "fsl,imx6sx-ocotp";
 		soc_id = "i.MX6SX";
 		break;
 	case MXC_CPU_IMX6Q:
-- 
2.7.4


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[PATCH 9/9] ARM: imx: Add serial number support for i.MX7D

[Anson Huang]

i.MX7D has a 64-bit SoC unique ID stored in OCOTP, it can be used
as SoC serial number, see below example:

root@imx7dsabresd:~# cat /sys/devices/soc0/serial_number
0000028FF618B953

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/mach-imx/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 17cfa86..d811803 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -160,6 +160,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6SLL";
 		break;
 	case MXC_CPU_IMX7D:
+		ocotp_compat = "fsl,imx7d-ocotp";
 		soc_id = "i.MX7D";
 		break;
 	case MXC_CPU_IMX7ULP:
-- 
2.7.4


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Re: [PATCH 0/9] Add SoC serial number support for i.MX6/7 SoCs

[Shawn Guo]

On Mon, Oct 28, 2019 at 11:12:41AM +0800, Anson Huang wrote:
> i.MX6/7 SoCs have 64-bit unique ID stored in OCOTP bank 0, word 1/2,
> read them out as SoC serial number which can be used from userspace:
> 
> root@imx7dsabresd:~# cat /sys/devices/soc0/serial_number
> 0000028FF618B953
> 
> Add support for i.MX6Q/6DL/6SL/6SX/6SLL/6UL/6ULL/6ULZ/7D, as they have
> same unique ID layout in OCOTP.
> 
> Anson Huang (9):
>   ARM: imx: Add serial number support for i.MX6Q
>   ARM: imx: Add serial number support for i.MX6DL
>   ARM: imx: Add serial number support for i.MX6SLL
>   ARM: imx: Add serial number support for i.MX6ULL
>   ARM: imx: Add serial number support for i.MX6UL
>   ARM: imx: Add serial number support for i.MX6ULZ
>   ARM: imx: Add serial number support for i.MX6SL
>   ARM: imx: Add serial number support for i.MX6SX
>   ARM: imx: Add serial number support for i.MX7D

For this particular case, I think one single patch is even better than
a series.  So please squash them.

Shawn

> 
>  arch/arm/mach-imx/cpu.c | 38 +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 37 insertions(+), 1 deletion(-)
> 
> -- 
> 2.7.4
> 

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RE: [PATCH 0/9] Add SoC serial number support for i.MX6/7 SoCs

[Anson Huang]

Hi, Shawn

> On Mon, Oct 28, 2019 at 11:12:41AM +0800, Anson Huang wrote:
> > i.MX6/7 SoCs have 64-bit unique ID stored in OCOTP bank 0, word 1/2,
> > read them out as SoC serial number which can be used from userspace:
> >
> > root@imx7dsabresd:~# cat /sys/devices/soc0/serial_number
> > 0000028FF618B953
> >
> > Add support for i.MX6Q/6DL/6SL/6SX/6SLL/6UL/6ULL/6ULZ/7D, as they
> have
> > same unique ID layout in OCOTP.
> >
> > Anson Huang (9):
> >   ARM: imx: Add serial number support for i.MX6Q
> >   ARM: imx: Add serial number support for i.MX6DL
> >   ARM: imx: Add serial number support for i.MX6SLL
> >   ARM: imx: Add serial number support for i.MX6ULL
> >   ARM: imx: Add serial number support for i.MX6UL
> >   ARM: imx: Add serial number support for i.MX6ULZ
> >   ARM: imx: Add serial number support for i.MX6SL
> >   ARM: imx: Add serial number support for i.MX6SX
> >   ARM: imx: Add serial number support for i.MX7D
> 
> For this particular case, I think one single patch is even better than a series.
> So please squash them.

Done in V2.

Thanks,
Anson


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