* [PATCH 1/6] phy: socionext: Use devm_platform_ioremap_resource()
2019-11-06 10:26 [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
@ 2019-11-06 10:26 ` Kunihiko Hayashi
2019-11-06 10:26 ` [PATCH 2/6] dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from usb3-hsphy Kunihiko Hayashi
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Kunihiko Hayashi @ 2019-11-06 10:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-kernel,
Jassi Brar, linux-arm-kernel
Use devm_platform_ioremap_resource() to simplify the code.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-pcie.c | 4 +---
drivers/phy/socionext/phy-uniphier-usb3hs.c | 4 +---
drivers/phy/socionext/phy-uniphier-usb3ss.c | 4 +---
3 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index 93ffbd2..25d1d9d 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -163,7 +163,6 @@ static int uniphier_pciephy_probe(struct platform_device *pdev)
struct phy_provider *phy_provider;
struct device *dev = &pdev->dev;
struct regmap *regmap;
- struct resource *res;
struct phy *phy;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -176,8 +175,7 @@ static int uniphier_pciephy_probe(struct platform_device *pdev)
priv->dev = dev;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->base = devm_ioremap_resource(dev, res);
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c
index 50f379f..1d3f9e8 100644
--- a/drivers/phy/socionext/phy-uniphier-usb3hs.c
+++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c
@@ -309,7 +309,6 @@ static int uniphier_u3hsphy_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct uniphier_u3hsphy_priv *priv;
struct phy_provider *phy_provider;
- struct resource *res;
struct phy *phy;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -322,8 +321,7 @@ static int uniphier_u3hsphy_probe(struct platform_device *pdev)
priv->data->nparams > MAX_PHY_PARAMS))
return -EINVAL;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->base = devm_ioremap_resource(dev, res);
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
diff --git a/drivers/phy/socionext/phy-uniphier-usb3ss.c b/drivers/phy/socionext/phy-uniphier-usb3ss.c
index ec231e4..05e40a2 100644
--- a/drivers/phy/socionext/phy-uniphier-usb3ss.c
+++ b/drivers/phy/socionext/phy-uniphier-usb3ss.c
@@ -215,7 +215,6 @@ static int uniphier_u3ssphy_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct uniphier_u3ssphy_priv *priv;
struct phy_provider *phy_provider;
- struct resource *res;
struct phy *phy;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -228,8 +227,7 @@ static int uniphier_u3ssphy_probe(struct platform_device *pdev)
priv->data->nparams > MAX_PHY_PARAMS))
return -EINVAL;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->base = devm_ioremap_resource(dev, res);
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
--
2.7.4
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/6] dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from usb3-hsphy
2019-11-06 10:26 [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
2019-11-06 10:26 ` [PATCH 1/6] phy: socionext: Use devm_platform_ioremap_resource() Kunihiko Hayashi
@ 2019-11-06 10:26 ` Kunihiko Hayashi
2019-11-07 0:52 ` Rob Herring
2019-11-06 10:26 ` [PATCH 3/6] phy: uniphier-usb3ss: Add Pro5 support Kunihiko Hayashi
` (5 subsequent siblings)
7 siblings, 1 reply; 10+ messages in thread
From: Kunihiko Hayashi @ 2019-11-06 10:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-kernel,
Jassi Brar, linux-arm-kernel
This adds compatible string for Pro5 SoC that needs to manage gio clock
and reset. And Pro4 SoC uses USB2 PHY instead of USB3 HS-PHY, so this
removes Pro4 description from usb3-hsphy.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt | 13 +++++++++----
.../devicetree/bindings/phy/uniphier-usb3-hsphy.txt | 6 +++---
.../devicetree/bindings/phy/uniphier-usb3-ssphy.txt | 5 +++--
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
index 1889d3b..3cee372 100644
--- a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
+++ b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
@@ -5,14 +5,19 @@ PCIe controller implemented on Socionext UniPhier SoCs.
Required properties:
- compatible: Should contain one of the following:
+ "socionext,uniphier-pro5-pcie-phy" - for Pro5 PHY
"socionext,uniphier-ld20-pcie-phy" - for LD20 PHY
"socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY
- reg: Specifies offset and length of the register set for the device.
- #phy-cells: Must be zero.
-- clocks: A phandle to the clock gate for PCIe glue layer including
- this phy.
-- resets: A phandle to the reset line for PCIe glue layer including
- this phy.
+- clocks: A list of phandles to the clock gate for PCIe glue layer
+ including this phy.
+- clock-names: For Pro5 only, should contain the following:
+ "gio", "link" - for Pro5 SoC
+- resets: A list of phandles to the reset line for PCIe glue layer
+ including this phy.
+- reset-names: For Pro5 only, should contain the following:
+ "gio", "link" - for Pro5 SoC
Optional properties:
- socionext,syscon: A phandle to system control to set configurations
diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
index e8d8086..093d4f0 100644
--- a/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
+++ b/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
@@ -7,7 +7,7 @@ this describes about High-Speed PHY.
Required properties:
- compatible: Should contain one of the following:
- "socionext,uniphier-pro4-usb3-hsphy" - for Pro4 SoC
+ "socionext,uniphier-pro5-usb3-hsphy" - for Pro5 SoC
"socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC
"socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC
"socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC
@@ -16,13 +16,13 @@ Required properties:
- clocks: A list of phandles to the clock gate for USB3 glue layer.
According to the clock-names, appropriate clocks are required.
- clock-names: Should contain the following:
- "gio", "link" - for Pro4 SoC
+ "gio", "link" - for Pro5 SoC
"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
"phy", "link" - for others
- resets: A list of phandles to the reset control for USB3 glue layer.
According to the reset-names, appropriate resets are required.
- reset-names: Should contain the following:
- "gio", "link" - for Pro4 SoC
+ "gio", "link" - for Pro5 SoC
"phy", "link" - for others
Optional properties:
diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
index 490b815..9df2bc2 100644
--- a/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
+++ b/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
@@ -8,6 +8,7 @@ this describes about Super-Speed PHY.
Required properties:
- compatible: Should contain one of the following:
"socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
+ "socionext,uniphier-pro5-usb3-ssphy" - for Pro5 SoC
"socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
"socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
"socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
@@ -16,13 +17,13 @@ Required properties:
- clocks: A list of phandles to the clock gate for USB3 glue layer.
According to the clock-names, appropriate clocks are required.
- clock-names:
- "gio", "link" - for Pro4 SoC
+ "gio", "link" - for Pro4 and Pro5 SoC
"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
"phy", "link" - for others
- resets: A list of phandles to the reset control for USB3 glue layer.
According to the reset-names, appropriate resets are required.
- reset-names:
- "gio", "link" - for Pro4 SoC
+ "gio", "link" - for Pro4 and Pro5 SoC
"phy", "link" - for others
Optional properties:
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/6] dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from usb3-hsphy
2019-11-06 10:26 ` [PATCH 2/6] dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from usb3-hsphy Kunihiko Hayashi
@ 2019-11-07 0:52 ` Rob Herring
0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2019-11-07 0:52 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Mark Rutland, devicetree, Kunihiko Hayashi, Masami Hiramatsu,
Jassi Brar, linux-kernel, Kishon Vijay Abraham I,
Masahiro Yamada, linux-arm-kernel
On Wed, 6 Nov 2019 19:26:15 +0900, Kunihiko Hayashi wrote:
> This adds compatible string for Pro5 SoC that needs to manage gio clock
> and reset. And Pro4 SoC uses USB2 PHY instead of USB3 HS-PHY, so this
> removes Pro4 description from usb3-hsphy.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt | 13 +++++++++----
> .../devicetree/bindings/phy/uniphier-usb3-hsphy.txt | 6 +++---
> .../devicetree/bindings/phy/uniphier-usb3-ssphy.txt | 5 +++--
> 3 files changed, 15 insertions(+), 9 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/6] phy: uniphier-usb3ss: Add Pro5 support
2019-11-06 10:26 [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
2019-11-06 10:26 ` [PATCH 1/6] phy: socionext: Use devm_platform_ioremap_resource() Kunihiko Hayashi
2019-11-06 10:26 ` [PATCH 2/6] dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from usb3-hsphy Kunihiko Hayashi
@ 2019-11-06 10:26 ` Kunihiko Hayashi
2019-11-06 10:26 ` [PATCH 4/6] phy: uniphier-usb3hs: Add legacy SoC support for Pro5 Kunihiko Hayashi
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Kunihiko Hayashi @ 2019-11-06 10:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-kernel,
Jassi Brar, linux-arm-kernel
Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is
equivalent to Pro4.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-usb3ss.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/socionext/phy-uniphier-usb3ss.c b/drivers/phy/socionext/phy-uniphier-usb3ss.c
index 05e40a2..6700645 100644
--- a/drivers/phy/socionext/phy-uniphier-usb3ss.c
+++ b/drivers/phy/socionext/phy-uniphier-usb3ss.c
@@ -313,6 +313,10 @@ static const struct of_device_id uniphier_u3ssphy_match[] = {
.data = &uniphier_pro4_data,
},
{
+ .compatible = "socionext,uniphier-pro5-usb3-ssphy",
+ .data = &uniphier_pro4_data,
+ },
+ {
.compatible = "socionext,uniphier-pxs2-usb3-ssphy",
.data = &uniphier_pxs2_data,
},
--
2.7.4
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/6] phy: uniphier-usb3hs: Add legacy SoC support for Pro5
2019-11-06 10:26 [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
` (2 preceding siblings ...)
2019-11-06 10:26 ` [PATCH 3/6] phy: uniphier-usb3ss: Add Pro5 support Kunihiko Hayashi
@ 2019-11-06 10:26 ` Kunihiko Hayashi
2019-11-06 10:26 ` [PATCH 5/6] phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failure Kunihiko Hayashi
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Kunihiko Hayashi @ 2019-11-06 10:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-kernel,
Jassi Brar, linux-arm-kernel
Add legacy SoC support that needs to manage gio clock and reset.
This supports Pro5.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-usb3hs.c | 68 ++++++++++++++++++++++-------
1 file changed, 53 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c
index 1d3f9e8..bdf696e 100644
--- a/drivers/phy/socionext/phy-uniphier-usb3hs.c
+++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c
@@ -66,13 +66,14 @@ struct uniphier_u3hsphy_trim_param {
struct uniphier_u3hsphy_priv {
struct device *dev;
void __iomem *base;
- struct clk *clk, *clk_parent, *clk_ext;
- struct reset_control *rst, *rst_parent;
+ struct clk *clk, *clk_parent, *clk_ext, *clk_parent_gio;
+ struct reset_control *rst, *rst_parent, *rst_parent_gio;
struct regulator *vbus;
const struct uniphier_u3hsphy_soc_data *data;
};
struct uniphier_u3hsphy_soc_data {
+ bool is_legacy;
int nparams;
const struct uniphier_u3hsphy_param param[MAX_PHY_PARAMS];
u32 config0;
@@ -256,11 +257,20 @@ static int uniphier_u3hsphy_init(struct phy *phy)
if (ret)
return ret;
- ret = reset_control_deassert(priv->rst_parent);
+ ret = clk_prepare_enable(priv->clk_parent_gio);
if (ret)
goto out_clk_disable;
- if (!priv->data->config0 && !priv->data->config1)
+ ret = reset_control_deassert(priv->rst_parent);
+ if (ret)
+ goto out_clk_gio_disable;
+
+ ret = reset_control_deassert(priv->rst_parent_gio);
+ if (ret)
+ goto out_rst_assert;
+
+ if ((priv->data->is_legacy)
+ || (!priv->data->config0 && !priv->data->config1))
return 0;
config0 = priv->data->config0;
@@ -280,6 +290,8 @@ static int uniphier_u3hsphy_init(struct phy *phy)
out_rst_assert:
reset_control_assert(priv->rst_parent);
+out_clk_gio_disable:
+ clk_disable_unprepare(priv->clk_parent_gio);
out_clk_disable:
clk_disable_unprepare(priv->clk_parent);
@@ -290,7 +302,9 @@ static int uniphier_u3hsphy_exit(struct phy *phy)
{
struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
+ reset_control_assert(priv->rst_parent_gio);
reset_control_assert(priv->rst_parent);
+ clk_disable_unprepare(priv->clk_parent_gio);
clk_disable_unprepare(priv->clk_parent);
return 0;
@@ -325,22 +339,34 @@ static int uniphier_u3hsphy_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- priv->clk = devm_clk_get(dev, "phy");
- if (IS_ERR(priv->clk))
- return PTR_ERR(priv->clk);
+ if (!priv->data->is_legacy) {
+ priv->clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ priv->clk_ext = devm_clk_get_optional(dev, "phy-ext");
+ if (IS_ERR(priv->clk_ext))
+ return PTR_ERR(priv->clk_ext);
+
+ priv->rst = devm_reset_control_get_shared(dev, "phy");
+ if (IS_ERR(priv->rst))
+ return PTR_ERR(priv->rst);
+
+ } else {
+ priv->clk_parent_gio = devm_clk_get(dev, "gio");
+ if (IS_ERR(priv->clk_parent_gio))
+ return PTR_ERR(priv->clk_parent_gio);
+
+ priv->rst_parent_gio =
+ devm_reset_control_get_shared(dev, "gio");
+ if (IS_ERR(priv->rst_parent_gio))
+ return PTR_ERR(priv->rst_parent_gio);
+ }
priv->clk_parent = devm_clk_get(dev, "link");
if (IS_ERR(priv->clk_parent))
return PTR_ERR(priv->clk_parent);
- priv->clk_ext = devm_clk_get_optional(dev, "phy-ext");
- if (IS_ERR(priv->clk_ext))
- return PTR_ERR(priv->clk_ext);
-
- priv->rst = devm_reset_control_get_shared(dev, "phy");
- if (IS_ERR(priv->rst))
- return PTR_ERR(priv->rst);
-
priv->rst_parent = devm_reset_control_get_shared(dev, "link");
if (IS_ERR(priv->rst_parent))
return PTR_ERR(priv->rst_parent);
@@ -362,11 +388,18 @@ static int uniphier_u3hsphy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
+static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = {
+ .is_legacy = true,
+ .nparams = 0,
+};
+
static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = {
+ .is_legacy = false,
.nparams = 0,
};
static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = {
+ .is_legacy = false,
.nparams = 2,
.param = {
{ LS_SLEW, 1 },
@@ -378,6 +411,7 @@ static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = {
};
static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = {
+ .is_legacy = false,
.nparams = 0,
.trim_func = uniphier_u3hsphy_trim_ld20,
.config0 = 0x92316680,
@@ -386,6 +420,10 @@ static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = {
static const struct of_device_id uniphier_u3hsphy_match[] = {
{
+ .compatible = "socionext,uniphier-pro5-usb3-hsphy",
+ .data = &uniphier_pro5_data,
+ },
+ {
.compatible = "socionext,uniphier-pxs2-usb3-hsphy",
.data = &uniphier_pxs2_data,
},
--
2.7.4
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 5/6] phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failure
2019-11-06 10:26 [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
` (3 preceding siblings ...)
2019-11-06 10:26 ` [PATCH 4/6] phy: uniphier-usb3hs: Add legacy SoC support for Pro5 Kunihiko Hayashi
@ 2019-11-06 10:26 ` Kunihiko Hayashi
2019-11-06 10:26 ` [PATCH 6/6] phy: uniphier-pcie: Add legacy SoC support for Pro5 Kunihiko Hayashi
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Kunihiko Hayashi @ 2019-11-06 10:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-kernel,
Jassi Brar, linux-arm-kernel
In case of using default parameters, communication failure might occur
in rare cases. This sets Rx sync mode parameter to avoid the issue.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-usb3hs.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c
index bdf696e..a9bc741 100644
--- a/drivers/phy/socionext/phy-uniphier-usb3hs.c
+++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c
@@ -41,10 +41,12 @@
#define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) }
+#define RX_CHK_SYNC PHY_F(0, 5, 5) /* RX sync mode */
+#define RX_SYNC_SEL PHY_F(1, 1, 0) /* RX sync length */
#define LS_SLEW PHY_F(10, 6, 6) /* LS mode slew rate */
#define FS_LS_DRV PHY_F(10, 5, 5) /* FS/LS slew rate */
-#define MAX_PHY_PARAMS 2
+#define MAX_PHY_PARAMS 4
struct uniphier_u3hsphy_param {
struct {
@@ -395,13 +397,19 @@ static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = {
static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = {
.is_legacy = false,
- .nparams = 0,
+ .nparams = 2,
+ .param = {
+ { RX_CHK_SYNC, 1 },
+ { RX_SYNC_SEL, 1 },
+ },
};
static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = {
.is_legacy = false,
- .nparams = 2,
+ .nparams = 4,
.param = {
+ { RX_CHK_SYNC, 1 },
+ { RX_SYNC_SEL, 1 },
{ LS_SLEW, 1 },
{ FS_LS_DRV, 1 },
},
@@ -412,7 +420,11 @@ static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = {
static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = {
.is_legacy = false,
- .nparams = 0,
+ .nparams = 2,
+ .param = {
+ { RX_CHK_SYNC, 1 },
+ { RX_SYNC_SEL, 1 },
+ },
.trim_func = uniphier_u3hsphy_trim_ld20,
.config0 = 0x92316680,
.config1 = 0x00000106,
--
2.7.4
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6/6] phy: uniphier-pcie: Add legacy SoC support for Pro5
2019-11-06 10:26 [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
` (4 preceding siblings ...)
2019-11-06 10:26 ` [PATCH 5/6] phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failure Kunihiko Hayashi
@ 2019-11-06 10:26 ` Kunihiko Hayashi
2019-12-20 12:00 ` [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
2020-01-15 2:13 ` Kunihiko Hayashi
7 siblings, 0 replies; 10+ messages in thread
From: Kunihiko Hayashi @ 2019-11-06 10:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-kernel,
Jassi Brar, linux-arm-kernel
Add legacy SoC support that needs to manage gio clock and reset and to skip
setting unimplemented phy parameters. This supports Pro5.
This specifies only 1 port use because Pro5 doesn't set it in the power-on
sequence.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-pcie.c | 83 +++++++++++++++++++++++++++----
1 file changed, 72 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index 25d1d9d..cd17c70 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -19,6 +19,10 @@
#include <linux/resource.h>
/* PHY */
+#define PCL_PHY_CLKCTRL 0x0000
+#define PORT_SEL_MASK GENMASK(11, 9)
+#define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1)
+
#define PCL_PHY_TEST_I 0x2000
#define PCL_PHY_TEST_O 0x2004
#define TESTI_DAT_MASK GENMASK(13, 6)
@@ -45,13 +49,14 @@
struct uniphier_pciephy_priv {
void __iomem *base;
struct device *dev;
- struct clk *clk;
- struct reset_control *rst;
+ struct clk *clk, *clk_gio;
+ struct reset_control *rst, *rst_gio;
const struct uniphier_pciephy_soc_data *data;
};
struct uniphier_pciephy_soc_data {
bool has_syscon;
+ bool is_legacy;
};
static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv,
@@ -111,16 +116,35 @@ static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv)
static int uniphier_pciephy_init(struct phy *phy)
{
struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
+ u32 val;
int ret;
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
- ret = reset_control_deassert(priv->rst);
+ ret = clk_prepare_enable(priv->clk_gio);
if (ret)
goto out_clk_disable;
+ ret = reset_control_deassert(priv->rst);
+ if (ret)
+ goto out_clk_gio_disable;
+
+ ret = reset_control_deassert(priv->rst_gio);
+ if (ret)
+ goto out_rst_assert;
+
+ /* support only 1 port */
+ val = readl(priv->base + PCL_PHY_CLKCTRL);
+ val &= ~PORT_SEL_MASK;
+ val |= PORT_SEL_1;
+ writel(val, priv->base + PCL_PHY_CLKCTRL);
+
+ /* legacy controller doesn't have phy_reset and parameters */
+ if (priv->data->is_legacy)
+ return 0;
+
uniphier_pciephy_set_param(priv, PCL_PHY_R00,
RX_EQ_ADJ_EN, RX_EQ_ADJ_EN);
uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ,
@@ -134,6 +158,10 @@ static int uniphier_pciephy_init(struct phy *phy)
return 0;
+out_rst_assert:
+ reset_control_assert(priv->rst);
+out_clk_gio_disable:
+ clk_disable_unprepare(priv->clk_gio);
out_clk_disable:
clk_disable_unprepare(priv->clk);
@@ -144,8 +172,11 @@ static int uniphier_pciephy_exit(struct phy *phy)
{
struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
- uniphier_pciephy_assert(priv);
+ if (!priv->data->is_legacy)
+ uniphier_pciephy_assert(priv);
+ reset_control_assert(priv->rst_gio);
reset_control_assert(priv->rst);
+ clk_disable_unprepare(priv->clk_gio);
clk_disable_unprepare(priv->clk);
return 0;
@@ -179,13 +210,32 @@ static int uniphier_pciephy_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- priv->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(priv->clk))
- return PTR_ERR(priv->clk);
-
- priv->rst = devm_reset_control_get_shared(dev, NULL);
- if (IS_ERR(priv->rst))
- return PTR_ERR(priv->rst);
+ if (priv->data->is_legacy) {
+ priv->clk_gio = devm_clk_get(dev, "gio");
+ if (IS_ERR(priv->clk_gio))
+ return PTR_ERR(priv->clk_gio);
+
+ priv->rst_gio =
+ devm_reset_control_get_shared(dev, "gio");
+ if (IS_ERR(priv->rst_gio))
+ return PTR_ERR(priv->rst_gio);
+
+ priv->clk = devm_clk_get(dev, "link");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ priv->rst = devm_reset_control_get_shared(dev, "link");
+ if (IS_ERR(priv->rst))
+ return PTR_ERR(priv->rst);
+ } else {
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ priv->rst = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(priv->rst))
+ return PTR_ERR(priv->rst);
+ }
phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops);
if (IS_ERR(phy))
@@ -203,16 +253,27 @@ static int uniphier_pciephy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
+static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
+ .has_syscon = false,
+ .is_legacy = true,
+};
+
static const struct uniphier_pciephy_soc_data uniphier_ld20_data = {
.has_syscon = true,
+ .is_legacy = false,
};
static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
.has_syscon = false,
+ .is_legacy = false,
};
static const struct of_device_id uniphier_pciephy_match[] = {
{
+ .compatible = "socionext,uniphier-pro5-pcie-phy",
+ .data = &uniphier_pro5_data,
+ },
+ {
.compatible = "socionext,uniphier-ld20-pcie-phy",
.data = &uniphier_ld20_data,
},
--
2.7.4
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support
2019-11-06 10:26 [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
` (5 preceding siblings ...)
2019-11-06 10:26 ` [PATCH 6/6] phy: uniphier-pcie: Add legacy SoC support for Pro5 Kunihiko Hayashi
@ 2019-12-20 12:00 ` Kunihiko Hayashi
2020-01-15 2:13 ` Kunihiko Hayashi
7 siblings, 0 replies; 10+ messages in thread
From: Kunihiko Hayashi @ 2019-12-20 12:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mark Rutland, devicetree, Masami Hiramatsu, Jassi Brar,
linux-kernel, Kishon Vijay Abraham I, Masahiro Yamada,
Rob Herring
Hi,
Gentle ping.
Are there any comments about this series?
Thank you,
On Wed, 6 Nov 2019 19:26:13 +0900 <hayashi.kunihiko@socionext.com> wrote:
> This series adds some improvements to PHY interface drivers, and adds legacy SoC
> support that needs to manage gio clock and reset.
>
> Kunihiko Hayashi (6):
> phy: socionext: Use devm_platform_ioremap_resource()
> dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from
> usb3-hsphy
> phy: uniphier-usb3ss: Add Pro5 support
> phy: uniphier-usb3hs: Add legacy SoC support for Pro5
> phy: uniphier-usb3hs: Change Rx sync mode to avoid communication
> failure
> phy: uniphier-pcie: Add legacy SoC support for Pro5
>
> .../devicetree/bindings/phy/uniphier-pcie-phy.txt | 13 ++-
> .../bindings/phy/uniphier-usb3-hsphy.txt | 6 +-
> .../bindings/phy/uniphier-usb3-ssphy.txt | 5 +-
> drivers/phy/socionext/phy-uniphier-pcie.c | 87 ++++++++++++++++----
> drivers/phy/socionext/phy-uniphier-usb3hs.c | 92 ++++++++++++++++------
> drivers/phy/socionext/phy-uniphier-usb3ss.c | 8 +-
> 6 files changed, 163 insertions(+), 48 deletions(-)
>
> --
> 2.7.4
---
Best Regards,
Kunihiko Hayashi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support
2019-11-06 10:26 [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
` (6 preceding siblings ...)
2019-12-20 12:00 ` [PATCH 0/6] phy: socionext: Add some improvements and legacy SoC support Kunihiko Hayashi
@ 2020-01-15 2:13 ` Kunihiko Hayashi
7 siblings, 0 replies; 10+ messages in thread
From: Kunihiko Hayashi @ 2020-01-15 2:13 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, devicetree, Masami Hiramatsu, Jassi Brar,
linux-kernel, Masahiro Yamada, Rob Herring, linux-arm-kernel
Hi,
Gentle ping.
Is there any comments about this series?
Thank you,
On Wed, 6 Nov 2019 19:26:13 +0900 <hayashi.kunihiko@socionext.com> wrote:
> This series adds some improvements to PHY interface drivers, and adds legacy SoC
> support that needs to manage gio clock and reset.
>
> Kunihiko Hayashi (6):
> phy: socionext: Use devm_platform_ioremap_resource()
> dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from
> usb3-hsphy
> phy: uniphier-usb3ss: Add Pro5 support
> phy: uniphier-usb3hs: Add legacy SoC support for Pro5
> phy: uniphier-usb3hs: Change Rx sync mode to avoid communication
> failure
> phy: uniphier-pcie: Add legacy SoC support for Pro5
>
> .../devicetree/bindings/phy/uniphier-pcie-phy.txt | 13 ++-
> .../bindings/phy/uniphier-usb3-hsphy.txt | 6 +-
> .../bindings/phy/uniphier-usb3-ssphy.txt | 5 +-
> drivers/phy/socionext/phy-uniphier-pcie.c | 87 ++++++++++++++++----
> drivers/phy/socionext/phy-uniphier-usb3hs.c | 92 ++++++++++++++++------
> drivers/phy/socionext/phy-uniphier-usb3ss.c | 8 +-
> 6 files changed, 163 insertions(+), 48 deletions(-)
>
> --
> 2.7.4
---
Best Regards,
Kunihiko Hayashi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread