From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v6 05/17] drm/mediatek: add mmsys private data for ddp path config
Date: Fri, 3 Jan 2020 11:12:16 +0800 [thread overview]
Message-ID: <1578021148-32413-6-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1578021148-32413-1-git-send-email-yongqiang.niu@mediatek.com>
This patch add mmsys private data for ddp path config
all these register offset and value will be different in future SOC
add these define into mmsys private data
u32 ovl0_mout_en;
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 ++++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 37 ++++++++++++++++++++++++---------
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 6 ++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 +++
5 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index e47cf84..9aacbcf 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -44,6 +44,7 @@ struct mtk_drm_crtc {
bool pending_planes;
struct regmap *config_regs;
+ const struct mtk_mmsys_reg_data *mmsys_reg_data;
struct mtk_disp_mutex *mutex;
unsigned int ddp_comp_nr;
struct mtk_ddp_comp **ddp_comp;
@@ -283,6 +284,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
+ mtk_crtc->mmsys_reg_data,
mtk_crtc->ddp_comp[i]->id,
mtk_crtc->ddp_comp[i + 1]->id);
mtk_disp_mutex_add_comp(mtk_crtc->mutex,
@@ -340,6 +342,7 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
mtk_disp_mutex_disable(mtk_crtc->mutex);
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
+ mtk_crtc->mmsys_reg_data,
mtk_crtc->ddp_comp[i]->id,
mtk_crtc->ddp_comp[i + 1]->id);
mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
@@ -649,6 +652,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
return -ENOMEM;
mtk_crtc->config_regs = priv->config_regs;
+ mtk_crtc->mmsys_reg_data = priv->data->reg_data;
mtk_crtc->ddp_comp_nr = path_len;
mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
sizeof(*mtk_crtc->ddp_comp),
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index ae08fc4..b279204 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -168,6 +168,10 @@ struct mtk_ddp {
const struct mtk_ddp_data *data;
};
+struct mtk_mmsys_reg_data {
+ u32 ovl0_mout_en;
+};
+
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
@@ -246,17 +250,26 @@ struct mtk_ddp {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
};
-static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
+const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = {
+ .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN,
+};
+
+const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data = {
+ .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
+};
+
+static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data,
+ enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
unsigned int *addr)
{
unsigned int value;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ *addr = data->ovl0_mout_en;
value = OVL0_MOUT_EN_COLOR0;
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ *addr = data->ovl0_mout_en;
value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
@@ -325,7 +338,8 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
return value;
}
-static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
+static unsigned int mtk_ddp_sel_in(const struct mtk_mmsys_reg_data *data,
+ enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
unsigned int *addr)
{
@@ -386,7 +400,8 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
return value;
}
-static unsigned int mtk_ddp_sout_sel(enum mtk_ddp_comp_id cur,
+static unsigned int mtk_ddp_sout_sel(const struct mtk_mmsys_reg_data *data,
+ enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
unsigned int *addr)
{
@@ -406,35 +421,37 @@ static unsigned int mtk_ddp_sout_sel(enum mtk_ddp_comp_id cur,
}
void mtk_ddp_add_comp_to_path(struct regmap *config_regs,
+ const struct mtk_mmsys_reg_data *reg_data,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
unsigned int addr, value;
- value = mtk_ddp_mout_en(cur, next, &addr);
+ value = mtk_ddp_mout_en(reg_data, cur, next, &addr);
if (value)
regmap_update_bits(config_regs, addr, value, value);
- value = mtk_ddp_sout_sel(cur, next, &addr);
+ value = mtk_ddp_sout_sel(reg_data, cur, next, &addr);
if (value)
regmap_update_bits(config_regs, addr, value, value);
- value = mtk_ddp_sel_in(cur, next, &addr);
+ value = mtk_ddp_sel_in(reg_data, cur, next, &addr);
if (value)
regmap_update_bits(config_regs, addr, value, value);
}
void mtk_ddp_remove_comp_from_path(struct regmap *config_regs,
+ const struct mtk_mmsys_reg_data *reg_data,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
unsigned int addr, value;
- value = mtk_ddp_mout_en(cur, next, &addr);
+ value = mtk_ddp_mout_en(reg_data, cur, next, &addr);
if (value)
regmap_update_bits(config_regs, addr, value, 0);
- value = mtk_ddp_sel_in(cur, next, &addr);
+ value = mtk_ddp_sel_in(reg_data, cur, next, &addr);
if (value)
regmap_update_bits(config_regs, addr, value, 0);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
index 01ff8b6..75fa56e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
@@ -11,11 +11,17 @@
struct regmap;
struct device;
struct mtk_disp_mutex;
+struct mtk_mmsys_reg_data;
+
+extern const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data;
+extern const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data;
void mtk_ddp_add_comp_to_path(struct regmap *config_regs,
+ const struct mtk_mmsys_reg_data *reg_data,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
void mtk_ddp_remove_comp_from_path(struct regmap *config_regs,
+ const struct mtk_mmsys_reg_data *reg_data,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f69af42..e3293cf8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -185,6 +185,7 @@ static int mtk_atomic_commit(struct drm_device *drm,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
+ .reg_data = &mt2701_mmsys_reg_data,
.shadow_register = true,
.clk_drv_name = "clk-mt2701-mm",
};
@@ -196,6 +197,7 @@ static int mtk_atomic_commit(struct drm_device *drm,
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .reg_data = &mt8173_mmsys_reg_data,
.clk_drv_name = "clk-mt2712-mm",
};
@@ -204,6 +206,7 @@ static int mtk_atomic_commit(struct drm_device *drm,
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .reg_data = &mt8173_mmsys_reg_data,
.clk_drv_name = "clk-mt8173-mm",
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 8fe9136..9d87441 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -7,6 +7,7 @@
#define MTK_DRM_DRV_H
#include <linux/io.h>
+#include "mtk_drm_ddp.h"
#include "mtk_drm_ddp_comp.h"
#define MAX_CRTC 3
@@ -28,6 +29,8 @@ struct mtk_mmsys_driver_data {
const enum mtk_ddp_comp_id *third_path;
unsigned int third_len;
+ const struct mtk_mmsys_reg_data *reg_data;
+
bool shadow_register;
const char *clk_drv_name;
};
--
1.8.1.1.dirty
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next prev parent reply other threads:[~2020-01-03 3:20 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-03 3:12 [RESEND PATCH v6 00/17] add drm support for MT8183 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 01/17] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display Yongqiang Niu
2020-01-03 5:10 ` CK Hu
2020-01-03 22:26 ` Rob Herring
2020-01-03 3:12 ` [RESEND PATCH v6 02/17] arm64: dts: add display nodes for mt8183 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 03/17] drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in Yongqiang Niu
2020-01-03 5:36 ` CK Hu
2020-01-03 3:12 ` [RESEND PATCH v6 04/17] drm/mediatek: make sout select function format same with select input Yongqiang Niu
2020-01-03 5:44 ` CK Hu
2020-01-03 3:12 ` Yongqiang Niu [this message]
2020-01-03 3:12 ` [RESEND PATCH v6 06/17] drm/mediatek: add private data for rdma1 to dpi0 connection Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 07/17] drm/mediatek: add private data for rdma1 to dsi0 connection Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 08/17] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 09/17] drm/mediatek: add connection from OVL0 to OVL_2L0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 10/17] drm/mediatek: add connection from RDMA0 to COLOR0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 11/17] drm/mediatek: add connection from RDMA1 to DSI0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 12/17] drm/mediatek: add connection from OVL_2L0 to RDMA0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 13/17] drm/mediatek: add connection from OVL_2L1 to RDMA1 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 14/17] drm/mediatek: add connection from DITHER0 to DSI0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 15/17] drm/mediatek: add connection from RDMA0 " Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 16/17] drm/mediatek: add fifo_size into rdma private data Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 17/17] drm/mediatek: add support for mediatek SOC MT8183 Yongqiang Niu
2020-01-03 4:58 ` [RESEND PATCH v6 00/17] add drm support for MT8183 CK Hu
2020-03-26 14:57 ` CK Hu
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