* [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller to json-schema
@ 2020-04-28 6:34 Kunihiko Hayashi
2020-04-28 6:34 ` [PATCH 2/3] dt-bindings: phy: Convert UniPhier USB2-PHY " Kunihiko Hayashi
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Kunihiko Hayashi @ 2020-04-28 6:34 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, linux-kernel, linux-arm-kernel
Convert the UniPhier PCIe-PHY controller to DT schema format.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../bindings/phy/socionext,uniphier-pcie-phy.yaml | 77 ++++++++++++++++++++++
.../devicetree/bindings/phy/uniphier-pcie-phy.txt | 36 ----------
2 files changed, 77 insertions(+), 36 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml
new file mode 100644
index 0000000..86f4909
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier PCIe PHY
+
+description: |
+ This describes the devicetree bindings for PHY interface built into
+ PCIe controller implemented on Socionext UniPhier SoCs.
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-pro5-pcie-phy
+ - socionext,uniphier-ld20-pcie-phy
+ - socionext,uniphier-pxs3-pcie-phy
+
+ reg:
+ description: PHY register region (offset and length)
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for others
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for others
+
+ socionext,syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to system control to set configurations for phy
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie_phy: phy@66038000 {
+ compatible = "socionext,uniphier-ld20-pcie-phy";
+ reg = <0x66038000 0x4000>;
+ #phy-cells = <0>;
+ clock-names = "link";
+ clocks = <&sys_clk 24>;
+ reset-names = "link";
+ resets = <&sys_rst 24>;
+ socionext,syscon = <&soc_glue>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
deleted file mode 100644
index 3cee372..0000000
--- a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Socionext UniPhier PCIe PHY bindings
-
-This describes the devicetree bindings for PHY interface built into
-PCIe controller implemented on Socionext UniPhier SoCs.
-
-Required properties:
-- compatible: Should contain one of the following:
- "socionext,uniphier-pro5-pcie-phy" - for Pro5 PHY
- "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY
- "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY
-- reg: Specifies offset and length of the register set for the device.
-- #phy-cells: Must be zero.
-- clocks: A list of phandles to the clock gate for PCIe glue layer
- including this phy.
-- clock-names: For Pro5 only, should contain the following:
- "gio", "link" - for Pro5 SoC
-- resets: A list of phandles to the reset line for PCIe glue layer
- including this phy.
-- reset-names: For Pro5 only, should contain the following:
- "gio", "link" - for Pro5 SoC
-
-Optional properties:
-- socionext,syscon: A phandle to system control to set configurations
- for phy.
-
-Refer to phy/phy-bindings.txt for the generic PHY binding properties.
-
-Example:
- pcie_phy: phy@66038000 {
- compatible = "socionext,uniphier-ld20-pcie-phy";
- reg = <0x66038000 0x4000>;
- #phy-cells = <0>;
- clocks = <&sys_clk 24>;
- resets = <&sys_rst 24>;
- socionext,syscon = <&soc_glue>;
- };
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] dt-bindings: phy: Convert UniPhier USB2-PHY controller to json-schema
2020-04-28 6:34 [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller to json-schema Kunihiko Hayashi
@ 2020-04-28 6:34 ` Kunihiko Hayashi
2020-05-12 2:04 ` Rob Herring
2020-04-28 6:34 ` [PATCH 3/3] dt-bindings: phy: Convert UniPhier USB3-PHY conroller " Kunihiko Hayashi
2020-05-12 2:03 ` [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller " Rob Herring
2 siblings, 1 reply; 6+ messages in thread
From: Kunihiko Hayashi @ 2020-04-28 6:34 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, linux-kernel, linux-arm-kernel
Convert the UniPhier USB2-PHY conroller to DT schema format.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../bindings/phy/socionext,uniphier-usb2-phy.yaml | 85 ++++++++++++++++++++++
.../devicetree/bindings/phy/uniphier-usb2-phy.txt | 45 ------------
2 files changed, 85 insertions(+), 45 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml
new file mode 100644
index 0000000..479b203
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier USB2 PHY
+
+description: |
+ This describes the devicetree bindings for PHY interface built into
+ USB2 controller implemented on Socionext UniPhier SoCs.
+ Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
+ controller doesn't include its own High-Speed PHY. This needs to specify
+ USB2 PHY instead of USB3 HS-PHY.
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-pro4-usb2-phy
+ - socionext,uniphier-ld11-usb2-phy
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^phy@[0-9]+$":
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+ description:
+ The ID number for the PHY
+
+ "#phy-cells":
+ const: 0
+
+ required:
+ - reg
+ - "#phy-cells"
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ // The UniPhier usb2-phy should be a subnode of a "syscon" compatible node.
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ usb-controller {
+ compatible = "socionext,uniphier-ld11-usb2-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_phy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ usb_phy2: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt
deleted file mode 100644
index b43b282..0000000
--- a/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Socionext UniPhier USB2 PHY
-
-This describes the devicetree bindings for PHY interface built into
-USB2 controller implemented on Socionext UniPhier SoCs.
-
-Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
-controller doesn't include its own High-Speed PHY. This needs to specify
-USB2 PHY instead of USB3 HS-PHY.
-
-Required properties:
-- compatible: Should contain one of the following:
- "socionext,uniphier-pro4-usb2-phy" - for Pro4 SoC
- "socionext,uniphier-ld11-usb2-phy" - for LD11 SoC
-
-Sub-nodes:
-Each PHY should be represented as a sub-node.
-
-Sub-nodes required properties:
-- #phy-cells: Should be 0.
-- reg: The number of the PHY.
-
-Sub-nodes optional properties:
-- vbus-supply: A phandle to the regulator for USB VBUS.
-
-Refer to phy/phy-bindings.txt for the generic PHY binding properties.
-
-Example:
- soc-glue@5f800000 {
- ...
- usb-phy {
- compatible = "socionext,uniphier-ld11-usb2-phy";
- usb_phy0: phy@0 {
- reg = <0>;
- #phy-cells = <0>;
- };
- ...
- };
- };
-
- usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- ...
- phy-names = "usb";
- phys = <&usb_phy0>;
- };
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] dt-bindings: phy: Convert UniPhier USB3-PHY conroller to json-schema
2020-04-28 6:34 [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller to json-schema Kunihiko Hayashi
2020-04-28 6:34 ` [PATCH 2/3] dt-bindings: phy: Convert UniPhier USB2-PHY " Kunihiko Hayashi
@ 2020-04-28 6:34 ` Kunihiko Hayashi
2020-05-12 2:04 ` Rob Herring
2020-05-12 2:03 ` [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller " Rob Herring
2 siblings, 1 reply; 6+ messages in thread
From: Kunihiko Hayashi @ 2020-04-28 6:34 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, linux-kernel, linux-arm-kernel
Convert the UniPhier USB3-PHY controller for SS/HS to DT schema format.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../phy/socionext,uniphier-usb3hs-phy.yaml | 104 +++++++++++++++++++++
.../phy/socionext,uniphier-usb3ss-phy.yaml | 97 +++++++++++++++++++
.../bindings/phy/uniphier-usb3-hsphy.txt | 69 --------------
.../bindings/phy/uniphier-usb3-ssphy.txt | 58 ------------
4 files changed, 201 insertions(+), 127 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
new file mode 100644
index 0000000..a92a034
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier USB3 High-Speed (HS) PHY
+
+description: |
+ This describes the devicetree bindings for PHY interfaces built into
+ USB3 controller implemented on Socionext UniPhier SoCs.
+ Although the controller includes High-Speed PHY and Super-Speed PHY,
+ this describes about High-Speed PHY.
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-pro5-usb3-hsphy
+ - socionext,uniphier-pxs2-usb3-hsphy
+ - socionext,uniphier-ld20-usb3-hsphy
+ - socionext,uniphier-pxs3-usb3-hsphy
+
+ reg:
+ description: PHY register region (offset and length)
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ oneOf:
+ - const: link # for PXs2
+ - items: # for PXs3
+ - const: link
+ - const: phy
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: link
+ - const: phy
+
+ vbus-supply:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to the regulator for USB VBUS
+
+ nvmem-cells:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandles to nvmem cell that contains the trimming data.
+ Available only for HS-PHY implemented on LD20 and PXs3, and
+ if unspecified, default value is used.
+
+ nvmem-cell-names:
+ items:
+ - const: rterm
+ - const: sel_t
+ - const: hs_i
+ description:
+ Should be the following names, which correspond to each nvmem-cells.
+ All of the 3 parameters associated with the above names are
+ required for each port, if any one is omitted, the trimming data
+ of the port will not be set at all.
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ usb-glue@65b00000 {
+ compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ usb_hsphy0: hs-phy@200 {
+ compatible = "socionext,uniphier-ld20-usb3-hsphy";
+ reg = <0x200 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 16>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 16>;
+ vbus-supply = <&usb_vbus0>;
+ nvmem-cell-names = "rterm", "sel_t", "hs_i";
+ nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml
new file mode 100644
index 0000000..ed67707
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier USB3 Super-Speed (SS) PHY
+
+description: |
+ This describes the devicetree bindings for PHY interfaces built into
+ USB3 controller implemented on Socionext UniPhier SoCs.
+ Although the controller includes High-Speed PHY and Super-Speed PHY,
+ this describes about Super-Speed PHY.
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-pro4-usb3-ssphy
+ - socionext,uniphier-pro5-usb3-ssphy
+ - socionext,uniphier-pxs2-usb3-ssphy
+ - socionext,uniphier-ld20-usb3-ssphy
+ - socionext,uniphier-pxs3-usb3-ssphy
+
+ reg:
+ description: PHY register region (offset and length)
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ oneOf:
+ - items: # for Pro4, Pro5
+ - const: gio
+ - const: link
+ - items: # for PXs3 with phy-ext
+ - const: link
+ - const: phy
+ - const: phy-ext
+ - items: # for others
+ - const: link
+ - const: phy
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ oneOf:
+ - items: # for Pro4,Pro5
+ - const: gio
+ - const: link
+ - items: # for others
+ - const: link
+ - const: phy
+
+ vbus-supply:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to the regulator for USB VBUS
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vbus-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ usb-glue@65b00000 {
+ compatible = "socionext,uniphier-ld20-dwc3-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ usb_ssphy0: ss-phy@300 {
+ compatible = "socionext,uniphier-ld20-usb3-ssphy";
+ reg = <0x300 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 16>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 16>;
+ vbus-supply = <&usb_vbus0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
deleted file mode 100644
index 093d4f0..0000000
--- a/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-Socionext UniPhier USB3 High-Speed (HS) PHY
-
-This describes the devicetree bindings for PHY interfaces built into
-USB3 controller implemented on Socionext UniPhier SoCs.
-Although the controller includes High-Speed PHY and Super-Speed PHY,
-this describes about High-Speed PHY.
-
-Required properties:
-- compatible: Should contain one of the following:
- "socionext,uniphier-pro5-usb3-hsphy" - for Pro5 SoC
- "socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC
- "socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC
- "socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC
-- reg: Specifies offset and length of the register set for the device.
-- #phy-cells: Should be 0.
-- clocks: A list of phandles to the clock gate for USB3 glue layer.
- According to the clock-names, appropriate clocks are required.
-- clock-names: Should contain the following:
- "gio", "link" - for Pro5 SoC
- "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
- "phy", "link" - for others
-- resets: A list of phandles to the reset control for USB3 glue layer.
- According to the reset-names, appropriate resets are required.
-- reset-names: Should contain the following:
- "gio", "link" - for Pro5 SoC
- "phy", "link" - for others
-
-Optional properties:
-- vbus-supply: A phandle to the regulator for USB VBUS.
-- nvmem-cells: Phandles to nvmem cell that contains the trimming data.
- Available only for HS-PHY implemented on LD20 and PXs3, and
- if unspecified, default value is used.
-- nvmem-cell-names: Should be the following names, which correspond to
- each nvmem-cells.
- All of the 3 parameters associated with the following names are
- required for each port, if any one is omitted, the trimming data
- of the port will not be set at all.
- "rterm", "sel_t", "hs_i" - Each cell name for phy parameters
-
-Refer to phy/phy-bindings.txt for the generic PHY binding properties.
-
-Example:
-
- usb-glue@65b00000 {
- compatible = "socionext,uniphier-ld20-dwc3-glue",
- "simple-mfd";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x65b00000 0x400>;
-
- usb_vbus0: regulator {
- ...
- };
-
- usb_hsphy0: hs-phy@200 {
- compatible = "socionext,uniphier-ld20-usb3-hsphy";
- reg = <0x200 0x10>;
- #phy-cells = <0>;
- clock-names = "link", "phy";
- clocks = <&sys_clk 14>, <&sys_clk 16>;
- reset-names = "link", "phy";
- resets = <&sys_rst 14>, <&sys_rst 16>;
- vbus-supply = <&usb_vbus0>;
- nvmem-cell-names = "rterm", "sel_t", "hs_i";
- nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
- <&usb_hs_i0>;
- };
- ...
- };
diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
deleted file mode 100644
index 9df2bc2..0000000
--- a/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-Socionext UniPhier USB3 Super-Speed (SS) PHY
-
-This describes the devicetree bindings for PHY interfaces built into
-USB3 controller implemented on Socionext UniPhier SoCs.
-Although the controller includes High-Speed PHY and Super-Speed PHY,
-this describes about Super-Speed PHY.
-
-Required properties:
-- compatible: Should contain one of the following:
- "socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
- "socionext,uniphier-pro5-usb3-ssphy" - for Pro5 SoC
- "socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
- "socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
- "socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
-- reg: Specifies offset and length of the register set for the device.
-- #phy-cells: Should be 0.
-- clocks: A list of phandles to the clock gate for USB3 glue layer.
- According to the clock-names, appropriate clocks are required.
-- clock-names:
- "gio", "link" - for Pro4 and Pro5 SoC
- "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
- "phy", "link" - for others
-- resets: A list of phandles to the reset control for USB3 glue layer.
- According to the reset-names, appropriate resets are required.
-- reset-names:
- "gio", "link" - for Pro4 and Pro5 SoC
- "phy", "link" - for others
-
-Optional properties:
-- vbus-supply: A phandle to the regulator for USB VBUS.
-
-Refer to phy/phy-bindings.txt for the generic PHY binding properties.
-
-Example:
-
- usb-glue@65b00000 {
- compatible = "socionext,uniphier-ld20-dwc3-glue",
- "simple-mfd";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x65b00000 0x400>;
-
- usb_vbus0: regulator {
- ...
- };
-
- usb_ssphy0: ss-phy@300 {
- compatible = "socionext,uniphier-ld20-usb3-ssphy";
- reg = <0x300 0x10>;
- #phy-cells = <0>;
- clock-names = "link", "phy";
- clocks = <&sys_clk 14>, <&sys_clk 16>;
- reset-names = "link", "phy";
- resets = <&sys_rst 14>, <&sys_rst 16>;
- vbus-supply = <&usb_vbus0>;
- };
- ...
- };
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller to json-schema
2020-04-28 6:34 [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller to json-schema Kunihiko Hayashi
2020-04-28 6:34 ` [PATCH 2/3] dt-bindings: phy: Convert UniPhier USB2-PHY " Kunihiko Hayashi
2020-04-28 6:34 ` [PATCH 3/3] dt-bindings: phy: Convert UniPhier USB3-PHY conroller " Kunihiko Hayashi
@ 2020-05-12 2:03 ` Rob Herring
2 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2020-05-12 2:03 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: devicetree, linux-kernel, Kishon Vijay Abraham I,
Masahiro Yamada, Rob Herring, linux-arm-kernel
On Tue, 28 Apr 2020 15:34:48 +0900, Kunihiko Hayashi wrote:
> Convert the UniPhier PCIe-PHY controller to DT schema format.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> .../bindings/phy/socionext,uniphier-pcie-phy.yaml | 77 ++++++++++++++++++++++
> .../devicetree/bindings/phy/uniphier-pcie-phy.txt | 36 ----------
> 2 files changed, 77 insertions(+), 36 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
>
Applied, thanks!
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/3] dt-bindings: phy: Convert UniPhier USB2-PHY controller to json-schema
2020-04-28 6:34 ` [PATCH 2/3] dt-bindings: phy: Convert UniPhier USB2-PHY " Kunihiko Hayashi
@ 2020-05-12 2:04 ` Rob Herring
0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2020-05-12 2:04 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: devicetree, linux-kernel, Kishon Vijay Abraham I,
Masahiro Yamada, Rob Herring, linux-arm-kernel
On Tue, 28 Apr 2020 15:34:49 +0900, Kunihiko Hayashi wrote:
> Convert the UniPhier USB2-PHY conroller to DT schema format.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> .../bindings/phy/socionext,uniphier-usb2-phy.yaml | 85 ++++++++++++++++++++++
> .../devicetree/bindings/phy/uniphier-usb2-phy.txt | 45 ------------
> 2 files changed, 85 insertions(+), 45 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] dt-bindings: phy: Convert UniPhier USB3-PHY conroller to json-schema
2020-04-28 6:34 ` [PATCH 3/3] dt-bindings: phy: Convert UniPhier USB3-PHY conroller " Kunihiko Hayashi
@ 2020-05-12 2:04 ` Rob Herring
0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2020-05-12 2:04 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: devicetree, linux-kernel, Kishon Vijay Abraham I,
Masahiro Yamada, Rob Herring, linux-arm-kernel
On Tue, 28 Apr 2020 15:34:50 +0900, Kunihiko Hayashi wrote:
> Convert the UniPhier USB3-PHY controller for SS/HS to DT schema format.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> .../phy/socionext,uniphier-usb3hs-phy.yaml | 104 +++++++++++++++++++++
> .../phy/socionext,uniphier-usb3ss-phy.yaml | 97 +++++++++++++++++++
> .../bindings/phy/uniphier-usb3-hsphy.txt | 69 --------------
> .../bindings/phy/uniphier-usb3-ssphy.txt | 58 ------------
> 4 files changed, 201 insertions(+), 127 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
> delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-05-12 2:04 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-28 6:34 [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller to json-schema Kunihiko Hayashi
2020-04-28 6:34 ` [PATCH 2/3] dt-bindings: phy: Convert UniPhier USB2-PHY " Kunihiko Hayashi
2020-05-12 2:04 ` Rob Herring
2020-04-28 6:34 ` [PATCH 3/3] dt-bindings: phy: Convert UniPhier USB3-PHY conroller " Kunihiko Hayashi
2020-05-12 2:04 ` Rob Herring
2020-05-12 2:03 ` [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller " Rob Herring
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