From: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
To: MyungJoo Ham <myungjoo.ham@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
"Rob Herring" <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Nishanth Menon <nm@ti.com>, "Stephen Boyd" <sboyd@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>
Cc: devicetree@vger.kernel.org,
"Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>,
srv_heupstream@mediatek.com, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 8/8] arm64: dts: mediatek: add cpufreq and cci devfreq nodes for mt8183
Date: Fri, 10 Jul 2020 10:31:24 +0800 [thread overview]
Message-ID: <1594348284-14199-9-git-send-email-andrew-sh.cheng@mediatek.com> (raw)
In-Reply-To: <1594348284-14199-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
add cpufreq and cci devfreq nodes for mt8183
base on regulator node
https://patchwork.kernel.org/patch/11500339/
Now queued for v5.7-next/dts64
Change-Id: I9d7d8f9ec9bda2b70ef50a54cfbf151afc734314
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 245 ++++++++++++++++++++++++++++
2 files changed, 281 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index afd6ddbcbdf2..8f738c6d5169 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -378,6 +378,42 @@
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu0 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu4 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu5 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu6 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index e6193c4f1684..8961cd61bc3a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -32,6 +32,219 @@
i2c11 = &i2c11;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <650000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <687500>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <718750>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <756250>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <818750>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <868750>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <893750>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <906250>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <943750>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ }; };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <700000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <725000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <750000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <775000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <825000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <875000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <900000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <912500>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <950000>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ cci_opp: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci_clock";
+ operating-points-v2 = <&cci_opp>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -74,6 +287,10 @@
reg = <0x000>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -84,6 +301,10 @@
reg = <0x001>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -94,6 +315,10 @@
reg = <0x002>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -104,6 +329,10 @@
reg = <0x003>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -114,6 +343,10 @@
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -124,6 +357,10 @@
reg = <0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -134,6 +371,10 @@
reg = <0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -144,6 +385,10 @@
reg = <0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
--
2.12.5
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prev parent reply other threads:[~2020-07-10 2:43 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-10 2:31 [PATCH v7 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 1/8] PM / devfreq: Add cpu based scaling support to passive_governor Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 2/8] cpufreq: mediatek: Enable clock and regulator Andrew-sh.Cheng
2020-07-13 9:39 ` Viresh Kumar
2020-07-14 13:18 ` andrew-sh.cheng
2020-07-15 3:38 ` Viresh Kumar
2020-07-10 2:31 ` [PATCH v7 3/8] dt-bindings: devfreq: add compatible for mt8183 cci devfreq Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 4/8] devfreq: add mediatek " Andrew-sh.Cheng
2020-07-10 6:43 ` andrew-sh.cheng
2020-07-10 2:31 ` [PATCH v7 5/8] opp: Modify opp API, dev_pm_opp_get_freq(), find freq in opp, even it is disabled Andrew-sh.Cheng
2020-07-13 9:42 ` Viresh Kumar
2020-07-16 11:28 ` andrew-sh.cheng
2020-07-10 2:31 ` [PATCH v7 6/8] cpufreq: mediatek: add opp notification for SVS support Andrew-sh.Cheng
2020-07-10 2:31 ` [PATCH v7 7/8] devfreq: mediatek: cci devfreq register " Andrew-sh.Cheng
2020-07-10 2:31 ` Andrew-sh.Cheng [this message]
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