* [PATCH v2 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM
@ 2020-12-03 3:06 Liu Ying
2020-12-03 3:06 ` [PATCH v2 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding Liu Ying
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Liu Ying @ 2020-12-03 3:06 UTC (permalink / raw)
To: linux-arm-kernel, dri-devel, devicetree, linux-kernel
Cc: p.zabel, tzimmermann, airlied, festevam, s.hauer,
maarten.lankhorst, mripard, robh+dt, linux-imx, daniel,
laurentiu.palcu, shawnguo, kernel
Hi,
This patch set introduces i.MX8qm/qxp Display Processing Unit(DPU) DRM support.
DPU is comprised of a blit engine for 2D graphics, a display controller
and a command sequencer. Outside of DPU, optional prefetch engines can
fetch data from memory prior to some DPU fetchunits of blit engine and
display controller. The pre-fetchers support linear formats and Vivante
GPU tile formats.
Reference manual can be found at:
https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
This patch set adds kernel modesetting support for the display controller part.
It supports two CRTCs per display controller, several planes, prefetch
engines and some properties of CRTC and plane. Currently, the registers of
the controller is accessed without command sequencer involved, instead just by
using CPU. DRM connectors would be created from the DPU KMS driver.
If people want to try this series with i.MX8qxp, clock patches can be found at:
https://www.spinics.net/lists/arm-kernel/msg859763.html
and, power domain patches have already landed in Shawn's
i.MX for-next git branch.
This version drops the device tree patches because we'll use new dt binding
way to support i.MX8qm/qxp clocks. It depends on the below series to do basic
conversions for the platforms which has not landed yet:
https://www.spinics.net/lists/linux-mmc/msg61965.html
I will send other patch sets to add downstream bridges(embedded in i.MX8qxp)
to support LVDS displays.
A brief look at the pipe:
prefetch eng -> DPU -> pixel combiner -> pixel link -> pixel to DPI(pxl2dpi) ->
LVDS display bridge(LDB)
Patch 1 ~ 3 add dt-bindings for DPU and prefetch engines.
Patch 4 is a minor improvement of a macro to suppress warning as the KMS driver
uses it.
Patch 5 introduces the DPU DRM support.
Patch 6 updates MAINTAINERS.
Welcome comments, thanks.
v1->v2:
* Test this patch set also with i.MX8qm LVDS displays.
* Drop the device tree patches because we'll use new dt binding way to
support i.MX8qm/qxp clocks. This depends on a not-yet-landed patch set
to do basic conversions for the platforms.
* Fix dt binding yamllint warnings.
* Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm in DPU's
dt binding documentation.
* Use new dt binding way to add clocks in the dt binding examples.
* Address several comments from Laurentiu on the DPU DRM patch.
Liu Ying (6):
dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding
dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding
drm/atomic: Avoid unused-but-set-variable warning on
for_each_old_plane_in_state
drm/imx: Introduce i.MX8qm/qxp DPU DRM
MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver
.../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++
.../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 416 +++++++++
.../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 ++
MAINTAINERS | 9 +
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dpu/Kconfig | 10 +
drivers/gpu/drm/imx/dpu/Makefile | 10 +
drivers/gpu/drm/imx/dpu/dpu-constframe.c | 170 ++++
drivers/gpu/drm/imx/dpu/dpu-core.c | 881 ++++++++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-crtc.c | 926 +++++++++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-crtc.h | 62 ++
drivers/gpu/drm/imx/dpu/dpu-disengcfg.c | 114 +++
drivers/gpu/drm/imx/dpu/dpu-dprc.c | 721 ++++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-dprc.h | 40 +
drivers/gpu/drm/imx/dpu/dpu-drv.c | 297 +++++++
drivers/gpu/drm/imx/dpu/dpu-drv.h | 28 +
drivers/gpu/drm/imx/dpu/dpu-extdst.c | 296 +++++++
drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c | 291 +++++++
drivers/gpu/drm/imx/dpu/dpu-fetcheco.c | 221 +++++
drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c | 151 ++++
drivers/gpu/drm/imx/dpu/dpu-fetchunit.c | 609 ++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-fetchunit.h | 191 +++++
drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c | 247 ++++++
drivers/gpu/drm/imx/dpu/dpu-framegen.c | 392 +++++++++
drivers/gpu/drm/imx/dpu/dpu-gammacor.c | 220 +++++
drivers/gpu/drm/imx/dpu/dpu-hscaler.c | 272 ++++++
drivers/gpu/drm/imx/dpu/dpu-kms.c | 543 ++++++++++++
drivers/gpu/drm/imx/dpu/dpu-kms.h | 23 +
drivers/gpu/drm/imx/dpu/dpu-layerblend.c | 345 ++++++++
drivers/gpu/drm/imx/dpu/dpu-plane.c | 703 ++++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-plane.h | 56 ++
drivers/gpu/drm/imx/dpu/dpu-prg.c | 433 ++++++++++
drivers/gpu/drm/imx/dpu/dpu-prg.h | 45 +
drivers/gpu/drm/imx/dpu/dpu-prv.h | 203 +++++
drivers/gpu/drm/imx/dpu/dpu-tcon.c | 249 ++++++
drivers/gpu/drm/imx/dpu/dpu-vscaler.c | 305 +++++++
drivers/gpu/drm/imx/dpu/dpu.h | 389 +++++++++
include/drm/drm_atomic.h | 4 +-
39 files changed, 10020 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
create mode 100644 drivers/gpu/drm/imx/dpu/Kconfig
create mode 100644 drivers/gpu/drm/imx/dpu/Makefile
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-constframe.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-core.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-disengcfg.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-dprc.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-dprc.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-drv.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-drv.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-extdst.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetcheco.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchunit.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchunit.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-framegen.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-gammacor.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-hscaler.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-kms.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-kms.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-layerblend.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-plane.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-plane.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prg.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prg.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prv.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-tcon.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-vscaler.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu.h
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
2020-12-03 3:06 [PATCH v2 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM Liu Ying
@ 2020-12-03 3:06 ` Liu Ying
2020-12-03 3:06 ` [PATCH v2 2/6] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding Liu Ying
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Liu Ying @ 2020-12-03 3:06 UTC (permalink / raw)
To: linux-arm-kernel, dri-devel, devicetree, linux-kernel
Cc: p.zabel, tzimmermann, airlied, festevam, s.hauer,
maarten.lankhorst, mripard, robh+dt, linux-imx, daniel,
laurentiu.palcu, shawnguo, kernel
This patch adds bindings for i.MX8qxp/qm Display Processing Unit.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
Note that this depends on the 'two cell binding' clock patch set which has
already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h
won't be found.
v1->v2:
* Fix yamllint warnings.
* Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the
display controller subsystem spec does say that they exist.
* Use new dt binding way to add clocks in the example.
* Trivial tweaks for the example.
.../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 416 +++++++++++++++++++++
1 file changed, 416 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
new file mode 100644
index 00000000..045df5a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
@@ -0,0 +1,416 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Processing Unit
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two
+ main components that include a blit engine for 2D graphics accelerations
+ and a display controller for display output processing, as well as a command
+ sequencer.
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx8qxp-dpu
+ - const: fsl,imx8qm-dpu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: |
+ store9 shadow load interrupt(blit engine)
+ - description: |
+ store9 frame complete interrupt(blit engine)
+ - description: |
+ store9 sequence complete interrupt(blit engine)
+ - description: |
+ extdst0 shadow load interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst0 frame complete interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst0 sequence complete interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst4 shadow load interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst4 frame complete interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst4 sequence complete interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst1 shadow load interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst1 frame complete interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst1 sequence complete interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst5 shadow load interrupt
+ (display controller, safety stream 1)
+ - description: |
+ extdst5 frame complete interrupt
+ (display controller, safety stream 1)
+ - description: |
+ extdst5 sequence complete interrupt
+ (display controller, safety stream 1)
+ - description: |
+ disengcfg0 shadow load interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg0 frame complete interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg0 sequence complete interrupt
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt0
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt1
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt2
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt3
+ (display controller, display stream 0)
+ - description: |
+ signature0 shadow load interrupt
+ (display controller, display stream 0)
+ - description: |
+ signature0 measurement valid interrupt
+ (display controller, display stream 0)
+ - description: |
+ signature0 error condition interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg1 shadow load interrupt
+ (display controller, display stream 1)
+ - description: |
+ disengcfg1 frame complete interrupt
+ (display controller, display stream 1)
+ - description: |
+ disengcfg1 sequence complete interrupt
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt0
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt1
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt2
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt3
+ (display controller, display stream 1)
+ - description: |
+ signature1 shadow load interrupt
+ (display controller, display stream 1)
+ - description: |
+ signature1 measurement valid interrupt
+ (display controller, display stream 1)
+ - description: |
+ signature1 error condition interrupt
+ (display controller, display stream 1)
+ - description: |
+ command sequencer error condition interrupt(command sequencer)
+ - description: |
+ common control software interrupt0(common control)
+ - description: |
+ common control software interrupt1(common control)
+ - description: |
+ common control software interrupt2(common control)
+ - description: |
+ common control software interrupt3(common control)
+ - description: |
+ framegen0 sychronization status activated interrupt
+ (display controller, safety stream 0)
+ - description: |
+ framegen0 sychronization status deactivated interrupt
+ (display controller, safety stream 0)
+ - description: |
+ framegen0 sychronization status activated interrupt
+ (display controller, content stream 0)
+ - description: |
+ framegen0 sychronization status deactivated interrupt
+ (display controller, content stream 0)
+ - description: |
+ framegen1 sychronization status activated interrupt
+ (display controller, safety stream 1)
+ - description: |
+ framegen1 sychronization status deactivated interrupt
+ (display controller, safety stream 1)
+ - description: |
+ framegen1 sychronization status activated interrupt
+ (display controller, content stream 1)
+ - description: |
+ framegen1 sychronization status deactivated interrupt
+ (display controller, content stream 1)
+
+ interrupt-names:
+ items:
+ - const: store9_shdload
+ - const: store9_framecomplete
+ - const: store9_seqcomplete
+ - const: extdst0_shdload
+ - const: extdst0_framecomplete
+ - const: extdst0_seqcomplete
+ - const: extdst4_shdload
+ - const: extdst4_framecomplete
+ - const: extdst4_seqcomplete
+ - const: extdst1_shdload
+ - const: extdst1_framecomplete
+ - const: extdst1_seqcomplete
+ - const: extdst5_shdload
+ - const: extdst5_framecomplete
+ - const: extdst5_seqcomplete
+ - const: disengcfg_shdload0
+ - const: disengcfg_framecomplete0
+ - const: disengcfg_seqcomplete0
+ - const: framegen0_int0
+ - const: framegen0_int1
+ - const: framegen0_int2
+ - const: framegen0_int3
+ - const: sig0_shdload
+ - const: sig0_valid
+ - const: sig0_error
+ - const: disengcfg_shdload1
+ - const: disengcfg_framecomplete1
+ - const: disengcfg_seqcomplete1
+ - const: framegen1_int0
+ - const: framegen1_int1
+ - const: framegen1_int2
+ - const: framegen1_int3
+ - const: sig1_shdload
+ - const: sig1_valid
+ - const: sig1_error
+ - const: cmdseq_error
+ - const: comctrl_sw0
+ - const: comctrl_sw1
+ - const: comctrl_sw2
+ - const: comctrl_sw3
+ - const: framegen0_primsync_on
+ - const: framegen0_primsync_off
+ - const: framegen0_secsync_on
+ - const: framegen0_secsync_off
+ - const: framegen1_primsync_on
+ - const: framegen1_primsync_off
+ - const: framegen1_secsync_on
+ - const: framegen1_secsync_off
+
+ clocks:
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: axi
+ - const: cfg
+ - const: pll0
+ - const: pll1
+ - const: bypass0
+ - const: bypass1
+ - const: disp0
+ - const: disp1
+
+ power-domains:
+ items:
+ - description: DC power-domain
+ - description: PLL0 power-domain
+ - description: PLL1 power-domain
+
+ power-domain-names:
+ items:
+ - const: dc
+ - const: pll0
+ - const: pll1
+
+ fsl,dpr-channels:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandle which points to DPR channels associated with
+ this DPU instance.
+
+ ports:
+ type: object
+ description: |
+ A node containing DPU output port nodes with endpoint definitions
+ as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ Documentation/devicetree/bindings/graph.txt
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ port@0:
+ type: object
+ description: The DPU output port node from display stream0.
+
+ properties:
+ reg:
+ const: 0
+
+ required:
+ - reg
+
+ port@1:
+ type: object
+ description: The DPU output port node from display stream1.
+
+ properties:
+ reg:
+ const: 1
+
+ required:
+ - reg
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+ - port@1
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - fsl,dpr-channels
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ dpu@56180000 {
+ compatible = "fsl,imx8qxp-dpu";
+ reg = <0x56180000 0x40000>;
+ interrupt-parent = <&dc0_irqsteer>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <70>, <193>, <194>,
+ <195>, <196>, <197>, <72>,
+ <73>, <74>, <75>, <76>,
+ <77>, <78>, <79>, <80>,
+ <81>, <199>, <200>, <201>,
+ <202>, <203>, <204>, <205>,
+ <206>, <207>, <208>, <0>,
+ <1>, <2>, <3>, <4>,
+ <82>, <83>, <84>, <85>,
+ <209>, <210>, <211>, <212>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_secsync_on",
+ "framegen0_secsync_off",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_secsync_on",
+ "framegen1_secsync_off";
+ clocks = <&dc0_dpu_lpcg IMX_LPCG_CLK_5>,
+ <&dc0_dpu_lpcg IMX_LPCG_CLK_4>,
+ <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_DC_0_VIDEO1 IMX_SC_PM_CLK_BYPASS>,
+ <&dc0_disp_lpcg IMX_LPCG_CLK_0>,
+ <&dc0_disp_lpcg IMX_LPCG_CLK_1>;
+ clock-names = "axi", "cfg",
+ "pll0", "pll1", "bypass0", "bypass1",
+ "disp0", "disp1";
+ power-domains = <&pd IMX_SC_R_DC_0>,
+ <&pd IMX_SC_R_DC_0_PLL_0>,
+ <&pd IMX_SC_R_DC_0_PLL_1>;
+ power-domain-names = "dc", "pll0", "pll1";
+ fsl,dpr-channels = <&dc0_dpr1_channel1>,
+ <&dc0_dpr1_channel2>,
+ <&dc0_dpr1_channel3>,
+ <&dc0_dpr2_channel1>,
+ <&dc0_dpr2_channel2>,
+ <&dc0_dpr2_channel3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu0_disp0_pixel_combiner0_ch0: endpoint {
+ remote-endpoint = <&pixel_combiner0_ch0_dpu0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu0_disp1_pixel_combiner0_ch1: endpoint {
+ remote-endpoint = <&pixel_combiner0_ch1_dpu0_disp1>;
+ };
+ };
+ };
+ };
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/6] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding
2020-12-03 3:06 [PATCH v2 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM Liu Ying
2020-12-03 3:06 ` [PATCH v2 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding Liu Ying
@ 2020-12-03 3:06 ` Liu Ying
2020-12-03 3:06 ` [PATCH v2 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding Liu Ying
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Liu Ying @ 2020-12-03 3:06 UTC (permalink / raw)
To: linux-arm-kernel, dri-devel, devicetree, linux-kernel
Cc: p.zabel, tzimmermann, airlied, festevam, s.hauer,
maarten.lankhorst, mripard, robh+dt, linux-imx, daniel,
laurentiu.palcu, shawnguo, kernel
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
Note that this depends on the 'two cell binding' clock patch set which has
already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h
won't be found.
v1->v2:
* Use new dt binding way to add clocks in the example.
.../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 ++++++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
new file mode 100644
index 00000000..d59e2db
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-prg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Prefetch Resolve Gasket
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The i.MX8qm/qxp Prefetch Resolve Gasket (PRG) is a gasket interface between
+ RTRAM controller and Display Controller. The main function is to convert
+ the AXI interface to the RTRAM interface, which includes re-mapping the
+ ARADDR to a RTRAM address.
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx8qxp-prg
+ - const: fsl,imx8qm-prg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: rtram clock
+ - description: apb clock
+
+ clock-names:
+ items:
+ - const: rtram
+ - const: apb
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ prg@56040000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x56040000 0x10000>;
+ clocks = <&dc0_prg0_lpcg IMX_LPCG_CLK_0>,
+ <&dc0_prg0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding
2020-12-03 3:06 [PATCH v2 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM Liu Ying
2020-12-03 3:06 ` [PATCH v2 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding Liu Ying
2020-12-03 3:06 ` [PATCH v2 2/6] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding Liu Ying
@ 2020-12-03 3:06 ` Liu Ying
2020-12-03 3:06 ` [PATCH v2 4/6] drm/atomic: Avoid unused-but-set-variable warning on for_each_old_plane_in_state Liu Ying
2020-12-03 3:06 ` [PATCH v2 6/6] MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver Liu Ying
4 siblings, 0 replies; 6+ messages in thread
From: Liu Ying @ 2020-12-03 3:06 UTC (permalink / raw)
To: linux-arm-kernel, dri-devel, devicetree, linux-kernel
Cc: p.zabel, tzimmermann, airlied, festevam, s.hauer,
maarten.lankhorst, mripard, robh+dt, linux-imx, daniel,
laurentiu.palcu, shawnguo, kernel
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
Note that this depends on the 'two cell binding' clock patch set which has
already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h
won't be found.
v1->v2:
* Use new dt binding way to add clocks in the example.
.../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++++++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
new file mode 100644
index 00000000..91e9472
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which
+ fetches display data before the display pipeline needs the data to drive
+ pixels in the active display region. This data is transformed, or resolved,
+ from a variety of tiled buffer formats into linear format, if needed.
+ The DPR works with a double bank memory structure. This memory structure is
+ implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to
+ as A and B. Each bank is either 4 or 8 lines high depending on the source
+ frame buffer format.
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx8qxp-dpr-channel
+ - const: fsl,imx8qm-dpr-channel
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: apb clock
+ - description: b clock
+ - description: rtram clock
+
+ clock-names:
+ items:
+ - const: apb
+ - const: b
+ - const: rtram
+
+ fsl,sc-resource:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The SCU resource ID associated with this DPRC instance.
+
+ fsl,prgs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandle which points to Prefetch Resolve Gaskets(PRGs)
+ associated with this DPRC instance.
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - fsl,sc-resource
+ - fsl,prgs
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ dpr-channel@56100000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x56100000 0x10000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>,
+ <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>,
+ <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>;
+ fsl,prgs = <&dc0_prg4>, <&dc0_prg5>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 4/6] drm/atomic: Avoid unused-but-set-variable warning on for_each_old_plane_in_state
2020-12-03 3:06 [PATCH v2 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM Liu Ying
` (2 preceding siblings ...)
2020-12-03 3:06 ` [PATCH v2 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding Liu Ying
@ 2020-12-03 3:06 ` Liu Ying
2020-12-03 3:06 ` [PATCH v2 6/6] MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver Liu Ying
4 siblings, 0 replies; 6+ messages in thread
From: Liu Ying @ 2020-12-03 3:06 UTC (permalink / raw)
To: linux-arm-kernel, dri-devel, devicetree, linux-kernel
Cc: p.zabel, tzimmermann, airlied, festevam, s.hauer,
maarten.lankhorst, mripard, robh+dt, linux-imx, daniel,
laurentiu.palcu, shawnguo, kernel
Artifically use 'plane' and 'old_plane_state' to avoid 'not used' warning.
The precedent has already been set by other macros in the same file.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* No change.
include/drm/drm_atomic.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 54e051a..9da1e35a3 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -888,7 +888,9 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
(__i)++) \
for_each_if ((__state)->planes[__i].ptr && \
((plane) = (__state)->planes[__i].ptr, \
- (old_plane_state) = (__state)->planes[__i].old_state, 1))
+ (void)(plane) /* Only to avoid unused-but-set-variable warning */, \
+ (old_plane_state) = (__state)->planes[__i].old_state, \
+ (void)(old_plane_state) /* Only to avoid unused-but-set-variable warning */, 1))
/**
* for_each_new_plane_in_state - iterate over all planes in an atomic update
* @__state: &struct drm_atomic_state pointer
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 6/6] MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver
2020-12-03 3:06 [PATCH v2 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM Liu Ying
` (3 preceding siblings ...)
2020-12-03 3:06 ` [PATCH v2 4/6] drm/atomic: Avoid unused-but-set-variable warning on for_each_old_plane_in_state Liu Ying
@ 2020-12-03 3:06 ` Liu Ying
4 siblings, 0 replies; 6+ messages in thread
From: Liu Ying @ 2020-12-03 3:06 UTC (permalink / raw)
To: linux-arm-kernel, dri-devel, devicetree, linux-kernel
Cc: p.zabel, tzimmermann, airlied, festevam, s.hauer,
maarten.lankhorst, mripard, robh+dt, linux-imx, daniel,
laurentiu.palcu, shawnguo, kernel
Add myself as the maintainer of the i.MX8qxp DPU DRM driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* No change.
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 970d9ce..dee4586 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5834,6 +5834,15 @@ F: Documentation/devicetree/bindings/display/imx/
F: drivers/gpu/drm/imx/
F: drivers/gpu/ipu-v3/
+DRM DRIVERS FOR FREESCALE i.MX8QXP
+M: Liu Ying <victor.liu@nxp.com>
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
+F: drivers/gpu/drm/imx/dpu/
+
DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
M: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
L: dri-devel@lists.freedesktop.org
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-12-03 3:18 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-12-03 3:06 [PATCH v2 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM Liu Ying
2020-12-03 3:06 ` [PATCH v2 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding Liu Ying
2020-12-03 3:06 ` [PATCH v2 2/6] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding Liu Ying
2020-12-03 3:06 ` [PATCH v2 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding Liu Ying
2020-12-03 3:06 ` [PATCH v2 4/6] drm/atomic: Avoid unused-but-set-variable warning on for_each_old_plane_in_state Liu Ying
2020-12-03 3:06 ` [PATCH v2 6/6] MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver Liu Ying
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