* [PATCH v8 1/3] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
2021-01-08 22:21 [PATCH v8 0/3] Variscite DART-6UL SoM support Oliver Graute
@ 2021-01-08 22:21 ` Oliver Graute
2021-01-09 19:50 ` Fabio Estevam
2021-01-08 22:21 ` [PATCH v8 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute
2021-01-08 22:21 ` [PATCH v3 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles Oliver Graute
2 siblings, 1 reply; 9+ messages in thread
From: Oliver Graute @ 2021-01-08 22:21 UTC (permalink / raw)
To: shawnguo
Cc: devicetree, parthitce, narmstrong, Sascha Hauer, m.felsch,
linux-kernel, Oliver Graute, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, linux-arm-kernel
This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
SoM Carrier-Board
Signed-off-by: Oliver Graute <oliver.graute@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Marco Felsch <m.felsch@pengutronix.de>
Cc: Parthiban Nallathambi <parthitce@gmail.com>
---
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 300 +++++++++++++++++++++
1 file changed, 300 insertions(+)
Changelog:
v8:
- remove can node
- remove flexscan pinctrl
- moved lcd and i2c pinctrl
- sorted regulators
- add dedicated pinctrl for dvfs regulator
v7:
- removed cpu0 node
- fixed phy problem
v6:
- renamed touch regulator
- renamed rmii clock
- moved some muxing to baseboard
- added pinctrl for gpio key
- added bus-width to usdhc1
- fixed missing subnode on partitions
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
new file mode 100644
index 00000000..913a66f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ clk_rmii_ref: clock-rmii-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "rmii-ref";
+ };
+
+ reg_gpio_dvfs: regulator-gpio {
+ compatible = "regulator-gpio";
+ gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dvfs_reg>;
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "gpio_dvfs";
+ regulator-type = "voltage";
+ enable-active-high;
+ states = <1300000 0x1 1400000 0x0>;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_touch_3v3: regulator-touch-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_3v3_supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+};
+
+&adc1 {
+ vref-supply = <®_touch_3v3>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ phy-reset-gpios=<&gpio5 10 1>;
+ phy-reset-duration=<100>;
+ phy-reset-on-resume;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&clk_rmii_ref>;
+ clock-names = "rmii-ref";
+ reg = <1>;
+ };
+
+ ethphy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,rmii-reference-clock-select-25-mhz;
+ clocks = <&clk_rmii_ref>;
+ clock-names = "rmii-ref";
+ reg = <3>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+ <&clks IMX6UL_CLK_SAI2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <0>, <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&snvs_rtc {
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <4>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ vmmc-supply = <®_sd1_vmmc>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
+ MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
+ MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
+ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
+ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
+ MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
+ MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
+ >;
+ };
+
+ pinctrl_dvfs_reg: dvfs-grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x78b0
+ >;
+ };
+};
--
2.7.4
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v8 1/3] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
2021-01-08 22:21 ` [PATCH v8 1/3] ARM: dts: imx6ul: Add " Oliver Graute
@ 2021-01-09 19:50 ` Fabio Estevam
0 siblings, 0 replies; 9+ messages in thread
From: Fabio Estevam @ 2021-01-09 19:50 UTC (permalink / raw)
To: Oliver Graute
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
parthitce, Neil Armstrong, Sascha Hauer, Marco Felsch,
linux-kernel, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Oliver,
On Fri, Jan 8, 2021 at 7:22 PM Oliver Graute <oliver.graute@gmail.com> wrote:
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet1>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy0>;
> + phy-reset-gpios=<&gpio5 10 1>;
> + phy-reset-duration=<100>;
These properties are obsolete. Please describe the Ethernet PHY reset
inside the ethernet-phy nodes as per:
Documentation/devicetree/bindings/net/ethernet-phy.yaml
> + phy-reset-on-resume;
This property does not exist.
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v8 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
2021-01-08 22:21 [PATCH v8 0/3] Variscite DART-6UL SoM support Oliver Graute
2021-01-08 22:21 ` [PATCH v8 1/3] ARM: dts: imx6ul: Add " Oliver Graute
@ 2021-01-08 22:21 ` Oliver Graute
2021-01-09 19:53 ` Fabio Estevam
2021-01-08 22:21 ` [PATCH v3 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles Oliver Graute
2 siblings, 1 reply; 9+ messages in thread
From: Oliver Graute @ 2021-01-08 22:21 UTC (permalink / raw)
To: shawnguo
Cc: devicetree, parthitce, Arnd Bergmann, narmstrong, Sascha Hauer,
m.felsch, linux-kernel, Oliver Graute, soc, Rob Herring,
NXP Linux Team, Pengutronix Kernel Team, Olof Johansson,
Fabio Estevam, linux-arm-kernel
This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI
Signed-off-by: Oliver Graute <oliver.graute@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Marco Felsch <m.felsch@pengutronix.de>
Cc: Parthiban Nallathambi <parthitce@gmail.com>
---
Changelog:
v8:
- backlight droped the status line
- port the display panel
- added pinctrl for touch
v7:
- fixed wakeup-source
v6:
- added some muxing
- added codec in sound node
- added adc1 node
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 270 ++++++++++++++++++++++++
2 files changed, 271 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3d1ea0b..7a73b72 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -634,6 +634,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
+ imx6ul-var-6ulcustomboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
new file mode 100644
index 00000000..e647d22
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Support for Variscite DART-6UL Module
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
+ * Copyright (C) 2018-2021 Oliver Graute <oliver.graute@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ul-imx6ull-var-dart-common.dtsi"
+
+/ {
+ model = "Variscite i.MX6 UltraLite Carrier-board";
+ compatible = "variscite,6ulcustomboard", "fsl,imx6ul";
+
+ backlight_lcd: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 20000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user {
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_BACK>;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ d16-led {
+ gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ panel1: panel-lcd {
+ compatible = "sgd,gktw70sdad1sd";
+
+ backlight = <&backlight_lcd>;
+ power-supply = <®_touch_3v3>;
+ label = "gktw70sdad1sd";
+
+ display-timing {
+ /* clock-frequency = <29232000>; */
+ clock-frequency = <35000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <40>;
+ hback-porch = <40>;
+ vsync-len = <48>;
+ vback-porch = <29>;
+ vfront-porch = <13>;
+ hsync-len = <3>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm8731audio";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Jack",
+ "Microphone", "Mic Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "RLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "Mic Bias", "Mic Jack";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,frame-master = <&codec_dai>;
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8731>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ wm8731: audio-codec@1a {
+ compatible = "wlf,wm8731";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ clock-names = "mclk";
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <4 IRQ_TYPE_NONE>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ wakeup-source;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ status = "okay";
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif: lcdif {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
+ MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
+ MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
+ MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
+ MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
+ MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x80000000
+ >;
+ };
+
+};
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v8 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
2021-01-08 22:21 ` [PATCH v8 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute
@ 2021-01-09 19:53 ` Fabio Estevam
2021-01-10 16:12 ` Oliver Graute
0 siblings, 1 reply; 9+ messages in thread
From: Fabio Estevam @ 2021-01-09 19:53 UTC (permalink / raw)
To: Oliver Graute
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
parthitce, Arnd Bergmann, Neil Armstrong, Sascha Hauer,
Marco Felsch, linux-kernel, soc, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Olof Johansson, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Fri, Jan 8, 2021 at 7:23 PM Oliver Graute <oliver.graute@gmail.com> wrote:
> + panel1: panel-lcd {
> + compatible = "sgd,gktw70sdad1sd";
> +
> + backlight = <&backlight_lcd>;
> + power-supply = <®_touch_3v3>;
> + label = "gktw70sdad1sd";
> +
> + display-timing {
If you pass the compatible, then you don't need to add the
display-timing in the device tree.
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v8 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
2021-01-09 19:53 ` Fabio Estevam
@ 2021-01-10 16:12 ` Oliver Graute
0 siblings, 0 replies; 9+ messages in thread
From: Oliver Graute @ 2021-01-10 16:12 UTC (permalink / raw)
To: Fabio Estevam
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
parthitce, Arnd Bergmann, Neil Armstrong, Sascha Hauer,
Marco Felsch, linux-kernel, soc, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Olof Johansson, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On 09/01/21, Fabio Estevam wrote:
> On Fri, Jan 8, 2021 at 7:23 PM Oliver Graute <oliver.graute@gmail.com> wrote:
>
> > + panel1: panel-lcd {
> > + compatible = "sgd,gktw70sdad1sd";
> > +
> > + backlight = <&backlight_lcd>;
> > + power-supply = <®_touch_3v3>;
> > + label = "gktw70sdad1sd";
> > +
> > + display-timing {
>
> If you pass the compatible, then you don't need to add the
> display-timing in the device tree.
thx I`ll drop it
Best Regards,
Oliver
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles
2021-01-08 22:21 [PATCH v8 0/3] Variscite DART-6UL SoM support Oliver Graute
2021-01-08 22:21 ` [PATCH v8 1/3] ARM: dts: imx6ul: Add " Oliver Graute
2021-01-08 22:21 ` [PATCH v8 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute
@ 2021-01-08 22:21 ` Oliver Graute
2021-01-09 19:54 ` Fabio Estevam
2 siblings, 1 reply; 9+ messages in thread
From: Oliver Graute @ 2021-01-08 22:21 UTC (permalink / raw)
To: shawnguo
Cc: devicetree, Robert Jones, Stefan Riedmueller, parthitce,
narmstrong, linux-kernel, Sascha Hauer, m.felsch,
Krzysztof Kozlowski, Li Yang, Oliver Graute, Michael Walle,
Rob Herring, NXP Linux Team, Pengutronix Kernel Team,
Fabio Estevam, linux-arm-kernel
Add the compatibles for Variscite i.MX6UL compatibles
Signed-off-by: Oliver Graute <oliver.graute@gmail.com>
---
Changelog:
v3:
- rebased
v2:
- renamed binding
- removed superflous "
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 05906e2..5f74d78 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -240,6 +240,7 @@ properties:
- technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
- technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit
- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
+ - variscite,imx6ul-var-6ulcustomboard # i.MX UltraLite Carrier-board
- const: fsl,imx6ul
- description: i.MX6UL PHYTEC phyBOARD-Segin
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles
2021-01-08 22:21 ` [PATCH v3 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles Oliver Graute
@ 2021-01-09 19:54 ` Fabio Estevam
2021-01-10 16:13 ` Oliver Graute
0 siblings, 1 reply; 9+ messages in thread
From: Fabio Estevam @ 2021-01-09 19:54 UTC (permalink / raw)
To: Oliver Graute
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Robert Jones, Stefan Riedmueller, parthitce, Neil Armstrong,
linux-kernel, Sascha Hauer, Marco Felsch, Krzysztof Kozlowski,
Li Yang, Michael Walle, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Fri, Jan 8, 2021 at 7:23 PM Oliver Graute <oliver.graute@gmail.com> wrote:
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 05906e2..5f74d78 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -240,6 +240,7 @@ properties:
> - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
> - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit
> - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
> + - variscite,imx6ul-var-6ulcustomboard # i.MX UltraLite Carrier-board
You missed to add a "6" in the description: i.MX6 UltraLite Carrier-board
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles
2021-01-09 19:54 ` Fabio Estevam
@ 2021-01-10 16:13 ` Oliver Graute
0 siblings, 0 replies; 9+ messages in thread
From: Oliver Graute @ 2021-01-10 16:13 UTC (permalink / raw)
To: Fabio Estevam
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Robert Jones, Stefan Riedmueller, parthitce, Neil Armstrong,
linux-kernel, Sascha Hauer, Marco Felsch, Krzysztof Kozlowski,
Li Yang, Michael Walle, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On 09/01/21, Fabio Estevam wrote:
> On Fri, Jan 8, 2021 at 7:23 PM Oliver Graute <oliver.graute@gmail.com> wrote:
>
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> > index 05906e2..5f74d78 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > @@ -240,6 +240,7 @@ properties:
> > - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
> > - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit
> > - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
> > + - variscite,imx6ul-var-6ulcustomboard # i.MX UltraLite Carrier-board
>
> You missed to add a "6" in the description: i.MX6 UltraLite Carrier-board
I will add it.
thx
Best regards,
Oliver
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^ permalink raw reply [flat|nested] 9+ messages in thread