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From: Alain Volmat <alain.volmat@foss.st.com>
To: <broonie@kernel.org>, <amelie.delaunay@foss.st.com>
Cc: <mcoquelin.stm32@gmail.com>, <alexandre.torgue@foss.st.com>,
	<linux-spi@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <fabrice.gasnier@foss.st.com>,
	<alain.volmat@foss.st.com>
Subject: [PATCH v2 6/7] spi: stm32h7: don't wait for EOT and flush fifo on disable
Date: Wed, 7 Jul 2021 10:27:05 +0200	[thread overview]
Message-ID: <1625646426-5826-7-git-send-email-alain.volmat@foss.st.com> (raw)
In-Reply-To: <1625646426-5826-1-git-send-email-alain.volmat@foss.st.com>

In nominal cases, disable is called as part of the unprepare_message,
after receiving a EOT and after receiving all data so it doesn't
make sense to check for EOT and empty the FIFO.
Moreover, at the end of the disable, the SPI is disable (SPE) leading
to clear of all internal FIFO, leaving the IP in a known status.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
---
 drivers/spi/spi-stm32.c | 24 ++----------------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index c2144e3c57eb..535f4bebc010 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -677,13 +677,12 @@ static void stm32f4_spi_disable(struct stm32_spi *spi)
  * stm32h7_spi_disable - Disable SPI controller
  * @spi: pointer to the spi controller data structure
  *
- * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
- * loss, use stm32_spi_read_rxfifo to read the remaining bytes in RX-Fifo.
+ * RX-Fifo is flushed when SPI controller is disabled.
  */
 static void stm32h7_spi_disable(struct stm32_spi *spi)
 {
 	unsigned long flags;
-	u32 cr1, sr;
+	u32 cr1;
 
 	dev_dbg(spi->dev, "disable controller\n");
 
@@ -696,25 +695,6 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
 		return;
 	}
 
-	/* Wait on EOT or suspend the flow */
-	if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
-					      sr, !(sr & STM32H7_SPI_SR_EOT),
-					      10, 100000) < 0) {
-		if (cr1 & STM32H7_SPI_CR1_CSTART) {
-			writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
-				       spi->base + STM32H7_SPI_CR1);
-			if (readl_relaxed_poll_timeout_atomic(
-						spi->base + STM32H7_SPI_SR,
-						sr, !(sr & STM32H7_SPI_SR_SUSP),
-						10, 100000) < 0)
-				dev_warn(spi->dev,
-					 "Suspend request timeout\n");
-		}
-	}
-
-	if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
-		stm32h7_spi_read_rxfifo(spi);
-
 	if (spi->cur_usedma && spi->dma_tx)
 		dmaengine_terminate_all(spi->dma_tx);
 	if (spi->cur_usedma && spi->dma_rx)
-- 
2.25.1


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  parent reply	other threads:[~2021-07-07  8:31 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-07  8:26 [PATCH v2 0/7] spi: stm32: various fixes & cleanup Alain Volmat
2021-07-07  8:27 ` [PATCH v2 1/7] spi: stm32: fixes pm_runtime calls in probe/remove Alain Volmat
2021-07-07  8:27 ` [PATCH v2 2/7] spi: stm32: enable pm_runtime autosuspend Alain Volmat
2021-07-07  8:27 ` [PATCH v2 3/7] spi: stm32h7: fix full duplex irq handler handling Alain Volmat
2021-07-07  8:27 ` [PATCH v2 4/7] spi: stm32: Revert "properly handle 0 byte transfer" Alain Volmat
2021-07-07  8:27 ` [PATCH v2 5/7] spi: stm32h7: rework rx fifo read function Alain Volmat
2021-07-07  8:27 ` Alain Volmat [this message]
2021-07-07  8:27 ` [PATCH v2 7/7] spi: stm32: finalize message either on dma callback or EOT Alain Volmat
2021-07-12 10:45 ` (subset) [PATCH v2 0/7] spi: stm32: various fixes & cleanup Mark Brown

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