[PATCH v1,0/3] Add TOPCKGEN control dpi_clk and mt8186 dpi

[PATCH v1,0/3] Add TOPCKGEN control dpi_clk and mt8186 dpi

[xinlei.lee]

From: Xinlei Lee <xinlei.lee@mediatek.com>

TOPCKGEN's control of dpi_clk was added in this series because in this
patch:
http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005281.html
Give CCF-controlled TOPCKGEN to dpi driver control, as described below:
The dpi0_sel clock should not propagate rate changes to its parent clock
so the dpi driver can have full control over PLL and divider.
This requires corresponding modifications in dpi_driver.

Change-Id: Id5182cc64a71e15f5326a95310c3296967d0693f

Xinlei Lee (3):
  dt-bindings: display: mediatek: dpi: Add compatible for MediaTek
    MT8186
  drm/mediatek: Add TOPCKGEN select mux control dpi_clk
  drm/mediatek: Add mt8186 dpi compatible to mtk_dpi.c

 .../display/mediatek/mediatek,dpi.yaml        |  1 +
 drivers/gpu/drm/mediatek/mtk_dpi.c            | 49 +++++++++++++++++--
 2 files changed, 46 insertions(+), 4 deletions(-)

-- 
2.18.0


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[PATCH v1, 1/3] dt-bindings: display: mediatek: dpi: Add compatible for MediaTek MT8186

[xinlei.lee]

From: Xinlei Lee <xinlei.lee@mediatek.com>

Add dt-binding documentation of dpi for MediaTek MT8186 SoC.

Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index dd2896a40ff0..a73044c50b5f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -22,6 +22,7 @@ properties:
       - mediatek,mt7623-dpi
       - mediatek,mt8173-dpi
       - mediatek,mt8183-dpi
+      - mediatek,mt8186-dpi
       - mediatek,mt8192-dpi
 
   reg:
-- 
2.18.0


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[PATCH v1,2/3] drm/mediatek: Add TOPCKGEN select mux control dpi_clk

[xinlei.lee]

From: Xinlei Lee <xinlei.lee@mediatek.com>

Dpi_clk is controlled by the mux selected
by TOPCKGEN and APMIXEDSYS can support small resolution.

Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 38 ++++++++++++++++++++++++++----
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 4554e2de1430..bad686817e29 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -63,6 +63,14 @@ enum mtk_dpi_out_color_format {
 	MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
 };
 
+enum TVDPLL_CLK {
+	TVDPLL_PLL = 0,
+	TVDPLL_D2 = 2,
+	TVDPLL_D4 = 4,
+	TVDPLL_D8 = 8,
+	TVDPLL_D16 = 16,
+};
+
 struct mtk_dpi {
 	struct drm_encoder encoder;
 	struct drm_bridge bridge;
@@ -73,6 +81,7 @@ struct mtk_dpi {
 	struct clk *engine_clk;
 	struct clk *pixel_clk;
 	struct clk *tvd_clk;
+	struct clk *pclk_src[5];
 	int irq;
 	struct drm_display_mode mode;
 	const struct mtk_dpi_conf *conf;
@@ -459,6 +468,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	struct videomode vm = { 0 };
 	unsigned long pll_rate;
 	unsigned int factor;
+	struct clk *clksrc = NULL;
 
 	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
 	factor = dpi->conf->cal_factor(mode->clock);
@@ -473,11 +483,26 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 
 	vm.pixelclock = pll_rate / factor;
 	if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
-	    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
-		clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
-	else
-		clk_set_rate(dpi->pixel_clk, vm.pixelclock);
+	    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) {
+		if (factor == 8)
+			clksrc = dpi->pclk_src[2];
+		else if (factor == 4)
+			clksrc = dpi->pclk_src[1];
+		else
+			clksrc = dpi->pclk_src[1];
+		}
+	else {
+		if (factor == 8)
+			clksrc = dpi->pclk_src[3];
+		else if (factor == 4)
+			clksrc = dpi->pclk_src[2];
+		else
+			clksrc = dpi->pclk_src[2];
+	}
 
+	clk_prepare_enable(dpi->pixel_clk);
+	clk_set_parent(dpi->pixel_clk, clksrc);
+	clk_disable_unprepare(dpi->pixel_clk);
 
 	vm.pixelclock = clk_get_rate(dpi->pixel_clk);
 
@@ -893,6 +918,11 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	dpi->pclk_src[1] = devm_clk_get_optional(dev, "tvdpll_d2");
+	dpi->pclk_src[2] = devm_clk_get_optional(dev, "tvdpll_d4");
+	dpi->pclk_src[3] = devm_clk_get_optional(dev, "tvdpll_d8");
+	dpi->pclk_src[4] = devm_clk_get_optional(dev, "tvdpll_d16");
+
 	dpi->irq = platform_get_irq(pdev, 0);
 	if (dpi->irq <= 0)
 		return -EINVAL;
-- 
2.18.0


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[PATCH v1,3/3] drm/mediatek: Add mt8186 dpi compatible to mtk_dpi.c

[xinlei.lee]

From: Xinlei Lee <xinlei.lee@mediatek.com>

Add the compatible because use different .data in mt8186.

Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index bad686817e29..5329663ab0fe 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -848,6 +848,14 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 };
 
+static const struct mtk_dpi_conf mt8186_conf = {
+	.cal_factor =  mt8183_calculate_factor,
+	.reg_h_fre_con = 0xe0,
+	.max_clock_khz = 150000,
+	.output_fmts = mt8183_output_fmts,
+	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+};
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -975,6 +983,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
 	{ .compatible = "mediatek,mt8192-dpi",
 	  .data = &mt8192_conf,
 	},
+	{ .compatible = "mediatek,mt8186-dpi",
+	  .data = &mt8186_conf,
+	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
-- 
2.18.0


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Re: [PATCH v1,2/3] drm/mediatek: Add TOPCKGEN select mux control dpi_clk

[AngeloGioacchino Del Regno]

Il 25/02/22 10:53, xinlei.lee@mediatek.com ha scritto:
> From: Xinlei Lee <xinlei.lee@mediatek.com>
> 
> Dpi_clk is controlled by the mux selected
> by TOPCKGEN and APMIXEDSYS can support small resolution.
> 
> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>

Hello Xinlei,

as it was pointed out by reviewers in the MT8195 DisplayPort series, that is
adding the same logic that you are proposing in this patch, the clock parent
selection should be performed by the clock drivers, I'd say in the callback
.set_rate_and_parent(), and not by the mtk_dpi driver.

Please fix this in the proper drivers (clocks!) instead.

Thanks,
Angelo

> ---
>   drivers/gpu/drm/mediatek/mtk_dpi.c | 38 ++++++++++++++++++++++++++----
>   1 file changed, 34 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 4554e2de1430..bad686817e29 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -63,6 +63,14 @@ enum mtk_dpi_out_color_format {
>   	MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
>   };
>   
> +enum TVDPLL_CLK {
> +	TVDPLL_PLL = 0,
> +	TVDPLL_D2 = 2,
> +	TVDPLL_D4 = 4,
> +	TVDPLL_D8 = 8,
> +	TVDPLL_D16 = 16,
> +};
> +
>   struct mtk_dpi {
>   	struct drm_encoder encoder;
>   	struct drm_bridge bridge;
> @@ -73,6 +81,7 @@ struct mtk_dpi {
>   	struct clk *engine_clk;
>   	struct clk *pixel_clk;
>   	struct clk *tvd_clk;
> +	struct clk *pclk_src[5];
>   	int irq;
>   	struct drm_display_mode mode;
>   	const struct mtk_dpi_conf *conf;
> @@ -459,6 +468,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>   	struct videomode vm = { 0 };
>   	unsigned long pll_rate;
>   	unsigned int factor;
> +	struct clk *clksrc = NULL;
>   
>   	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
>   	factor = dpi->conf->cal_factor(mode->clock);
> @@ -473,11 +483,26 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>   
>   	vm.pixelclock = pll_rate / factor;
>   	if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
> -	    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
> -		clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
> -	else
> -		clk_set_rate(dpi->pixel_clk, vm.pixelclock);
> +	    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) {
> +		if (factor == 8)
> +			clksrc = dpi->pclk_src[2];
> +		else if (factor == 4)
> +			clksrc = dpi->pclk_src[1];
> +		else
> +			clksrc = dpi->pclk_src[1];
> +		}
> +	else {
> +		if (factor == 8)
> +			clksrc = dpi->pclk_src[3];
> +		else if (factor == 4)
> +			clksrc = dpi->pclk_src[2];
> +		else
> +			clksrc = dpi->pclk_src[2];
> +	}
>   
> +	clk_prepare_enable(dpi->pixel_clk);
> +	clk_set_parent(dpi->pixel_clk, clksrc);
> +	clk_disable_unprepare(dpi->pixel_clk);
>   
>   	vm.pixelclock = clk_get_rate(dpi->pixel_clk);
>   
> @@ -893,6 +918,11 @@ static int mtk_dpi_probe(struct platform_device *pdev)
>   		return ret;
>   	}
>   
> +	dpi->pclk_src[1] = devm_clk_get_optional(dev, "tvdpll_d2");
> +	dpi->pclk_src[2] = devm_clk_get_optional(dev, "tvdpll_d4");
> +	dpi->pclk_src[3] = devm_clk_get_optional(dev, "tvdpll_d8");
> +	dpi->pclk_src[4] = devm_clk_get_optional(dev, "tvdpll_d16");
> +
>   	dpi->irq = platform_get_irq(pdev, 0);
>   	if (dpi->irq <= 0)
>   		return -EINVAL;


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Re: [PATCH v1,2/3] drm/mediatek: Add TOPCKGEN select mux control dpi_clk

[xinlei.lee]

On Wed, 2022-03-02 at 10:07 +0100, AngeloGioacchino Del Regno wrote:
> Il 25/02/22 10:53, xinlei.lee@mediatek.com ha scritto:
> > From: Xinlei Lee <xinlei.lee@mediatek.com>
> > 
> > Dpi_clk is controlled by the mux selected
> > by TOPCKGEN and APMIXEDSYS can support small resolution.
> > 
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> 
> Hello Xinlei,
> 
> as it was pointed out by reviewers in the MT8195 DisplayPort series,
> that is
> adding the same logic that you are proposing in this patch, the clock
> parent
> selection should be performed by the clock drivers, I'd say in the
> callback
> .set_rate_and_parent(), and not by the mtk_dpi driver.
> 
> Please fix this in the proper drivers (clocks!) instead.
> 
> Thanks,
> Angelo
> 
> > ---
> >   drivers/gpu/drm/mediatek/mtk_dpi.c | 38
> > ++++++++++++++++++++++++++----
> >   1 file changed, 34 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index 4554e2de1430..bad686817e29 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -63,6 +63,14 @@ enum mtk_dpi_out_color_format {
> >   	MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
> >   };
> >   
> > +enum TVDPLL_CLK {
> > +	TVDPLL_PLL = 0,
> > +	TVDPLL_D2 = 2,
> > +	TVDPLL_D4 = 4,
> > +	TVDPLL_D8 = 8,
> > +	TVDPLL_D16 = 16,
> > +};
> > +
> >   struct mtk_dpi {
> >   	struct drm_encoder encoder;
> >   	struct drm_bridge bridge;
> > @@ -73,6 +81,7 @@ struct mtk_dpi {
> >   	struct clk *engine_clk;
> >   	struct clk *pixel_clk;
> >   	struct clk *tvd_clk;
> > +	struct clk *pclk_src[5];
> >   	int irq;
> >   	struct drm_display_mode mode;
> >   	const struct mtk_dpi_conf *conf;
> > @@ -459,6 +468,7 @@ static int mtk_dpi_set_display_mode(struct
> > mtk_dpi *dpi,
> >   	struct videomode vm = { 0 };
> >   	unsigned long pll_rate;
> >   	unsigned int factor;
> > +	struct clk *clksrc = NULL;
> >   
> >   	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
> >   	factor = dpi->conf->cal_factor(mode->clock);
> > @@ -473,11 +483,26 @@ static int mtk_dpi_set_display_mode(struct
> > mtk_dpi *dpi,
> >   
> >   	vm.pixelclock = pll_rate / factor;
> >   	if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
> > -	    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
> > -		clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
> > -	else
> > -		clk_set_rate(dpi->pixel_clk, vm.pixelclock);
> > +	    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) {
> > +		if (factor == 8)
> > +			clksrc = dpi->pclk_src[2];
> > +		else if (factor == 4)
> > +			clksrc = dpi->pclk_src[1];
> > +		else
> > +			clksrc = dpi->pclk_src[1];
> > +		}
> > +	else {
> > +		if (factor == 8)
> > +			clksrc = dpi->pclk_src[3];
> > +		else if (factor == 4)
> > +			clksrc = dpi->pclk_src[2];
> > +		else
> > +			clksrc = dpi->pclk_src[2];
> > +	}
> >   
> > +	clk_prepare_enable(dpi->pixel_clk);
> > +	clk_set_parent(dpi->pixel_clk, clksrc);
> > +	clk_disable_unprepare(dpi->pixel_clk);
> >   
> >   	vm.pixelclock = clk_get_rate(dpi->pixel_clk);
> >   
> > @@ -893,6 +918,11 @@ static int mtk_dpi_probe(struct
> > platform_device *pdev)
> >   		return ret;
> >   	}
> >   
> > +	dpi->pclk_src[1] = devm_clk_get_optional(dev, "tvdpll_d2");
> > +	dpi->pclk_src[2] = devm_clk_get_optional(dev, "tvdpll_d4");
> > +	dpi->pclk_src[3] = devm_clk_get_optional(dev, "tvdpll_d8");
> > +	dpi->pclk_src[4] = devm_clk_get_optional(dev, "tvdpll_d16");
> > +
> >   	dpi->irq = platform_get_irq(pdev, 0);
> >   	if (dpi->irq <= 0)
> >   		return -EINVAL;
> 
> 

Hi Angelo:

Thanks for your review, I would like to explain why I operate clk in
dpi driver.
A patch I mentioned on the cover: 
http://lists.infradead.org/pipermail/linux-mediatek/2016-May/005281.html
It contains instructions:

+ * The dpi0_sel clock should not propagate rate changes to its parent
+ * clock so the dpi driver can have full control over PLL and divider.

My understanding is that the clk driver will no longer perform the
set_rate_and_parent() operation on dpi_clk, but will hand over the
control to the dpi driver.
The current modification may be to synchronize the previous clk
modification.
Can we operate clk on dpi driver for this reson?

Best Regards!
xinlei
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