* [PATCH v5,0/2] Add dpi output format control for MT8186
@ 2022-09-05 13:34 xinlei.lee
2022-09-05 13:34 ` [PATCH v5,1/2] soc: mediatek: Add mmsys func to adapt to dpi output " xinlei.lee
2022-09-05 13:34 ` [PATCH v5,2/2] drm: mediatek: Adjust the dpi output format to MT8186 xinlei.lee
0 siblings, 2 replies; 4+ messages in thread
From: xinlei.lee @ 2022-09-05 13:34 UTC (permalink / raw)
To: matthias.bgg, angelogioacchino.delregno, rex-bc.chen,
jason-jh.lin, chunkuang.hu, yongqiang.niu, p.zabel, airlied,
daniel
Cc: dri-devel, linux-mediatek, linux-arm-kernel, linux-kernel,
Project_Global_Chrome_Upstream_Group, jitao.shi, Xinlei Lee
From: Xinlei Lee <xinlei.lee@mediatek.com>
Base on the branch of Linux-next/master.
Changes since v4:
1. This series of cancellations is based on the following patches:
[1] Add MediaTek SoC(vdosys1) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/cover/20220711075245.10492-1-nancy.lin@mediatek.com/
[2] Add MediaTek SoC DRM (vdosys1) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/cover/20220804072827.22383-1-nancy.lin@mediatek.com/
2. Added mtk_mmsys_update_bits function in mtk-mmsys.c;
3. MMSYS 0x400 register is modified to MT8186_MMSYS_DPI_OUTPUT_FORMAT;
4. Fix formatting issues.
Changes since v3:
1. Fix formatting issues;
2. Modify the edge output control name & description;
3. Fix the threading problem.
Changes since v2:
1. Modify key nouns in the description;
2. Add the label of jitao to Co-developed-by;
3. Macro definition address lowercase problem and function naming;
4. Add missing a description of this property in the mtk_dpi_conf.
Change since v1:
1. Modify mt8186 compatiable location.
2. Modify MT8186_DPI_OUTPUT_FORMAT name.
When MT8186 outputs dpi signal, it is necessary to add dual edge output
format control in mmsys.
Xinlei Lee (2):
FROMLIST: soc: mediatek: Add mmsys func to adapt to dpi output for
MT8186
FROMLIST: drm: mediatek: Adjust the dpi output format to MT8186
drivers/gpu/drm/mediatek/mtk_dpi.c | 31 +++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 5 ++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
drivers/soc/mediatek/mt8186-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 16 +++++++++++++
include/linux/soc/mediatek/mtk-mmsys.h | 2 ++
6 files changed, 57 insertions(+)
--
2.18.0
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v5,1/2] soc: mediatek: Add mmsys func to adapt to dpi output for MT8186
2022-09-05 13:34 [PATCH v5,0/2] Add dpi output format control for MT8186 xinlei.lee
@ 2022-09-05 13:34 ` xinlei.lee
2022-09-05 13:34 ` [PATCH v5,2/2] drm: mediatek: Adjust the dpi output format to MT8186 xinlei.lee
1 sibling, 0 replies; 4+ messages in thread
From: xinlei.lee @ 2022-09-05 13:34 UTC (permalink / raw)
To: matthias.bgg, angelogioacchino.delregno, rex-bc.chen,
jason-jh.lin, chunkuang.hu, yongqiang.niu, p.zabel, airlied,
daniel
Cc: dri-devel, linux-mediatek, linux-arm-kernel, linux-kernel,
Project_Global_Chrome_Upstream_Group, jitao.shi, Xinlei Lee
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="yes", Size: 2383 bytes --]
From: Xinlei Lee <xinlei.lee@mediatek.com>
Add mmsys func to manipulate dpi output format config for MT8186.
Co-developed-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: Nílas F. R. A. Prado <nfraprado@collabora.com>
---
drivers/soc/mediatek/mt8186-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 16 ++++++++++++++++
include/linux/soc/mediatek/mtk-mmsys.h | 2 ++
3 files changed, 19 insertions(+)
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index eb1ad9c37a9c..3db0806647c3 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -3,6 +3,7 @@
#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
#define __SOC_MEDIATEK_MT8186_MMSYS_H
+#define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400
#define MT8186_MMSYS_OVL_CON 0xF04
#define MT8186_MMSYS_OVL0_CON_MASK 0x3
#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 06d8e83a2cb5..d7d17d4a9a5d 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -227,6 +227,22 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(mmsys->regs + offset);
+ tmp = (tmp & ~mask) | val;
+ writel_relaxed(tmp, mmsys->regs + offset);
+}
+
+void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 mask, u32 val)
+{
+ mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8186_MMSYS_DPI_OUTPUT_FORMAT, mask,
+ val);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 59117d970daf..7a378d247505 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -65,4 +65,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 mask, u32 val);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v5,2/2] drm: mediatek: Adjust the dpi output format to MT8186
2022-09-05 13:34 [PATCH v5,0/2] Add dpi output format control for MT8186 xinlei.lee
2022-09-05 13:34 ` [PATCH v5,1/2] soc: mediatek: Add mmsys func to adapt to dpi output " xinlei.lee
@ 2022-09-05 13:34 ` xinlei.lee
2022-09-07 9:09 ` CK Hu
1 sibling, 1 reply; 4+ messages in thread
From: xinlei.lee @ 2022-09-05 13:34 UTC (permalink / raw)
To: matthias.bgg, angelogioacchino.delregno, rex-bc.chen,
jason-jh.lin, chunkuang.hu, yongqiang.niu, p.zabel, airlied,
daniel
Cc: dri-devel, linux-mediatek, linux-arm-kernel, linux-kernel,
Project_Global_Chrome_Upstream_Group, jitao.shi, Xinlei Lee
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="yes", Size: 4993 bytes --]
From: Xinlei Lee <xinlei.lee@mediatek.com>
Dpi output needs to adjust the output format to dual edge for MT8186.
Co-developed-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nílas F. R. A. Prado <nfraprado@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 31 +++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 5 ++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
3 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 630a4e301ef6..ffe4a4b70a0f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -15,6 +15,7 @@
#include <linux/of_graph.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/types.h>
#include <video/videomode.h>
@@ -30,6 +31,7 @@
#include "mtk_disp_drv.h"
#include "mtk_dpi_regs.h"
#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
enum mtk_dpi_out_bit_num {
MTK_DPI_OUT_BIT_NUM_8BITS,
@@ -82,6 +84,7 @@ struct mtk_dpi {
struct pinctrl_state *pins_dpi;
u32 output_fmt;
int refcount;
+ struct device *mmsys_dev;
};
static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
@@ -135,6 +138,7 @@ struct mtk_dpi_yc_limit {
* @yuv422_en_bit: Enable bit of yuv422.
* @csc_enable_bit: Enable bit of CSC.
* @pixels_per_iter: Quantity of transferred pixels per iteration.
+ * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
*/
struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
@@ -153,6 +157,7 @@ struct mtk_dpi_conf {
u32 yuv422_en_bit;
u32 csc_enable_bit;
u32 pixels_per_iter;
+ bool edge_cfg_in_mmsys;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -449,6 +454,9 @@ static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ?
EDGE_SEL : 0, EDGE_SEL);
+ if (dpi->conf->edge_cfg_in_mmsys)
+ mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, DPI_RGB888_DDR_CON,
+ DPI_FORMAT_MASK);
} else {
mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
}
@@ -778,8 +786,10 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
{
struct mtk_dpi *dpi = dev_get_drvdata(dev);
struct drm_device *drm_dev = data;
+ struct mtk_drm_private *priv = drm_dev->dev_private;
int ret;
+ dpi->mmsys_dev = priv->mmsys_dev;
ret = drm_simple_encoder_init(drm_dev, &dpi->encoder,
DRM_MODE_ENCODER_TMDS);
if (ret) {
@@ -930,6 +940,24 @@ static const struct mtk_dpi_conf mt8183_conf = {
.csc_enable_bit = CSC_ENABLE,
};
+static const struct mtk_dpi_conf mt8186_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .reg_h_fre_con = 0xe0,
+ .max_clock_khz = 150000,
+ .output_fmts = mt8183_output_fmts,
+ .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+ .edge_cfg_in_mmsys = true,
+ .pixels_per_iter = 1,
+ .is_ck_de_pol = true,
+ .swap_input_support = true,
+ .support_direct_pin = true,
+ .dimension_mask = HPW_MASK,
+ .hvsize_mask = HSIZE_MASK,
+ .channel_swap_shift = CH_SWAP,
+ .yuv422_en_bit = YUV422_EN,
+ .csc_enable_bit = CSC_ENABLE,
+};
+
static const struct mtk_dpi_conf mt8192_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
@@ -1080,6 +1108,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8183-dpi",
.data = &mt8183_conf,
},
+ { .compatible = "mediatek,mt8186-dpi",
+ .data = &mt8186_conf,
+ },
{ .compatible = "mediatek,mt8192-dpi",
.data = &mt8192_conf,
},
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 62bd4931b344..779e868ffb1a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -235,4 +235,9 @@
#define MATRIX_SEL_RGB_TO_JPEG 0
#define MATRIX_SEL_RGB_TO_BT601 2
+/* Values for DPI configuration in MMSYS address space */
+#define DPI_FORMAT_MASK 0x1
+#define DPI_RGB888_DDR_CON BIT(0)
+#define DPI_RGB565_SDR_CON BIT(1)
+
#endif /* __MTK_DPI_REGS_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5f02f8d0e4fc..28eb1ac91c15 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -631,6 +631,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8183-dpi",
.data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8186-dpi",
+ .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8192-dpi",
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8195-dp-intf",
--
2.18.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v5,2/2] drm: mediatek: Adjust the dpi output format to MT8186
2022-09-05 13:34 ` [PATCH v5,2/2] drm: mediatek: Adjust the dpi output format to MT8186 xinlei.lee
@ 2022-09-07 9:09 ` CK Hu
0 siblings, 0 replies; 4+ messages in thread
From: CK Hu @ 2022-09-07 9:09 UTC (permalink / raw)
To: xinlei.lee, matthias.bgg, angelogioacchino.delregno, rex-bc.chen,
jason-jh.lin, chunkuang.hu, yongqiang.niu, p.zabel, airlied,
daniel
Cc: jitao.shi, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
linux-arm-kernel
Hi, Xinlei:
On Mon, 2022-09-05 at 21:34 +0800, xinlei.lee@mediatek.com wrote:
> From: Xinlei Lee <xinlei.lee@mediatek.com>
>
> Dpi output needs to adjust the output format to dual edge for MT8186.
Separate this patch into two patches. One is adding edge_cfg_in_mmsys,
and another one is adding mt8186 dpi support.
I think the default value in mmsys (single edge) should work for some
display so that mmsys hardware use single edge for default value. So I
need you to describe more information why we need dual edge.
>
> Co-developed-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nílas F. R. A. Prado <nfraprado@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 31
> +++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 5 ++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
> 3 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 630a4e301ef6..ffe4a4b70a0f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -15,6 +15,7 @@
> #include <linux/of_graph.h>
> #include <linux/pinctrl/consumer.h>
> #include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> #include <linux/types.h>
>
> #include <video/videomode.h>
> @@ -30,6 +31,7 @@
> #include "mtk_disp_drv.h"
> #include "mtk_dpi_regs.h"
> #include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
>
> enum mtk_dpi_out_bit_num {
> MTK_DPI_OUT_BIT_NUM_8BITS,
> @@ -82,6 +84,7 @@ struct mtk_dpi {
> struct pinctrl_state *pins_dpi;
> u32 output_fmt;
> int refcount;
> + struct device *mmsys_dev;
> };
>
> static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
> @@ -135,6 +138,7 @@ struct mtk_dpi_yc_limit {
> * @yuv422_en_bit: Enable bit of yuv422.
> * @csc_enable_bit: Enable bit of CSC.
> * @pixels_per_iter: Quantity of transferred pixels per iteration.
> + * @edge_cfg_in_mmsys: If the edge configuration for DPI's output
> needs to be set in MMSYS.
> */
> struct mtk_dpi_conf {
> unsigned int (*cal_factor)(int clock);
> @@ -153,6 +157,7 @@ struct mtk_dpi_conf {
> u32 yuv422_en_bit;
> u32 csc_enable_bit;
> u32 pixels_per_iter;
> + bool edge_cfg_in_mmsys;
> };
>
> static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val,
> u32 mask)
> @@ -449,6 +454,9 @@ static void mtk_dpi_dual_edge(struct mtk_dpi
> *dpi)
> mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
> dpi->output_fmt ==
> MEDIA_BUS_FMT_RGB888_2X12_LE ?
> EDGE_SEL : 0, EDGE_SEL);
> + if (dpi->conf->edge_cfg_in_mmsys)
> + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev,
> DPI_RGB888_DDR_CON,
> + DPI_FORMAT_MASK);
> } else {
> mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
> 0);
> }
> @@ -778,8 +786,10 @@ static int mtk_dpi_bind(struct device *dev,
> struct device *master, void *data)
> {
> struct mtk_dpi *dpi = dev_get_drvdata(dev);
> struct drm_device *drm_dev = data;
> + struct mtk_drm_private *priv = drm_dev->dev_private;
> int ret;
>
> + dpi->mmsys_dev = priv->mmsys_dev;
> ret = drm_simple_encoder_init(drm_dev, &dpi->encoder,
> DRM_MODE_ENCODER_TMDS);
> if (ret) {
> @@ -930,6 +940,24 @@ static const struct mtk_dpi_conf mt8183_conf = {
> .csc_enable_bit = CSC_ENABLE,
> };
>
> +static const struct mtk_dpi_conf mt8186_conf = {
> + .cal_factor = mt8183_calculate_factor,
> + .reg_h_fre_con = 0xe0,
> + .max_clock_khz = 150000,
> + .output_fmts = mt8183_output_fmts,
> + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
> + .edge_cfg_in_mmsys = true,
> + .pixels_per_iter = 1,
> + .is_ck_de_pol = true,
> + .swap_input_support = true,
> + .support_direct_pin = true,
> + .dimension_mask = HPW_MASK,
> + .hvsize_mask = HSIZE_MASK,
> + .channel_swap_shift = CH_SWAP,
> + .yuv422_en_bit = YUV422_EN,
> + .csc_enable_bit = CSC_ENABLE,
> +};
> +
> static const struct mtk_dpi_conf mt8192_conf = {
> .cal_factor = mt8183_calculate_factor,
> .reg_h_fre_con = 0xe0,
> @@ -1080,6 +1108,9 @@ static const struct of_device_id
> mtk_dpi_of_ids[] = {
> { .compatible = "mediatek,mt8183-dpi",
> .data = &mt8183_conf,
> },
> + { .compatible = "mediatek,mt8186-dpi",
> + .data = &mt8186_conf,
> + },
> { .compatible = "mediatek,mt8192-dpi",
> .data = &mt8192_conf,
> },
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 62bd4931b344..779e868ffb1a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -235,4 +235,9 @@
> #define MATRIX_SEL_RGB_TO_JPEG 0
> #define MATRIX_SEL_RGB_TO_BT601 2
>
> +/* Values for DPI configuration in MMSYS address space */
> +#define DPI_FORMAT_MASK 0x1
> +#define DPI_RGB888_DDR_CON BIT(0)
> +#define DPI_RGB565_SDR_CON BIT(1)
This is the mmsys register definition, so move these to mmsys driver.
Regards,
CK
> +
> #endif /* __MTK_DPI_REGS_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 5f02f8d0e4fc..28eb1ac91c15 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -631,6 +631,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8183-dpi",
> .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt8186-dpi",
> + .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8192-dpi",
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8195-dp-intf",
> --
> 2.18.0
>
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2022-09-05 13:34 [PATCH v5,0/2] Add dpi output format control for MT8186 xinlei.lee
2022-09-05 13:34 ` [PATCH v5,1/2] soc: mediatek: Add mmsys func to adapt to dpi output " xinlei.lee
2022-09-05 13:34 ` [PATCH v5,2/2] drm: mediatek: Adjust the dpi output format to MT8186 xinlei.lee
2022-09-07 9:09 ` CK Hu
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