From: Richard Zhu <hongxing.zhu@nxp.com>
To: vkoul@kernel.org, p.zabel@pengutronix.de, l.stach@pengutronix.de,
bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org,
shawnguo@kernel.org, alexander.stein@ew.tq-group.com,
marex@denx.de, richard.leitner@linux.dev
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v10 1/4] dt-binding: phy: Add i.MX8MP PCIe PHY binding
Date: Thu, 29 Sep 2022 16:36:59 +0800 [thread overview]
Message-ID: <1664440622-18556-2-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1664440622-18556-1-git-send-email-hongxing.zhu@nxp.com>
Add i.MX8MP PCIe PHY binding.
On i.MX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy
reg:
maxItems: 1
@@ -28,11 +29,16 @@ properties:
- const: ref
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
- items:
- - const: pciephy
+ oneOf:
+ - items: # for iMX8MM
+ - const: pciephy
+ - items: # for IMX8MP
+ - const: pciephy
+ - const: perst
fsl,refclk-pad-mode:
description: |
@@ -60,6 +66,10 @@ properties:
description: A boolean property indicating the CLKREQ# signal is
not supported in the board design (optional)
+ power-domains:
+ description: PCIe PHY power domain (optional).
+ maxItems: 1
+
required:
- "#phy-cells"
- compatible
--
2.25.1
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next prev parent reply other threads:[~2022-09-29 8:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-29 8:36 [PATCH v10 0/4] Add the iMX8MP PCIe support Richard Zhu
2022-09-29 8:36 ` Richard Zhu [this message]
2022-09-29 8:37 ` [PATCH v10 2/4] phy: freescale: imx8m-pcie: Refine register definitions Richard Zhu
2022-09-29 8:37 ` [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver Richard Zhu
2022-09-30 8:28 ` Ahmad Fatoum
2022-10-03 5:14 ` Hongxing Zhu
2022-09-29 8:37 ` [PATCH v10 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support Richard Zhu
2022-09-30 8:46 ` Ahmad Fatoum
2022-10-03 5:15 ` Hongxing Zhu
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