RE: [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver

[Hongxing Zhu <hongxing.zhu@nxp.com>]

> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Sent: 2022年9月30日 16:29
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; vkoul@kernel.org;
> p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de; richard.leitner@linux.dev
> Cc: devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-kernel@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> kernel@pengutronix.de; linux-phy@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM
> PCIe PHY driver
> 
> On 29.09.22 09:37, Richard Zhu wrote:
> > To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
> > driver.
> > - Use gpr compatible string to avoid the codes duplications when add
> >   another platform PCIe PHY support.
> > - Re-orange the codes to let it more flexible and easy to expand.
> 
> Re-arrange
Sorry for the spell mistake. Thanks for your review comments.

> 
> > No functions changes basicly.
> 
> No functional change.
Got that, thanks.
> 
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 106
> > +++++++++++++--------
> >  1 file changed, 66 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > index 2377ed307b53..59b46a4ae069 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > @@ -11,6 +11,7 @@
> >  #include <linux/mfd/syscon.h>
> >  #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> >  #include <linux/module.h>
> > +#include <linux/of_device.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/regmap.h>
> > @@ -45,6 +46,15 @@
> >  #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
> >  #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
> >
> > +enum imx8_pcie_phy_type {
> > +	IMX8MM,
> > +};
> > +
> > +struct imx8_pcie_phy_drvdata {
> > +	enum		imx8_pcie_phy_type variant;
> 
> Better do indentation on the member name.
Got that, would make them indent later thanks.
> 
> > +	const char	*gpr;
> > +};
> > +
> >  struct imx8_pcie_phy {
> >  	void __iomem		*base;
> >  	struct clk		*clk;
> > @@ -55,6 +65,7 @@ struct imx8_pcie_phy {
> >  	u32			tx_deemph_gen1;
> >  	u32			tx_deemph_gen2;
> >  	bool			clkreq_unused;
> > +	const struct imx8_pcie_phy_drvdata	*drvdata;
> >  };
> >
> >  static int imx8_pcie_phy_init(struct phy *phy) @@ -66,31 +77,17 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> >  	reset_control_assert(imx8_phy->reset);
> >
> >  	pad_mode = imx8_phy->refclk_pad_mode;
> > -	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > -			   imx8_phy->clkreq_unused ?
> > -			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_AUX_EN,
> > -			   IMX8MM_GPR_PCIE_AUX_EN);
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> > -
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > -			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > -			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > -			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > -	usleep_range(100, 200);
> > -
> > -	/* Do the PHY common block reset */
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_CMN_RST,
> > -			   IMX8MM_GPR_PCIE_CMN_RST);
> > -	usleep_range(200, 500);
> > +	switch (imx8_phy->drvdata->variant) {
> > +	case IMX8MM:
> > +		/* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > +		if (imx8_phy->tx_deemph_gen1)
> > +			writel(imx8_phy->tx_deemph_gen1,
> > +			       imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > +		if (imx8_phy->tx_deemph_gen2)
> > +			writel(imx8_phy->tx_deemph_gen2,
> > +			       imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > +		break;
> > +	}
> 
> If you say no functional change intended, I'd expect that register writes happen
> in the same sequence. It might be ok, that you do this tuning here, but I think
> it warrants a mention in the commit message why it's ok.
> 
> 
> Looks good otherwise. With nitpicks addressed:
> 
> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> 
Got that, thanks a lot.

Best Regards
Richard Zhu
> 
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