From: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
mturquette@baylibre.com, sboyd@kernel.org,
narmstrong@baylibre.com, linux-clk@vger.kernel.org
Cc: khilman@baylibre.com, linux-kernel@vger.kernel.org,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFC v1 2/3] clk: meson: regmap: switch to determine_rate for the dividers
Date: Tue, 18 May 2021 09:47:50 +0200 [thread overview]
Message-ID: <1jr1i41o0p.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20210517203724.1006254-3-martin.blumenstingl@googlemail.com>
On Mon 17 May 2021 at 22:37, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> This increases the maxmium supported frequency on 32-bit systems from
> 2^31 (signed long as used by clk_ops.round_rate, maximum value:
> approx. 2.14GHz) to 2^32 (unsigned long as used by
> clk_ops.determine_rate, maximum value: approx. 4.29GHz).
> On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are
> capable of running at up to 2.97GHz. So switch the divider
> implementation in clk-regmap to clk_ops.determine_rate to support these
> higher frequencies on 32-bit systems.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/clk/meson/clk-regmap.c | 19 +++++++++----------
> 1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c
> index dcd1757cc5df..8ad8977cf1c2 100644
> --- a/drivers/clk/meson/clk-regmap.c
> +++ b/drivers/clk/meson/clk-regmap.c
> @@ -75,8 +75,8 @@ static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
> div->width);
> }
>
> -static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
> - unsigned long *prate)
> +static int clk_regmap_div_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> {
> struct clk_regmap *clk = to_clk_regmap(hw);
> struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
> @@ -87,18 +87,17 @@ static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
> if (div->flags & CLK_DIVIDER_READ_ONLY) {
> ret = regmap_read(clk->map, div->offset, &val);
> if (ret)
> - /* Gives a hint that something is wrong */
> - return 0;
> + return ret;
>
> val >>= div->shift;
> val &= clk_div_mask(div->width);
>
> - return divider_ro_round_rate(hw, rate, prate, div->table,
> - div->width, div->flags, val);
> + return divider_ro_determine_rate(hw, req, div->table,
> + div->width, div->flags, val);
> }
>
> - return divider_round_rate(hw, rate, prate, div->table, div->width,
> - div->flags);
> + return divider_determine_rate(hw, req, div->table, div->width,
> + div->flags);
> }
>
> static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
> @@ -123,14 +122,14 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
>
> const struct clk_ops clk_regmap_divider_ops = {
> .recalc_rate = clk_regmap_div_recalc_rate,
> - .round_rate = clk_regmap_div_round_rate,
> + .determine_rate = clk_regmap_div_determine_rate,
> .set_rate = clk_regmap_div_set_rate,
> };
> EXPORT_SYMBOL_GPL(clk_regmap_divider_ops);
>
> const struct clk_ops clk_regmap_divider_ro_ops = {
> .recalc_rate = clk_regmap_div_recalc_rate,
> - .round_rate = clk_regmap_div_round_rate,
> + .determine_rate = clk_regmap_div_determine_rate,
> };
> EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops);
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next prev parent reply other threads:[~2021-05-18 7:49 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 20:37 [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Martin Blumenstingl
2021-05-17 20:37 ` [PATCH RFC v1 1/3] clk: divider: Add re-usable determine_rate implementations Martin Blumenstingl
2021-05-18 7:44 ` Jerome Brunet
2021-05-18 20:33 ` Martin Blumenstingl
2021-05-19 12:31 ` Jerome Brunet
2021-05-17 20:37 ` [PATCH RFC v1 2/3] clk: meson: regmap: switch to determine_rate for the dividers Martin Blumenstingl
2021-05-18 7:47 ` Jerome Brunet [this message]
2021-05-17 20:37 ` [PATCH RFC v1 3/3] clk: meson: pll: switch to determine_rate for the PLL ops Martin Blumenstingl
2021-05-18 7:50 ` Jerome Brunet
2021-05-18 20:17 ` Martin Blumenstingl
2021-05-19 15:10 ` Jerome Brunet
2021-05-18 7:37 ` [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Jerome Brunet
2021-05-18 20:20 ` Martin Blumenstingl
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