From: Jerome Brunet <jbrunet@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
Jan Dakinevich <jan.dakinevich@salutedevices.com>,
Rob Herring <robh@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Jiucheng Xu <jiucheng.xu@amlogic.com>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH v3 4/6] dt-bindings: clock: meson: document A1 SoC audio clock controller driver
Date: Mon, 22 Apr 2024 09:57:30 +0200 [thread overview]
Message-ID: <1jzftlakgg.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <1jle55c0bl.fsf@starbuckisacylon.baylibre.com>
On Mon 22 Apr 2024 at 09:16, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Sun 21 Apr 2024 at 20:14, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
>> On 20/04/2024 18:15, Jan Dakinevich wrote:
>>>
>>>
>>> On 4/20/24 00:09, Rob Herring wrote:
>>>> On Fri, Apr 19, 2024 at 03:58:10PM +0300, Jan Dakinevich wrote:
>>>>> Add device tree bindings for A1 SoC audio clock and reset controllers.
>>>>>
>>>>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>>> ---
>>>>>
>>>>> This controller has 6 mandatory and up to 20 optional clocks. To describe
>>>>> this, I use 'additionalItems'. It produces correct processed-schema.json:
>>>>>
>>>>> "clock-names": {
>>>>> "maxItems": 26,
>>>>> "items": [
>>>>> {
>>>>> "const": "pclk"
>>>>> },
>>>>> {
>>>>> "const": "dds_in"
>>>>> },
>>>>> {
>>>>> "const": "fclk_div2"
>>>>> },
>>>>> {
>>>>> "const": "fclk_div3"
>>>>> },
>>>>> {
>>>>> "const": "hifi_pll"
>>>>> },
>>>>> {
>>>>> "const": "xtal"
>>>>> }
>>>>> ],
>>>>> "additionalItems": {
>>>>> "oneOf": [
>>>>> {
>>>>> "pattern": "^slv_sclk[0-9]$"
>>>>> },
>>>>> {
>>>>> "pattern": "^slv_lrclk[0-9]$"
>>>>> }
>>>>> ]
>>>>> },
>>>>> "type": "array",
>>>>> "minItems": 6
>>>>> },
>>>>>
>>>>> and it behaves as expected. However, the checking is followed by
>>>>> complaints like this:
>>>>>
>>>>> Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml: properties:clock-names:additionalItems: {'oneOf': [{'pattern': '^slv_sclk[0-9]$'}, {'pattern': '^slv_lrclk[0-9]$'}]} is not of type 'boolean'
>>>>>
>>>>> And indeed, 'additionalItems' has boolean type in meta-schema. So, how to
>>>>> do it right?
>>>>
>>>> The meta-schemas are written both to prevent nonsense that json-schema
>>>> allows by default (e.g additionalitems (wrong case)) and constraints to
>>>> follow the patterns we expect. I'm happy to loosen the latter case if
>>>> there's really a need.
>>>>
>>>> Generally, most bindings shouldn't be using 'additionalItems' at all as
>>>> all entries should be defined, but there's a few exceptions. Here, the
>>>> only reasoning I see is 26 entries is a lot to write out, but that
>>>> wouldn't really justify it.
>>>
>>> Writing a lot of entries don't scary me too much, but the reason is that
>>> the existence of optional clock sources depends on schematics. Also, we
>>
>> Aren't you documenting SoC component, not a board? So how exactly it
>> depends on schematics? SoC is done or not done...
>>
>>> unable to declare dt-nodes for 'clocks' array in any generic way,
>>> because their declaration would depends on that what is actually
>>> connected to the SoC (dt-node could be "fixed-clock" with specific rate
>>> or something else).
>>
>> So these are clock inputs to the SoC?
>>
>
> Yes, possibly.
> Like an external crystal or a set clocks provided by an external codec
> where the codec is the clock master of the link.
>
> This is same case as the AXG that was discussed here:
> https://lore.kernel.org/linux-devicetree/20230808194811.113087-1-alexander.stein@mailbox.org/
>
> IMO, like the AXG, only the pclk is a required clock.
> All the others - master and slave clocks - are optional.
> The controller is designed to operate with grounded inputs
Looking again at the implementation of the controller, there is a clear
indication in patch 3 that the controller interface is the same as the
AXG and that the above statement is true.
The AXG had 8 master clocks wired in. The A1 just has 5 - and 3 grounded
master clocks. This is why you to had to provide a mux input table to
skip the grounded inputs. You would not have to do so if the controller was
properly declared with the 8 master clock input, as it actually is.
It also shows that it is a bad idea to name input after what is coming
in (like you do with "dds_in" or "fclk_div2") instead of what they
actually are like in the AXG (mst0, mst1, etc ...)
>
>>>
>>> By the way, I don't know any example (neither for A1 SoC nor for other
>>> Amlogic's SoCs) where these optional clocks are used, but they are
>>> allowed by hw.
>
> Those scenario exists and have been tested. There is just no dts using
> that upstream because they are all mostly copy of the AML ref design.
>
>>>
>>> This is my understanding of this controller. I hope, Jerome Brunet will
>>> clarify how it actually works.
>>
>
> I think the simpliest way to deal with this to just list all the clocks
> with 'minItems = 1'. It is going be hard to read with a lot of '<0>,' in
> the DTS when do need those slave clocks but at least the binding doc
> will be simple.
>
>> Best regards,
>> Krzysztof
>
> If you are going ahead with this, please name the file
> amlogic,axg-audio-clkc.yaml because this is really the first controller
> of the type and is meant to be documented in the same file.
>
> You are free to handle the conversion of the AXG at the same time if
> you'd like. It would be much appreciated if you do.
--
Jerome
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next prev parent reply other threads:[~2024-04-22 8:08 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-19 12:58 [RFC PATCH v3 0/6] Add A1 Soc audio clock controller driver Jan Dakinevich
2024-04-19 12:58 ` [RFC PATCH v3 1/6] reset: reset-meson-audio: introduce separate driver Jan Dakinevich
2024-04-22 7:46 ` Jerome Brunet
2024-05-14 18:33 ` Jan Dakinevich
2024-04-19 12:58 ` [RFC PATCH v3 2/6] clk: meson: axg: share the set of audio helper macro Jan Dakinevich
2024-04-19 12:58 ` [RFC PATCH v3 3/6] clk: meson: axg: introduce AUD_MUX_TABLE() " Jan Dakinevich
2024-04-22 8:09 ` Jerome Brunet
2024-04-19 12:58 ` [RFC PATCH v3 4/6] dt-bindings: clock: meson: document A1 SoC audio clock controller driver Jan Dakinevich
2024-04-19 14:06 ` Krzysztof Kozlowski
2024-04-20 14:48 ` Jan Dakinevich
2024-04-21 14:02 ` Krzysztof Kozlowski
2024-04-21 15:35 ` Jan Dakinevich
2024-04-21 18:17 ` Krzysztof Kozlowski
2024-04-22 7:43 ` Jerome Brunet
2024-04-19 16:44 ` Rob Herring
2024-04-19 21:09 ` Rob Herring
2024-04-20 16:15 ` Jan Dakinevich
2024-04-21 18:14 ` Krzysztof Kozlowski
2024-04-21 21:03 ` Jan Dakinevich
2024-04-22 7:16 ` Jerome Brunet
2024-04-22 7:57 ` Jerome Brunet [this message]
2024-04-22 14:31 ` Jan Dakinevich
2024-04-22 15:38 ` Jerome Brunet
2024-04-22 15:43 ` Jan Dakinevich
2024-04-22 7:40 ` Jerome Brunet
2024-04-19 12:58 ` [RFC PATCH v3 5/6] clk: meson: a1: add the " Jan Dakinevich
2024-04-22 7:53 ` Jerome Brunet
2024-04-22 13:49 ` Jan Dakinevich
2024-04-19 12:58 ` [RFC PATCH v3 6/6] arm64: dts: meson: a1: add the audio clock controller Jan Dakinevich
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