* [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board
@ 2015-09-05 2:58 Ding Tianhong
2015-09-05 2:58 ` [PATCH 1/2] arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02 Board Ding Tianhong
` (2 more replies)
0 siblings, 3 replies; 16+ messages in thread
From: Ding Tianhong @ 2015-09-05 2:58 UTC (permalink / raw)
To: linux-arm-kernel
Hip05-D02 Development Board is based on Cortex-A57, this patchset
contains initial support for Hip05-D02 Soc and Board. Initial support
is minimal and includes just the arch configuration, device tree
configuration.
PSCI is enabled in device tree and there is no problem to boot all the
16 cores, and the CPU hotplug is also working now, you can download and
compile the latest firmware based on the following link to run this
patch set.
https://github.com/hisilicon/estuary/blob/master/README
v1->v2:
- 1. Change the compatible name for per CPU.
2. Remove the GIC_CPU_MASK_SIMPLE(xx) which is not used for gicv3
from hip05.dtsi.
Ding Tianhong (2):
arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02
Board
arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board
.../bindings/arm/hisilicon/hisilicon.txt | 4 +
arch/arm64/boot/dts/hisilicon/Makefile | 2 +-
arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 +++
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 +++++++++++++++++++++
4 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi
--
1.9.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/2] arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02 Board 2015-09-05 2:58 [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Ding Tianhong @ 2015-09-05 2:58 ` Ding Tianhong 2015-09-05 2:58 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong 2015-09-05 9:18 ` [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Marc Zyngier 2 siblings, 0 replies; 16+ messages in thread From: Ding Tianhong @ 2015-09-05 2:58 UTC (permalink / raw) To: linux-arm-kernel This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon Hip05-D02 development board. Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index c431c67..f98b39d 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -20,6 +20,10 @@ HiKey Board Required root node properties: - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; +HiP05 D02 Board +Required root node properties: + - compatible = "hisilicon,hip05-d02"; + Hisilicon system controller Required properties: -- 1.9.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-09-05 2:58 [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Ding Tianhong 2015-09-05 2:58 ` [PATCH 1/2] arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02 Board Ding Tianhong @ 2015-09-05 2:58 ` Ding Tianhong 2015-09-05 9:28 ` Marc Zyngier 2015-09-05 9:18 ` [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Marc Zyngier 2 siblings, 1 reply; 16+ messages in thread From: Ding Tianhong @ 2015-09-05 2:58 UTC (permalink / raw) To: linux-arm-kernel Add initial dtsi file to support Hisilicon Hip05-D02 Board with support of CPUs in four clusters and each cluster has quard Cortex-A57. Also add dts file to support Hip05-D02 development board. Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/boot/dts/hisilicon/Makefile | 2 +- arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile index fa81a6e..cd158b8 100644 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ b/arch/arm64/boot/dts/hisilicon/Makefile @@ -1,4 +1,4 @@ -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts new file mode 100644 index 0000000..ae34e25 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -0,0 +1,36 @@ +/** + * dts file for Hisilicon D02 Development Board + * + * Copyright (C) 2014,2015 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include "hip05.dtsi" + +/ { + model = "Hisilicon Hip05 D02 Development Board"; + compatible = "hisilicon,hip05-d02"; + + memory at 00000000 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x80000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi new file mode 100644 index 0000000..92d00f4 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -0,0 +1,271 @@ +/** + * dts file for Hisilicon D02 Development Board + * + * Copyright (C) 2014,2015 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "hisilicon,hip05-d02"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + }; + + cpu0: cpu at 20000 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20000>; + enable-method = "psci"; + }; + + cpu1: cpu at 20001 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20001>; + enable-method = "psci"; + }; + + cpu2: cpu at 20002 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20002>; + enable-method = "psci"; + }; + + cpu3: cpu at 20003 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20003>; + enable-method = "psci"; + }; + + cpu4: cpu at 20100 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20100>; + enable-method = "psci"; + }; + + cpu5: cpu at 20101 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20101>; + enable-method = "psci"; + }; + + cpu6: cpu at 20102 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20102>; + enable-method = "psci"; + }; + + cpu7: cpu at 20103 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20103>; + enable-method = "psci"; + }; + + cpu8: cpu at 20200 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20200>; + enable-method = "psci"; + }; + + cpu9: cpu at 20201 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20201>; + enable-method = "psci"; + }; + + cpu10: cpu at 20202 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20202>; + enable-method = "psci"; + }; + + cpu11: cpu at 20203 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20203>; + enable-method = "psci"; + }; + + cpu12: cpu at 20300 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20300>; + enable-method = "psci"; + }; + + cpu13: cpu at 20301 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20301>; + enable-method = "psci"; + }; + + cpu14: cpu at 20302 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20302>; + enable-method = "psci"; + }; + + cpu15: cpu at 20303 { + device_type = "cpu"; + compatible = "hisilicon,hip05", "arm,armv8"; + reg = <0x20303>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller at 8d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x30000>; + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ + <0x0 0x8d100000 0 0x300000>, /* GICR */ + <0x0 0xfe000000 0 0x10000>, /* GICC */ + <0x0 0xfe010000 0 0x10000>, /* GICH */ + <0x0 0xfe020000 0 0x10000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + its_totems: interrupt-controller at 8c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x8c000000 0x0 0x1000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk200mhz: refclk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart0: uart at 80300000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80300000 0x0 0x10000>; + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclk200mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: uart at 80310000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80310000 0x0 0x10000>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclk200mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +}; -- 1.9.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-09-05 2:58 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong @ 2015-09-05 9:28 ` Marc Zyngier 2015-09-06 2:47 ` Ding Tianhong 0 siblings, 1 reply; 16+ messages in thread From: Marc Zyngier @ 2015-09-05 9:28 UTC (permalink / raw) To: linux-arm-kernel On Sat, 5 Sep 2015 10:58:59 +0800 Ding Tianhong <dingtianhong@huawei.com> wrote: > Add initial dtsi file to support Hisilicon Hip05-D02 Board with > support of CPUs in four clusters and each cluster has quard Cortex-A57. > > Also add dts file to support Hip05-D02 development board. > > Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> > Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> > --- > arch/arm64/boot/dts/hisilicon/Makefile | 2 +- > arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ > arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ > 3 files changed, 308 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts > create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi > > diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile > index fa81a6e..cd158b8 100644 > --- a/arch/arm64/boot/dts/hisilicon/Makefile > +++ b/arch/arm64/boot/dts/hisilicon/Makefile > @@ -1,4 +1,4 @@ > -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb > +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts > new file mode 100644 > index 0000000..ae34e25 > --- /dev/null > +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts > @@ -0,0 +1,36 @@ > +/** > + * dts file for Hisilicon D02 Development Board > + * > + * Copyright (C) 2014,2015 Hisilicon Ltd. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * publishhed by the Free Software Foundation. > + * > + */ > + > +/dts-v1/; > + > +#include "hip05.dtsi" > + > +/ { > + model = "Hisilicon Hip05 D02 Development Board"; > + compatible = "hisilicon,hip05-d02"; > + > + memory at 00000000 { > + device_type = "memory"; > + reg = <0x0 0x00000000 0x0 0x80000000>; > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + status = "ok"; > +}; > diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > new file mode 100644 > index 0000000..92d00f4 > --- /dev/null > +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > @@ -0,0 +1,271 @@ > +/** > + * dts file for Hisilicon D02 Development Board > + * > + * Copyright (C) 2014,2015 Hisilicon Ltd. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * publishhed by the Free Software Foundation. > + * > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + compatible = "hisilicon,hip05-d02"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + cluster2 { > + core0 { > + cpu = <&cpu8>; > + }; > + core1 { > + cpu = <&cpu9>; > + }; > + core2 { > + cpu = <&cpu10>; > + }; > + core3 { > + cpu = <&cpu11>; > + }; > + }; > + cluster3 { > + core0 { > + cpu = <&cpu12>; > + }; > + core1 { > + cpu = <&cpu13>; > + }; > + core2 { > + cpu = <&cpu14>; > + }; > + core3 { > + cpu = <&cpu15>; > + }; > + }; > + }; > + > + cpu0: cpu at 20000 { > + device_type = "cpu"; > + compatible = "hisilicon,hip05", "arm,armv8"; Your cover letter says: "Hip05-D02 Development Board is based on Cortex-A57". So "hisilicon,hip05" has nothing to do here. This should read "arm,cortex-a57" (the SoC name is irrelevant for a cpu node). Apparently I'm not the first one to mention that to you, so please address this in your next version. [...] > + gic: interrupt-controller at 8d000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x30000>; Really? You redistributors are 192kB apart? > + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ > + <0x0 0x8d100000 0 0x300000>, /* GICR */ > + <0x0 0xfe000000 0 0x10000>, /* GICC */ > + <0x0 0xfe010000 0 0x10000>, /* GICH */ > + <0x0 0xfe020000 0 0x10000>; /* GICV */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + its_totems: interrupt-controller at 8c000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0x8c000000 0x0 0x1000000>; Why is the ITS region that big? It should normally only be 128kB. Thanks, M. -- Jazz is not dead. It just smells funny. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-09-05 9:28 ` Marc Zyngier @ 2015-09-06 2:47 ` Ding Tianhong 0 siblings, 0 replies; 16+ messages in thread From: Ding Tianhong @ 2015-09-06 2:47 UTC (permalink / raw) To: linux-arm-kernel On 2015/9/5 17:28, Marc Zyngier wrote: > On Sat, 5 Sep 2015 10:58:59 +0800 > Ding Tianhong <dingtianhong@huawei.com> wrote: > >> Add initial dtsi file to support Hisilicon Hip05-D02 Board with >> support of CPUs in four clusters and each cluster has quard Cortex-A57. >> >> Also add dts file to support Hip05-D02 development board. >> >> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> >> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> >> --- >> arch/arm64/boot/dts/hisilicon/Makefile | 2 +- >> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ >> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ >> 3 files changed, 308 insertions(+), 1 deletion(-) >> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts >> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi >> >> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile >> index fa81a6e..cd158b8 100644 >> --- a/arch/arm64/boot/dts/hisilicon/Makefile >> +++ b/arch/arm64/boot/dts/hisilicon/Makefile >> @@ -1,4 +1,4 @@ >> -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb >> +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb >> >> always := $(dtb-y) >> subdir-y := $(dts-dirs) >> diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >> new file mode 100644 >> index 0000000..ae34e25 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >> @@ -0,0 +1,36 @@ >> +/** >> + * dts file for Hisilicon D02 Development Board >> + * >> + * Copyright (C) 2014,2015 Hisilicon Ltd. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * publishhed by the Free Software Foundation. >> + * >> + */ >> + >> +/dts-v1/; >> + >> +#include "hip05.dtsi" >> + >> +/ { >> + model = "Hisilicon Hip05 D02 Development Board"; >> + compatible = "hisilicon,hip05-d02"; >> + >> + memory at 00000000 { >> + device_type = "memory"; >> + reg = <0x0 0x00000000 0x0 0x80000000>; >> + }; >> + >> + aliases { >> + serial0 = &uart0; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> +}; >> + >> +&uart0 { >> + status = "ok"; >> +}; >> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >> new file mode 100644 >> index 0000000..92d00f4 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >> @@ -0,0 +1,271 @@ >> +/** >> + * dts file for Hisilicon D02 Development Board >> + * >> + * Copyright (C) 2014,2015 Hisilicon Ltd. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * publishhed by the Free Software Foundation. >> + * >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +/ { >> + compatible = "hisilicon,hip05-d02"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu0>; >> + }; >> + core1 { >> + cpu = <&cpu1>; >> + }; >> + core2 { >> + cpu = <&cpu2>; >> + }; >> + core3 { >> + cpu = <&cpu3>; >> + }; >> + }; >> + cluster1 { >> + core0 { >> + cpu = <&cpu4>; >> + }; >> + core1 { >> + cpu = <&cpu5>; >> + }; >> + core2 { >> + cpu = <&cpu6>; >> + }; >> + core3 { >> + cpu = <&cpu7>; >> + }; >> + }; >> + cluster2 { >> + core0 { >> + cpu = <&cpu8>; >> + }; >> + core1 { >> + cpu = <&cpu9>; >> + }; >> + core2 { >> + cpu = <&cpu10>; >> + }; >> + core3 { >> + cpu = <&cpu11>; >> + }; >> + }; >> + cluster3 { >> + core0 { >> + cpu = <&cpu12>; >> + }; >> + core1 { >> + cpu = <&cpu13>; >> + }; >> + core2 { >> + cpu = <&cpu14>; >> + }; >> + core3 { >> + cpu = <&cpu15>; >> + }; >> + }; >> + }; >> + >> + cpu0: cpu at 20000 { >> + device_type = "cpu"; >> + compatible = "hisilicon,hip05", "arm,armv8"; > > Your cover letter says: "Hip05-D02 Development Board is based on > Cortex-A57". So "hisilicon,hip05" has nothing to do here. This should > read "arm,cortex-a57" (the SoC name is irrelevant for a cpu node). > > Apparently I'm not the first one to mention that to you, so please > address this in your next version. > Ok. > [...] > >> + gic: interrupt-controller at 8d000000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + interrupt-controller; >> + #redistributor-regions = <1>; >> + redistributor-stride = <0x0 0x30000>; > > Really? You redistributors are 192kB apart? Yes, our chip need 192kb for GICR. > >> + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ >> + <0x0 0x8d100000 0 0x300000>, /* GICR */ >> + <0x0 0xfe000000 0 0x10000>, /* GICC */ >> + <0x0 0xfe010000 0 0x10000>, /* GICH */ >> + <0x0 0xfe020000 0 0x10000>; /* GICV */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + >> + its_totems: interrupt-controller at 8c000000 { >> + compatible = "arm,gic-v3-its"; >> + msi-controller; >> + reg = <0x0 0x8c000000 0x0 0x1000000>; > > Why is the ITS region that big? It should normally only be 128kB. > Yes, No need to reserve so big memory for ITS, actually 256kb is enough, fix it in next version, thanks. Ding > Thanks, > > M. > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board 2015-09-05 2:58 [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Ding Tianhong 2015-09-05 2:58 ` [PATCH 1/2] arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02 Board Ding Tianhong 2015-09-05 2:58 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong @ 2015-09-05 9:18 ` Marc Zyngier 2015-09-06 2:40 ` Ding Tianhong 2 siblings, 1 reply; 16+ messages in thread From: Marc Zyngier @ 2015-09-05 9:18 UTC (permalink / raw) To: linux-arm-kernel On Sat, 5 Sep 2015 10:58:57 +0800 Ding Tianhong <dingtianhong@huawei.com> wrote: > Hip05-D02 Development Board is based on Cortex-A57, this patchset > contains initial support for Hip05-D02 Soc and Board. Initial support > is minimal and includes just the arch configuration, device tree > configuration. > > PSCI is enabled in device tree and there is no problem to boot all the > 16 cores, and the CPU hotplug is also working now, you can download and > compile the latest firmware based on the following link to run this > patch set. > > https://github.com/hisilicon/estuary/blob/master/README > > v1->v2: > - 1. Change the compatible name for per CPU. > 2. Remove the GIC_CPU_MASK_SIMPLE(xx) which is not used for gicv3 > from hip05.dtsi. Please always indicate the version number in the email subject ("PATCH v2" is the usual scheme). It makes it otherwise difficult to keep track of what version I am looking at. Thanks, M. -- Jazz is not dead. It just smells funny. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board 2015-09-05 9:18 ` [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Marc Zyngier @ 2015-09-06 2:40 ` Ding Tianhong 0 siblings, 0 replies; 16+ messages in thread From: Ding Tianhong @ 2015-09-06 2:40 UTC (permalink / raw) To: linux-arm-kernel On 2015/9/5 17:18, Marc Zyngier wrote: > On Sat, 5 Sep 2015 10:58:57 +0800 > Ding Tianhong <dingtianhong@huawei.com> wrote: > >> Hip05-D02 Development Board is based on Cortex-A57, this patchset >> contains initial support for Hip05-D02 Soc and Board. Initial support >> is minimal and includes just the arch configuration, device tree >> configuration. >> >> PSCI is enabled in device tree and there is no problem to boot all the >> 16 cores, and the CPU hotplug is also working now, you can download and >> compile the latest firmware based on the following link to run this >> patch set. >> >> https://github.com/hisilicon/estuary/blob/master/README >> >> v1->v2: >> - 1. Change the compatible name for per CPU. >> 2. Remove the GIC_CPU_MASK_SIMPLE(xx) which is not used for gicv3 >> from hip05.dtsi. > > Please always indicate the version number in the email subject ("PATCH > v2" is the usual scheme). It makes it otherwise difficult to keep track > of what version I am looking at. > > Thanks, > Miss it, fix it in next version, thanks. Ding > M. > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board
@ 2015-08-29 8:52 Ding Tianhong
2015-08-29 8:52 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong
0 siblings, 1 reply; 16+ messages in thread
From: Ding Tianhong @ 2015-08-29 8:52 UTC (permalink / raw)
To: linux-arm-kernel
Hip05-D02 Development Board is based on Cortex-A57, this patchset
contains initial support for Hip05-D02 Soc and Board. Initial support
is minimal and includes just the arch configuration, device tree
configuration.
PSCI is enabled in device tree and there is no problem to boot all the
16 cores, and the CPU hotplug is also working now, you can download and
compile the latest firmware based on the following link to run this
patch set.
https://github.com/hisilicon/estuary/blob/master/README
Ding Tianhong (2):
arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02
Board
arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board
.../bindings/arm/hisilicon/hisilicon.txt | 4 +
arch/arm64/boot/dts/hisilicon/Makefile | 2 +-
arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 +++
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 +++++++++++++++++++++
4 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi
--
1.9.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-08-29 8:52 Ding Tianhong @ 2015-08-29 8:52 ` Ding Tianhong 2015-08-31 13:12 ` Leo Yan 0 siblings, 1 reply; 16+ messages in thread From: Ding Tianhong @ 2015-08-29 8:52 UTC (permalink / raw) To: linux-arm-kernel Add initial dtsi file to support Hisilicon Hip05-D02 Board with support of CPUs in four clusters and each cluster has quard Cortex-A57. Also add dts file to support Hip05-D02 development board. Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/boot/dts/hisilicon/Makefile | 2 +- arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile index fa81a6e..cd158b8 100644 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ b/arch/arm64/boot/dts/hisilicon/Makefile @@ -1,4 +1,4 @@ -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts new file mode 100644 index 0000000..ae34e25 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -0,0 +1,36 @@ +/** + * dts file for Hisilicon D02 Development Board + * + * Copyright (C) 2014,2015 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include "hip05.dtsi" + +/ { + model = "Hisilicon Hip05 D02 Development Board"; + compatible = "hisilicon,hip05-d02"; + + memory at 00000000 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x80000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi new file mode 100644 index 0000000..da12d94 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -0,0 +1,271 @@ +/** + * dts file for Hisilicon D02 Development Board + * + * Copyright (C) 2014,2015 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "hisilicon,hip05-d02"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + }; + + cpu0: cpu at 20000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20000>; + enable-method = "psci"; + }; + + cpu1: cpu at 20001 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20001>; + enable-method = "psci"; + }; + + cpu2: cpu at 20002 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20002>; + enable-method = "psci"; + }; + + cpu3: cpu at 20003 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20003>; + enable-method = "psci"; + }; + + cpu4: cpu at 20100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20100>; + enable-method = "psci"; + }; + + cpu5: cpu at 20101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20101>; + enable-method = "psci"; + }; + + cpu6: cpu at 20102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20102>; + enable-method = "psci"; + }; + + cpu7: cpu at 20103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20103>; + enable-method = "psci"; + }; + + cpu8: cpu at 20200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20200>; + enable-method = "psci"; + }; + + cpu9: cpu at 20201 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20201>; + enable-method = "psci"; + }; + + cpu10: cpu at 20202 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20202>; + enable-method = "psci"; + }; + + cpu11: cpu at 20203 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20203>; + enable-method = "psci"; + }; + + cpu12: cpu at 20300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20300>; + enable-method = "psci"; + }; + + cpu13: cpu at 20301 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20301>; + enable-method = "psci"; + }; + + cpu14: cpu at 20302 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20302>; + enable-method = "psci"; + }; + + cpu15: cpu at 20303 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20303>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller at 8d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x30000>; + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ + <0x0 0x8d100000 0 0x300000>, /* GICR */ + <0x0 0xfe000000 0 0x10000>, /* GICC */ + <0x0 0xfe010000 0 0x10000>, /* GICH */ + <0x0 0xfe020000 0 0x10000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + + its_totems: interrupt-controller at 8c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x8c000000 0x0 0x1000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk200mhz: refclk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart0: uart at 80300000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80300000 0x0 0x10000>; + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclk200mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: uart at 80310000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80310000 0x0 0x10000>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclk200mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +}; -- 1.9.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-08-29 8:52 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong @ 2015-08-31 13:12 ` Leo Yan 2015-08-31 13:44 ` Ding Tianhong 0 siblings, 1 reply; 16+ messages in thread From: Leo Yan @ 2015-08-31 13:12 UTC (permalink / raw) To: linux-arm-kernel On Sat, Aug 29, 2015 at 04:52:41PM +0800, Ding Tianhong wrote: > Add initial dtsi file to support Hisilicon Hip05-D02 Board with > support of CPUs in four clusters and each cluster has quard Cortex-A57. > > Also add dts file to support Hip05-D02 development board. > > Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> > Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> > --- > arch/arm64/boot/dts/hisilicon/Makefile | 2 +- > arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ > arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ > 3 files changed, 308 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts > create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi > > diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile > index fa81a6e..cd158b8 100644 > --- a/arch/arm64/boot/dts/hisilicon/Makefile > +++ b/arch/arm64/boot/dts/hisilicon/Makefile > @@ -1,4 +1,4 @@ > -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb > +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts > new file mode 100644 > index 0000000..ae34e25 > --- /dev/null > +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts > @@ -0,0 +1,36 @@ > +/** > + * dts file for Hisilicon D02 Development Board > + * > + * Copyright (C) 2014,2015 Hisilicon Ltd. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * publishhed by the Free Software Foundation. > + * > + */ > + > +/dts-v1/; > + > +#include "hip05.dtsi" > + > +/ { > + model = "Hisilicon Hip05 D02 Development Board"; > + compatible = "hisilicon,hip05-d02"; > + > + memory at 00000000 { > + device_type = "memory"; > + reg = <0x0 0x00000000 0x0 0x80000000>; > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + status = "ok"; > +}; > diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > new file mode 100644 > index 0000000..da12d94 > --- /dev/null > +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > @@ -0,0 +1,271 @@ > +/** > + * dts file for Hisilicon D02 Development Board > + * > + * Copyright (C) 2014,2015 Hisilicon Ltd. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * publishhed by the Free Software Foundation. > + * > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + compatible = "hisilicon,hip05-d02"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + cluster2 { > + core0 { > + cpu = <&cpu8>; > + }; > + core1 { > + cpu = <&cpu9>; > + }; > + core2 { > + cpu = <&cpu10>; > + }; > + core3 { > + cpu = <&cpu11>; > + }; > + }; > + cluster3 { > + core0 { > + cpu = <&cpu12>; > + }; > + core1 { > + cpu = <&cpu13>; > + }; > + core2 { > + cpu = <&cpu14>; > + }; > + core3 { > + cpu = <&cpu15>; > + }; > + }; > + }; > + > + cpu0: cpu at 20000 { > + device_type = "cpu"; > + compatible = "arm,armv8"; Change to "arm,cortex-a57","arm,armv8"? > + reg = <0x20000>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu at 20001 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20001>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu at 20002 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20002>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu at 20003 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20003>; > + enable-method = "psci"; > + }; > + > + cpu4: cpu at 20100 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20100>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu at 20101 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20101>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu at 20102 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20102>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu at 20103 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20103>; > + enable-method = "psci"; > + }; > + > + cpu8: cpu at 20200 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20200>; > + enable-method = "psci"; > + }; > + > + cpu9: cpu at 20201 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20201>; > + enable-method = "psci"; > + }; > + > + cpu10: cpu at 20202 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20202>; > + enable-method = "psci"; > + }; > + > + cpu11: cpu at 20203 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20203>; > + enable-method = "psci"; > + }; > + > + cpu12: cpu at 20300 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20300>; > + enable-method = "psci"; > + }; > + > + cpu13: cpu at 20301 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20301>; > + enable-method = "psci"; > + }; > + > + cpu14: cpu at 20302 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20302>; > + enable-method = "psci"; > + }; > + > + cpu15: cpu at 20303 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x20303>; > + enable-method = "psci"; > + }; > + }; > + > + gic: interrupt-controller at 8d000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x30000>; > + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ > + <0x0 0x8d100000 0 0x300000>, /* GICR */ > + <0x0 0xfe000000 0 0x10000>, /* GICC */ > + <0x0 0xfe010000 0 0x10000>, /* GICH */ > + <0x0 0xfe020000 0 0x10000>; /* GICV */ > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; > + > + its_totems: interrupt-controller at 8c000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0x8c000000 0x0 0x1000000>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; Here have a question: In devcie tree binding file: Documentation/devicetree/bindings/arm/gic.txt, it only considers for maximum 8 cpus. So will we need change the binding file and also use GIC_CPU_MASK_SIMPLE(16) for 16 cores? > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + refclk200mhz: refclk200mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + }; > + > + uart0: uart at 80300000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x80300000 0x0 0x10000>; > + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&refclk200mhz>; > + clock-names = "apb_pclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart1: uart at 80310000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x80310000 0x0 0x10000>; > + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&refclk200mhz>; > + clock-names = "apb_pclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + }; > +}; > -- > 1.9.0 > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-08-31 13:12 ` Leo Yan @ 2015-08-31 13:44 ` Ding Tianhong 2015-08-31 14:40 ` Leo Yan 2015-09-02 4:28 ` Ding Tianhong 0 siblings, 2 replies; 16+ messages in thread From: Ding Tianhong @ 2015-08-31 13:44 UTC (permalink / raw) To: linux-arm-kernel On 2015/8/31 21:12, Leo Yan wrote: > On Sat, Aug 29, 2015 at 04:52:41PM +0800, Ding Tianhong wrote: >> Add initial dtsi file to support Hisilicon Hip05-D02 Board with >> support of CPUs in four clusters and each cluster has quard Cortex-A57. >> >> Also add dts file to support Hip05-D02 development board. >> >> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> >> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> >> --- >> arch/arm64/boot/dts/hisilicon/Makefile | 2 +- >> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ >> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ >> 3 files changed, 308 insertions(+), 1 deletion(-) >> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts >> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi >> >> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile >> index fa81a6e..cd158b8 100644 >> --- a/arch/arm64/boot/dts/hisilicon/Makefile >> +++ b/arch/arm64/boot/dts/hisilicon/Makefile >> @@ -1,4 +1,4 @@ >> -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb >> +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb >> >> always := $(dtb-y) >> subdir-y := $(dts-dirs) >> diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >> new file mode 100644 >> index 0000000..ae34e25 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >> @@ -0,0 +1,36 @@ >> +/** >> + * dts file for Hisilicon D02 Development Board >> + * >> + * Copyright (C) 2014,2015 Hisilicon Ltd. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * publishhed by the Free Software Foundation. >> + * >> + */ >> + >> +/dts-v1/; >> + >> +#include "hip05.dtsi" >> + >> +/ { >> + model = "Hisilicon Hip05 D02 Development Board"; >> + compatible = "hisilicon,hip05-d02"; >> + >> + memory at 00000000 { >> + device_type = "memory"; >> + reg = <0x0 0x00000000 0x0 0x80000000>; >> + }; >> + >> + aliases { >> + serial0 = &uart0; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> +}; >> + >> +&uart0 { >> + status = "ok"; >> +}; >> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >> new file mode 100644 >> index 0000000..da12d94 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >> @@ -0,0 +1,271 @@ >> +/** >> + * dts file for Hisilicon D02 Development Board >> + * >> + * Copyright (C) 2014,2015 Hisilicon Ltd. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * publishhed by the Free Software Foundation. >> + * >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +/ { >> + compatible = "hisilicon,hip05-d02"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu0>; >> + }; >> + core1 { >> + cpu = <&cpu1>; >> + }; >> + core2 { >> + cpu = <&cpu2>; >> + }; >> + core3 { >> + cpu = <&cpu3>; >> + }; >> + }; >> + cluster1 { >> + core0 { >> + cpu = <&cpu4>; >> + }; >> + core1 { >> + cpu = <&cpu5>; >> + }; >> + core2 { >> + cpu = <&cpu6>; >> + }; >> + core3 { >> + cpu = <&cpu7>; >> + }; >> + }; >> + cluster2 { >> + core0 { >> + cpu = <&cpu8>; >> + }; >> + core1 { >> + cpu = <&cpu9>; >> + }; >> + core2 { >> + cpu = <&cpu10>; >> + }; >> + core3 { >> + cpu = <&cpu11>; >> + }; >> + }; >> + cluster3 { >> + core0 { >> + cpu = <&cpu12>; >> + }; >> + core1 { >> + cpu = <&cpu13>; >> + }; >> + core2 { >> + cpu = <&cpu14>; >> + }; >> + core3 { >> + cpu = <&cpu15>; >> + }; >> + }; >> + }; >> + >> + cpu0: cpu at 20000 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; > > Change to "arm,cortex-a57","arm,armv8"? > Ok?but I think should be "hisilicon,hip05","arm,armv8". >> + reg = <0x20000>; >> + enable-method = "psci"; >> + }; >> + >> + cpu1: cpu at 20001 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20001>; >> + enable-method = "psci"; >> + }; >> + >> + cpu2: cpu at 20002 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20002>; >> + enable-method = "psci"; >> + }; >> + >> + cpu3: cpu at 20003 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20003>; >> + enable-method = "psci"; >> + }; >> + >> + cpu4: cpu at 20100 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20100>; >> + enable-method = "psci"; >> + }; >> + >> + cpu5: cpu at 20101 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20101>; >> + enable-method = "psci"; >> + }; >> + >> + cpu6: cpu at 20102 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20102>; >> + enable-method = "psci"; >> + }; >> + >> + cpu7: cpu at 20103 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20103>; >> + enable-method = "psci"; >> + }; >> + >> + cpu8: cpu at 20200 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20200>; >> + enable-method = "psci"; >> + }; >> + >> + cpu9: cpu at 20201 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20201>; >> + enable-method = "psci"; >> + }; >> + >> + cpu10: cpu at 20202 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20202>; >> + enable-method = "psci"; >> + }; >> + >> + cpu11: cpu at 20203 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20203>; >> + enable-method = "psci"; >> + }; >> + >> + cpu12: cpu at 20300 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20300>; >> + enable-method = "psci"; >> + }; >> + >> + cpu13: cpu at 20301 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20301>; >> + enable-method = "psci"; >> + }; >> + >> + cpu14: cpu at 20302 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20302>; >> + enable-method = "psci"; >> + }; >> + >> + cpu15: cpu at 20303 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x20303>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + gic: interrupt-controller at 8d000000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + interrupt-controller; >> + #redistributor-regions = <1>; >> + redistributor-stride = <0x0 0x30000>; >> + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ >> + <0x0 0x8d100000 0 0x300000>, /* GICR */ >> + <0x0 0xfe000000 0 0x10000>, /* GICC */ >> + <0x0 0xfe010000 0 0x10000>, /* GICH */ >> + <0x0 0xfe020000 0 0x10000>; /* GICV */ >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; >> + >> + its_totems: interrupt-controller at 8c000000 { >> + compatible = "arm,gic-v3-its"; >> + msi-controller; >> + reg = <0x0 0x8c000000 0x0 0x1000000>; >> + }; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > > Here have a question: > In devcie tree binding file: Documentation/devicetree/bindings/arm/gic.txt, > it only considers for maximum 8 cpus. So will we need change the > binding file and also use GIC_CPU_MASK_SIMPLE(16) for 16 cores? > Looks like should updtate gic.txt and use the GIC_CPU_MASK_SIMPLE(16) for 16 cores. Ding >> + }; >> + >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + soc { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + refclk200mhz: refclk200mhz { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <200000000>; >> + }; >> + >> + uart0: uart at 80300000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x0 0x80300000 0x0 0x10000>; >> + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&refclk200mhz>; >> + clock-names = "apb_pclk"; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + status = "disabled"; >> + }; >> + >> + uart1: uart at 80310000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x0 0x80310000 0x0 0x10000>; >> + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&refclk200mhz>; >> + clock-names = "apb_pclk"; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + status = "disabled"; >> + }; >> + }; >> +}; >> -- >> 1.9.0 >> >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel at lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > . > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-08-31 13:44 ` Ding Tianhong @ 2015-08-31 14:40 ` Leo Yan 2015-09-01 1:14 ` Ding Tianhong 2015-09-02 4:28 ` Ding Tianhong 1 sibling, 1 reply; 16+ messages in thread From: Leo Yan @ 2015-08-31 14:40 UTC (permalink / raw) To: linux-arm-kernel On Mon, Aug 31, 2015 at 09:44:38PM +0800, Ding Tianhong wrote: > On 2015/8/31 21:12, Leo Yan wrote: > > On Sat, Aug 29, 2015 at 04:52:41PM +0800, Ding Tianhong wrote: > >> Add initial dtsi file to support Hisilicon Hip05-D02 Board with > >> support of CPUs in four clusters and each cluster has quard Cortex-A57. > >> > >> Also add dts file to support Hip05-D02 development board. > >> > >> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> > >> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> > >> --- > >> arch/arm64/boot/dts/hisilicon/Makefile | 2 +- > >> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ > >> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ > >> 3 files changed, 308 insertions(+), 1 deletion(-) > >> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts > >> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi > >> > >> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile > >> index fa81a6e..cd158b8 100644 > >> --- a/arch/arm64/boot/dts/hisilicon/Makefile > >> +++ b/arch/arm64/boot/dts/hisilicon/Makefile > >> @@ -1,4 +1,4 @@ > >> -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb > >> +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb > >> > >> always := $(dtb-y) > >> subdir-y := $(dts-dirs) > >> diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts > >> new file mode 100644 > >> index 0000000..ae34e25 > >> --- /dev/null > >> +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts > >> @@ -0,0 +1,36 @@ > >> +/** > >> + * dts file for Hisilicon D02 Development Board > >> + * > >> + * Copyright (C) 2014,2015 Hisilicon Ltd. > >> + * > >> + * This program is free software; you can redistribute it and/or modify > >> + * it under the terms of the GNU General Public License version 2 as > >> + * publishhed by the Free Software Foundation. > >> + * > >> + */ > >> + > >> +/dts-v1/; > >> + > >> +#include "hip05.dtsi" > >> + > >> +/ { > >> + model = "Hisilicon Hip05 D02 Development Board"; > >> + compatible = "hisilicon,hip05-d02"; > >> + > >> + memory at 00000000 { > >> + device_type = "memory"; > >> + reg = <0x0 0x00000000 0x0 0x80000000>; > >> + }; > >> + > >> + aliases { > >> + serial0 = &uart0; > >> + }; > >> + > >> + chosen { > >> + stdout-path = "serial0:115200n8"; > >> + }; > >> +}; > >> + > >> +&uart0 { > >> + status = "ok"; > >> +}; > >> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > >> new file mode 100644 > >> index 0000000..da12d94 > >> --- /dev/null > >> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > >> @@ -0,0 +1,271 @@ > >> +/** > >> + * dts file for Hisilicon D02 Development Board > >> + * > >> + * Copyright (C) 2014,2015 Hisilicon Ltd. > >> + * > >> + * This program is free software; you can redistribute it and/or modify > >> + * it under the terms of the GNU General Public License version 2 as > >> + * publishhed by the Free Software Foundation. > >> + * > >> + */ > >> + > >> +#include <dt-bindings/interrupt-controller/arm-gic.h> > >> + > >> +/ { > >> + compatible = "hisilicon,hip05-d02"; > >> + interrupt-parent = <&gic>; > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + > >> + psci { > >> + compatible = "arm,psci-0.2"; > >> + method = "smc"; > >> + }; > >> + > >> + cpus { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + > >> + cpu-map { > >> + cluster0 { > >> + core0 { > >> + cpu = <&cpu0>; > >> + }; > >> + core1 { > >> + cpu = <&cpu1>; > >> + }; > >> + core2 { > >> + cpu = <&cpu2>; > >> + }; > >> + core3 { > >> + cpu = <&cpu3>; > >> + }; > >> + }; > >> + cluster1 { > >> + core0 { > >> + cpu = <&cpu4>; > >> + }; > >> + core1 { > >> + cpu = <&cpu5>; > >> + }; > >> + core2 { > >> + cpu = <&cpu6>; > >> + }; > >> + core3 { > >> + cpu = <&cpu7>; > >> + }; > >> + }; > >> + cluster2 { > >> + core0 { > >> + cpu = <&cpu8>; > >> + }; > >> + core1 { > >> + cpu = <&cpu9>; > >> + }; > >> + core2 { > >> + cpu = <&cpu10>; > >> + }; > >> + core3 { > >> + cpu = <&cpu11>; > >> + }; > >> + }; > >> + cluster3 { > >> + core0 { > >> + cpu = <&cpu12>; > >> + }; > >> + core1 { > >> + cpu = <&cpu13>; > >> + }; > >> + core2 { > >> + cpu = <&cpu14>; > >> + }; > >> + core3 { > >> + cpu = <&cpu15>; > >> + }; > >> + }; > >> + }; > >> + > >> + cpu0: cpu at 20000 { > >> + device_type = "cpu"; > >> + compatible = "arm,armv8"; > > > > Change to "arm,cortex-a57","arm,armv8"? > > > > Ok?but I think should be "hisilicon,hip05","arm,armv8". If the CPU is a starndard ARM core (such like CA53, CA57, etc), you need directly use the CPU type which has been defined in: Documentation/devicetree/bindings/arm/cpus.txt. So here hip05 is the naming code for SoC? or for the CPU customized by Hisilicon? [...] Thanks, Leo Yan ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-08-31 14:40 ` Leo Yan @ 2015-09-01 1:14 ` Ding Tianhong 0 siblings, 0 replies; 16+ messages in thread From: Ding Tianhong @ 2015-09-01 1:14 UTC (permalink / raw) To: linux-arm-kernel On 2015/8/31 22:40, Leo Yan wrote: > On Mon, Aug 31, 2015 at 09:44:38PM +0800, Ding Tianhong wrote: >> On 2015/8/31 21:12, Leo Yan wrote: >>> On Sat, Aug 29, 2015 at 04:52:41PM +0800, Ding Tianhong wrote: >>>> Add initial dtsi file to support Hisilicon Hip05-D02 Board with >>>> support of CPUs in four clusters and each cluster has quard Cortex-A57. >>>> >>>> Also add dts file to support Hip05-D02 development board. >>>> >>>> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> >>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> >>>> --- >>>> arch/arm64/boot/dts/hisilicon/Makefile | 2 +- >>>> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ >>>> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ >>>> 3 files changed, 308 insertions(+), 1 deletion(-) >>>> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>> >>>> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile >>>> index fa81a6e..cd158b8 100644 >>>> --- a/arch/arm64/boot/dts/hisilicon/Makefile >>>> +++ b/arch/arm64/boot/dts/hisilicon/Makefile >>>> @@ -1,4 +1,4 @@ >>>> -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb >>>> +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb >>>> >>>> always := $(dtb-y) >>>> subdir-y := $(dts-dirs) >>>> diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>> new file mode 100644 >>>> index 0000000..ae34e25 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>> @@ -0,0 +1,36 @@ >>>> +/** >>>> + * dts file for Hisilicon D02 Development Board >>>> + * >>>> + * Copyright (C) 2014,2015 Hisilicon Ltd. >>>> + * >>>> + * This program is free software; you can redistribute it and/or modify >>>> + * it under the terms of the GNU General Public License version 2 as >>>> + * publishhed by the Free Software Foundation. >>>> + * >>>> + */ >>>> + >>>> +/dts-v1/; >>>> + >>>> +#include "hip05.dtsi" >>>> + >>>> +/ { >>>> + model = "Hisilicon Hip05 D02 Development Board"; >>>> + compatible = "hisilicon,hip05-d02"; >>>> + >>>> + memory at 00000000 { >>>> + device_type = "memory"; >>>> + reg = <0x0 0x00000000 0x0 0x80000000>; >>>> + }; >>>> + >>>> + aliases { >>>> + serial0 = &uart0; >>>> + }; >>>> + >>>> + chosen { >>>> + stdout-path = "serial0:115200n8"; >>>> + }; >>>> +}; >>>> + >>>> +&uart0 { >>>> + status = "ok"; >>>> +}; >>>> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>> new file mode 100644 >>>> index 0000000..da12d94 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>> @@ -0,0 +1,271 @@ >>>> +/** >>>> + * dts file for Hisilicon D02 Development Board >>>> + * >>>> + * Copyright (C) 2014,2015 Hisilicon Ltd. >>>> + * >>>> + * This program is free software; you can redistribute it and/or modify >>>> + * it under the terms of the GNU General Public License version 2 as >>>> + * publishhed by the Free Software Foundation. >>>> + * >>>> + */ >>>> + >>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>> + >>>> +/ { >>>> + compatible = "hisilicon,hip05-d02"; >>>> + interrupt-parent = <&gic>; >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>>> + psci { >>>> + compatible = "arm,psci-0.2"; >>>> + method = "smc"; >>>> + }; >>>> + >>>> + cpus { >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + >>>> + cpu-map { >>>> + cluster0 { >>>> + core0 { >>>> + cpu = <&cpu0>; >>>> + }; >>>> + core1 { >>>> + cpu = <&cpu1>; >>>> + }; >>>> + core2 { >>>> + cpu = <&cpu2>; >>>> + }; >>>> + core3 { >>>> + cpu = <&cpu3>; >>>> + }; >>>> + }; >>>> + cluster1 { >>>> + core0 { >>>> + cpu = <&cpu4>; >>>> + }; >>>> + core1 { >>>> + cpu = <&cpu5>; >>>> + }; >>>> + core2 { >>>> + cpu = <&cpu6>; >>>> + }; >>>> + core3 { >>>> + cpu = <&cpu7>; >>>> + }; >>>> + }; >>>> + cluster2 { >>>> + core0 { >>>> + cpu = <&cpu8>; >>>> + }; >>>> + core1 { >>>> + cpu = <&cpu9>; >>>> + }; >>>> + core2 { >>>> + cpu = <&cpu10>; >>>> + }; >>>> + core3 { >>>> + cpu = <&cpu11>; >>>> + }; >>>> + }; >>>> + cluster3 { >>>> + core0 { >>>> + cpu = <&cpu12>; >>>> + }; >>>> + core1 { >>>> + cpu = <&cpu13>; >>>> + }; >>>> + core2 { >>>> + cpu = <&cpu14>; >>>> + }; >>>> + core3 { >>>> + cpu = <&cpu15>; >>>> + }; >>>> + }; >>>> + }; >>>> + >>>> + cpu0: cpu at 20000 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>> >>> Change to "arm,cortex-a57","arm,armv8"? >>> >> >> Ok?but I think should be "hisilicon,hip05","arm,armv8". > > If the CPU is a starndard ARM core (such like CA53, CA57, etc), you > need directly use the CPU type which has been defined in: > Documentation/devicetree/bindings/arm/cpus.txt. So here hip05 is the > naming code for SoC? or for the CPU customized by Hisilicon? > > [...] Hip05 is the name for SoC. > > Thanks, > Leo Yan > > . > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-08-31 13:44 ` Ding Tianhong 2015-08-31 14:40 ` Leo Yan @ 2015-09-02 4:28 ` Ding Tianhong 2015-09-02 7:58 ` Marc Zyngier 1 sibling, 1 reply; 16+ messages in thread From: Ding Tianhong @ 2015-09-02 4:28 UTC (permalink / raw) To: linux-arm-kernel Hi?Marc? Can you check this, I am not sure whether the GIC_CPU_MASK_SIMPLE(xx) is used for gic-v3, maybe we should remove it, thanks. Ding On 2015/8/31 21:44, Ding Tianhong wrote: > On 2015/8/31 21:12, Leo Yan wrote: >> On Sat, Aug 29, 2015 at 04:52:41PM +0800, Ding Tianhong wrote: >>> Add initial dtsi file to support Hisilicon Hip05-D02 Board with >>> support of CPUs in four clusters and each cluster has quard Cortex-A57. >>> >>> Also add dts file to support Hip05-D02 development board. >>> >>> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> >>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> >>> --- >>> arch/arm64/boot/dts/hisilicon/Makefile | 2 +- >>> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ >>> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ >>> 3 files changed, 308 insertions(+), 1 deletion(-) >>> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile >>> index fa81a6e..cd158b8 100644 >>> --- a/arch/arm64/boot/dts/hisilicon/Makefile >>> +++ b/arch/arm64/boot/dts/hisilicon/Makefile >>> @@ -1,4 +1,4 @@ >>> -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb >>> +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb >>> >>> always := $(dtb-y) >>> subdir-y := $(dts-dirs) >>> diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>> new file mode 100644 >>> index 0000000..ae34e25 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>> @@ -0,0 +1,36 @@ >>> +/** >>> + * dts file for Hisilicon D02 Development Board >>> + * >>> + * Copyright (C) 2014,2015 Hisilicon Ltd. >>> + * >>> + * This program is free software; you can redistribute it and/or modify >>> + * it under the terms of the GNU General Public License version 2 as >>> + * publishhed by the Free Software Foundation. >>> + * >>> + */ >>> + >>> +/dts-v1/; >>> + >>> +#include "hip05.dtsi" >>> + >>> +/ { >>> + model = "Hisilicon Hip05 D02 Development Board"; >>> + compatible = "hisilicon,hip05-d02"; >>> + >>> + memory at 00000000 { >>> + device_type = "memory"; >>> + reg = <0x0 0x00000000 0x0 0x80000000>; >>> + }; >>> + >>> + aliases { >>> + serial0 = &uart0; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0:115200n8"; >>> + }; >>> +}; >>> + >>> +&uart0 { >>> + status = "ok"; >>> +}; >>> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >>> new file mode 100644 >>> index 0000000..da12d94 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >>> @@ -0,0 +1,271 @@ >>> +/** >>> + * dts file for Hisilicon D02 Development Board >>> + * >>> + * Copyright (C) 2014,2015 Hisilicon Ltd. >>> + * >>> + * This program is free software; you can redistribute it and/or modify >>> + * it under the terms of the GNU General Public License version 2 as >>> + * publishhed by the Free Software Foundation. >>> + * >>> + */ >>> + >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> + >>> +/ { >>> + compatible = "hisilicon,hip05-d02"; >>> + interrupt-parent = <&gic>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + psci { >>> + compatible = "arm,psci-0.2"; >>> + method = "smc"; >>> + }; >>> + >>> + cpus { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + cpu-map { >>> + cluster0 { >>> + core0 { >>> + cpu = <&cpu0>; >>> + }; >>> + core1 { >>> + cpu = <&cpu1>; >>> + }; >>> + core2 { >>> + cpu = <&cpu2>; >>> + }; >>> + core3 { >>> + cpu = <&cpu3>; >>> + }; >>> + }; >>> + cluster1 { >>> + core0 { >>> + cpu = <&cpu4>; >>> + }; >>> + core1 { >>> + cpu = <&cpu5>; >>> + }; >>> + core2 { >>> + cpu = <&cpu6>; >>> + }; >>> + core3 { >>> + cpu = <&cpu7>; >>> + }; >>> + }; >>> + cluster2 { >>> + core0 { >>> + cpu = <&cpu8>; >>> + }; >>> + core1 { >>> + cpu = <&cpu9>; >>> + }; >>> + core2 { >>> + cpu = <&cpu10>; >>> + }; >>> + core3 { >>> + cpu = <&cpu11>; >>> + }; >>> + }; >>> + cluster3 { >>> + core0 { >>> + cpu = <&cpu12>; >>> + }; >>> + core1 { >>> + cpu = <&cpu13>; >>> + }; >>> + core2 { >>> + cpu = <&cpu14>; >>> + }; >>> + core3 { >>> + cpu = <&cpu15>; >>> + }; >>> + }; >>> + }; >>> + >>> + cpu0: cpu at 20000 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >> >> Change to "arm,cortex-a57","arm,armv8"? >> > > Ok?but I think should be "hisilicon,hip05","arm,armv8". > >>> + reg = <0x20000>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu1: cpu at 20001 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20001>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu2: cpu at 20002 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20002>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu3: cpu at 20003 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20003>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu4: cpu at 20100 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20100>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu5: cpu at 20101 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20101>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu6: cpu at 20102 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20102>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu7: cpu at 20103 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20103>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu8: cpu at 20200 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20200>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu9: cpu at 20201 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20201>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu10: cpu at 20202 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20202>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu11: cpu at 20203 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20203>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu12: cpu at 20300 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20300>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu13: cpu at 20301 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20301>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu14: cpu at 20302 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20302>; >>> + enable-method = "psci"; >>> + }; >>> + >>> + cpu15: cpu at 20303 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x20303>; >>> + enable-method = "psci"; >>> + }; >>> + }; >>> + >>> + gic: interrupt-controller at 8d000000 { >>> + compatible = "arm,gic-v3"; >>> + #interrupt-cells = <3>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges; >>> + interrupt-controller; >>> + #redistributor-regions = <1>; >>> + redistributor-stride = <0x0 0x30000>; >>> + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ >>> + <0x0 0x8d100000 0 0x300000>, /* GICR */ >>> + <0x0 0xfe000000 0 0x10000>, /* GICC */ >>> + <0x0 0xfe010000 0 0x10000>, /* GICH */ >>> + <0x0 0xfe020000 0 0x10000>; /* GICV */ >>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; >>> + >>> + its_totems: interrupt-controller at 8c000000 { >>> + compatible = "arm,gic-v3-its"; >>> + msi-controller; >>> + reg = <0x0 0x8c000000 0x0 0x1000000>; >>> + }; >>> + }; >>> + >>> + timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >> >> Here have a question: >> In devcie tree binding file: Documentation/devicetree/bindings/arm/gic.txt, >> it only considers for maximum 8 cpus. So will we need change the >> binding file and also use GIC_CPU_MASK_SIMPLE(16) for 16 cores? >> > > Looks like should updtate gic.txt and use the GIC_CPU_MASK_SIMPLE(16) for 16 cores. > > Ding > >>> + }; >>> + >>> + pmu { >>> + compatible = "arm,armv8-pmuv3"; >>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>> + }; >>> + >>> + soc { >>> + compatible = "simple-bus"; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges; >>> + >>> + refclk200mhz: refclk200mhz { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <200000000>; >>> + }; >>> + >>> + uart0: uart at 80300000 { >>> + compatible = "snps,dw-apb-uart"; >>> + reg = <0x0 0x80300000 0x0 0x10000>; >>> + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; >>> + clocks = <&refclk200mhz>; >>> + clock-names = "apb_pclk"; >>> + reg-shift = <2>; >>> + reg-io-width = <4>; >>> + status = "disabled"; >>> + }; >>> + >>> + uart1: uart at 80310000 { >>> + compatible = "snps,dw-apb-uart"; >>> + reg = <0x0 0x80310000 0x0 0x10000>; >>> + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; >>> + clocks = <&refclk200mhz>; >>> + clock-names = "apb_pclk"; >>> + reg-shift = <2>; >>> + reg-io-width = <4>; >>> + status = "disabled"; >>> + }; >>> + }; >>> +}; >>> -- >>> 1.9.0 >>> >>> >>> >>> _______________________________________________ >>> linux-arm-kernel mailing list >>> linux-arm-kernel at lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> >> . >> > > > _______________________________________________ > linuxarm mailing list > linuxarm at huawei.com > http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-09-02 4:28 ` Ding Tianhong @ 2015-09-02 7:58 ` Marc Zyngier 2015-09-02 8:20 ` Ding Tianhong 0 siblings, 1 reply; 16+ messages in thread From: Marc Zyngier @ 2015-09-02 7:58 UTC (permalink / raw) To: linux-arm-kernel [Don't top-post, this is very annoying] On 02/09/15 05:28, Ding Tianhong wrote: > Hi?Marc? > > Can you check this, I am not sure whether the GIC_CPU_MASK_SIMPLE(xx) > is used for gic-v3, maybe we should remove it, thanks. The binding documentation (Documentation/devicetree/bindings/arm/gic-v3.txt) is very clear: The 3rd cell is the flags, encoded as follows: bits[3:0] trigger type and level flags. 1 = edge triggered 4 = level triggered There is no mask whatsoever, because that would restrict the interrupt to only 32 CPUs at most. So please remove this, this is just wrong. Thanks, M. > Ding > > On 2015/8/31 21:44, Ding Tianhong wrote: >> On 2015/8/31 21:12, Leo Yan wrote: >>> On Sat, Aug 29, 2015 at 04:52:41PM +0800, Ding Tianhong wrote: >>>> Add initial dtsi file to support Hisilicon Hip05-D02 Board with >>>> support of CPUs in four clusters and each cluster has quard Cortex-A57. >>>> >>>> Also add dts file to support Hip05-D02 development board. >>>> >>>> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> >>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> >>>> --- >>>> arch/arm64/boot/dts/hisilicon/Makefile | 2 +- >>>> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ >>>> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ >>>> 3 files changed, 308 insertions(+), 1 deletion(-) >>>> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>> >>>> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile >>>> index fa81a6e..cd158b8 100644 >>>> --- a/arch/arm64/boot/dts/hisilicon/Makefile >>>> +++ b/arch/arm64/boot/dts/hisilicon/Makefile >>>> @@ -1,4 +1,4 @@ >>>> -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb >>>> +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb >>>> >>>> always := $(dtb-y) >>>> subdir-y := $(dts-dirs) >>>> diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>> new file mode 100644 >>>> index 0000000..ae34e25 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>> @@ -0,0 +1,36 @@ >>>> +/** >>>> + * dts file for Hisilicon D02 Development Board >>>> + * >>>> + * Copyright (C) 2014,2015 Hisilicon Ltd. >>>> + * >>>> + * This program is free software; you can redistribute it and/or modify >>>> + * it under the terms of the GNU General Public License version 2 as >>>> + * publishhed by the Free Software Foundation. >>>> + * >>>> + */ >>>> + >>>> +/dts-v1/; >>>> + >>>> +#include "hip05.dtsi" >>>> + >>>> +/ { >>>> + model = "Hisilicon Hip05 D02 Development Board"; >>>> + compatible = "hisilicon,hip05-d02"; >>>> + >>>> + memory at 00000000 { >>>> + device_type = "memory"; >>>> + reg = <0x0 0x00000000 0x0 0x80000000>; >>>> + }; >>>> + >>>> + aliases { >>>> + serial0 = &uart0; >>>> + }; >>>> + >>>> + chosen { >>>> + stdout-path = "serial0:115200n8"; >>>> + }; >>>> +}; >>>> + >>>> +&uart0 { >>>> + status = "ok"; >>>> +}; >>>> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>> new file mode 100644 >>>> index 0000000..da12d94 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>> @@ -0,0 +1,271 @@ >>>> +/** >>>> + * dts file for Hisilicon D02 Development Board >>>> + * >>>> + * Copyright (C) 2014,2015 Hisilicon Ltd. >>>> + * >>>> + * This program is free software; you can redistribute it and/or modify >>>> + * it under the terms of the GNU General Public License version 2 as >>>> + * publishhed by the Free Software Foundation. >>>> + * >>>> + */ >>>> + >>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>> + >>>> +/ { >>>> + compatible = "hisilicon,hip05-d02"; >>>> + interrupt-parent = <&gic>; >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>>> + psci { >>>> + compatible = "arm,psci-0.2"; >>>> + method = "smc"; >>>> + }; >>>> + >>>> + cpus { >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + >>>> + cpu-map { >>>> + cluster0 { >>>> + core0 { >>>> + cpu = <&cpu0>; >>>> + }; >>>> + core1 { >>>> + cpu = <&cpu1>; >>>> + }; >>>> + core2 { >>>> + cpu = <&cpu2>; >>>> + }; >>>> + core3 { >>>> + cpu = <&cpu3>; >>>> + }; >>>> + }; >>>> + cluster1 { >>>> + core0 { >>>> + cpu = <&cpu4>; >>>> + }; >>>> + core1 { >>>> + cpu = <&cpu5>; >>>> + }; >>>> + core2 { >>>> + cpu = <&cpu6>; >>>> + }; >>>> + core3 { >>>> + cpu = <&cpu7>; >>>> + }; >>>> + }; >>>> + cluster2 { >>>> + core0 { >>>> + cpu = <&cpu8>; >>>> + }; >>>> + core1 { >>>> + cpu = <&cpu9>; >>>> + }; >>>> + core2 { >>>> + cpu = <&cpu10>; >>>> + }; >>>> + core3 { >>>> + cpu = <&cpu11>; >>>> + }; >>>> + }; >>>> + cluster3 { >>>> + core0 { >>>> + cpu = <&cpu12>; >>>> + }; >>>> + core1 { >>>> + cpu = <&cpu13>; >>>> + }; >>>> + core2 { >>>> + cpu = <&cpu14>; >>>> + }; >>>> + core3 { >>>> + cpu = <&cpu15>; >>>> + }; >>>> + }; >>>> + }; >>>> + >>>> + cpu0: cpu at 20000 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>> >>> Change to "arm,cortex-a57","arm,armv8"? >>> >> >> Ok?but I think should be "hisilicon,hip05","arm,armv8". >> >>>> + reg = <0x20000>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu1: cpu at 20001 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20001>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu2: cpu at 20002 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20002>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu3: cpu at 20003 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20003>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu4: cpu at 20100 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20100>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu5: cpu at 20101 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20101>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu6: cpu at 20102 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20102>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu7: cpu at 20103 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20103>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu8: cpu at 20200 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20200>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu9: cpu at 20201 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20201>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu10: cpu at 20202 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20202>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu11: cpu at 20203 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20203>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu12: cpu at 20300 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20300>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu13: cpu at 20301 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20301>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu14: cpu at 20302 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20302>; >>>> + enable-method = "psci"; >>>> + }; >>>> + >>>> + cpu15: cpu at 20303 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,armv8"; >>>> + reg = <0x20303>; >>>> + enable-method = "psci"; >>>> + }; >>>> + }; >>>> + >>>> + gic: interrupt-controller at 8d000000 { >>>> + compatible = "arm,gic-v3"; >>>> + #interrupt-cells = <3>; >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + ranges; >>>> + interrupt-controller; >>>> + #redistributor-regions = <1>; >>>> + redistributor-stride = <0x0 0x30000>; >>>> + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ >>>> + <0x0 0x8d100000 0 0x300000>, /* GICR */ >>>> + <0x0 0xfe000000 0 0x10000>, /* GICC */ >>>> + <0x0 0xfe010000 0 0x10000>, /* GICH */ >>>> + <0x0 0xfe020000 0 0x10000>; /* GICV */ >>>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; >>>> + >>>> + its_totems: interrupt-controller at 8c000000 { >>>> + compatible = "arm,gic-v3-its"; >>>> + msi-controller; >>>> + reg = <0x0 0x8c000000 0x0 0x1000000>; >>>> + }; >>>> + }; >>>> + >>>> + timer { >>>> + compatible = "arm,armv8-timer"; >>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >>> >>> Here have a question: >>> In devcie tree binding file: Documentation/devicetree/bindings/arm/gic.txt, >>> it only considers for maximum 8 cpus. So will we need change the >>> binding file and also use GIC_CPU_MASK_SIMPLE(16) for 16 cores? >>> >> >> Looks like should updtate gic.txt and use the GIC_CPU_MASK_SIMPLE(16) for 16 cores. >> >> Ding >> >>>> + }; >>>> + >>>> + pmu { >>>> + compatible = "arm,armv8-pmuv3"; >>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>>> + }; >>>> + >>>> + soc { >>>> + compatible = "simple-bus"; >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + ranges; >>>> + >>>> + refclk200mhz: refclk200mhz { >>>> + compatible = "fixed-clock"; >>>> + #clock-cells = <0>; >>>> + clock-frequency = <200000000>; >>>> + }; >>>> + >>>> + uart0: uart at 80300000 { >>>> + compatible = "snps,dw-apb-uart"; >>>> + reg = <0x0 0x80300000 0x0 0x10000>; >>>> + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; >>>> + clocks = <&refclk200mhz>; >>>> + clock-names = "apb_pclk"; >>>> + reg-shift = <2>; >>>> + reg-io-width = <4>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + uart1: uart at 80310000 { >>>> + compatible = "snps,dw-apb-uart"; >>>> + reg = <0x0 0x80310000 0x0 0x10000>; >>>> + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; >>>> + clocks = <&refclk200mhz>; >>>> + clock-names = "apb_pclk"; >>>> + reg-shift = <2>; >>>> + reg-io-width = <4>; >>>> + status = "disabled"; >>>> + }; >>>> + }; >>>> +}; >>>> -- >>>> 1.9.0 >>>> >>>> >>>> >>>> _______________________________________________ >>>> linux-arm-kernel mailing list >>>> linux-arm-kernel at lists.infradead.org >>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >>> >>> . >>> >> >> >> _______________________________________________ >> linuxarm mailing list >> linuxarm at huawei.com >> http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm >> > > -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-09-02 7:58 ` Marc Zyngier @ 2015-09-02 8:20 ` Ding Tianhong 0 siblings, 0 replies; 16+ messages in thread From: Ding Tianhong @ 2015-09-02 8:20 UTC (permalink / raw) To: linux-arm-kernel On 2015/9/2 15:58, Marc Zyngier wrote: > [Don't top-post, this is very annoying] > > On 02/09/15 05:28, Ding Tianhong wrote: >> Hi?Marc? >> >> Can you check this, I am not sure whether the GIC_CPU_MASK_SIMPLE(xx) >> is used for gic-v3, maybe we should remove it, thanks. > > The binding documentation > (Documentation/devicetree/bindings/arm/gic-v3.txt) is very clear: > > The 3rd cell is the flags, encoded as follows: > bits[3:0] trigger type and level flags. > 1 = edge triggered > 4 = level triggered > > There is no mask whatsoever, because that would restrict the interrupt > to only 32 CPUs at most. > > So please remove this, this is just wrong. > > Thanks, > > M. > Ok, thanks. Ding >> Ding >> >> On 2015/8/31 21:44, Ding Tianhong wrote: >>> On 2015/8/31 21:12, Leo Yan wrote: >>>> On Sat, Aug 29, 2015 at 04:52:41PM +0800, Ding Tianhong wrote: >>>>> Add initial dtsi file to support Hisilicon Hip05-D02 Board with >>>>> support of CPUs in four clusters and each cluster has quard Cortex-A57. >>>>> >>>>> Also add dts file to support Hip05-D02 development board. >>>>> >>>>> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> >>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> >>>>> --- >>>>> arch/arm64/boot/dts/hisilicon/Makefile | 2 +- >>>>> arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ >>>>> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ >>>>> 3 files changed, 308 insertions(+), 1 deletion(-) >>>>> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>>> create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>>> >>>>> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile >>>>> index fa81a6e..cd158b8 100644 >>>>> --- a/arch/arm64/boot/dts/hisilicon/Makefile >>>>> +++ b/arch/arm64/boot/dts/hisilicon/Makefile >>>>> @@ -1,4 +1,4 @@ >>>>> -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb >>>>> +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb >>>>> >>>>> always := $(dtb-y) >>>>> subdir-y := $(dts-dirs) >>>>> diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>>> new file mode 100644 >>>>> index 0000000..ae34e25 >>>>> --- /dev/null >>>>> +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts >>>>> @@ -0,0 +1,36 @@ >>>>> +/** >>>>> + * dts file for Hisilicon D02 Development Board >>>>> + * >>>>> + * Copyright (C) 2014,2015 Hisilicon Ltd. >>>>> + * >>>>> + * This program is free software; you can redistribute it and/or modify >>>>> + * it under the terms of the GNU General Public License version 2 as >>>>> + * publishhed by the Free Software Foundation. >>>>> + * >>>>> + */ >>>>> + >>>>> +/dts-v1/; >>>>> + >>>>> +#include "hip05.dtsi" >>>>> + >>>>> +/ { >>>>> + model = "Hisilicon Hip05 D02 Development Board"; >>>>> + compatible = "hisilicon,hip05-d02"; >>>>> + >>>>> + memory at 00000000 { >>>>> + device_type = "memory"; >>>>> + reg = <0x0 0x00000000 0x0 0x80000000>; >>>>> + }; >>>>> + >>>>> + aliases { >>>>> + serial0 = &uart0; >>>>> + }; >>>>> + >>>>> + chosen { >>>>> + stdout-path = "serial0:115200n8"; >>>>> + }; >>>>> +}; >>>>> + >>>>> +&uart0 { >>>>> + status = "ok"; >>>>> +}; >>>>> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>>> new file mode 100644 >>>>> index 0000000..da12d94 >>>>> --- /dev/null >>>>> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi >>>>> @@ -0,0 +1,271 @@ >>>>> +/** >>>>> + * dts file for Hisilicon D02 Development Board >>>>> + * >>>>> + * Copyright (C) 2014,2015 Hisilicon Ltd. >>>>> + * >>>>> + * This program is free software; you can redistribute it and/or modify >>>>> + * it under the terms of the GNU General Public License version 2 as >>>>> + * publishhed by the Free Software Foundation. >>>>> + * >>>>> + */ >>>>> + >>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>>> + >>>>> +/ { >>>>> + compatible = "hisilicon,hip05-d02"; >>>>> + interrupt-parent = <&gic>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + >>>>> + psci { >>>>> + compatible = "arm,psci-0.2"; >>>>> + method = "smc"; >>>>> + }; >>>>> + >>>>> + cpus { >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + >>>>> + cpu-map { >>>>> + cluster0 { >>>>> + core0 { >>>>> + cpu = <&cpu0>; >>>>> + }; >>>>> + core1 { >>>>> + cpu = <&cpu1>; >>>>> + }; >>>>> + core2 { >>>>> + cpu = <&cpu2>; >>>>> + }; >>>>> + core3 { >>>>> + cpu = <&cpu3>; >>>>> + }; >>>>> + }; >>>>> + cluster1 { >>>>> + core0 { >>>>> + cpu = <&cpu4>; >>>>> + }; >>>>> + core1 { >>>>> + cpu = <&cpu5>; >>>>> + }; >>>>> + core2 { >>>>> + cpu = <&cpu6>; >>>>> + }; >>>>> + core3 { >>>>> + cpu = <&cpu7>; >>>>> + }; >>>>> + }; >>>>> + cluster2 { >>>>> + core0 { >>>>> + cpu = <&cpu8>; >>>>> + }; >>>>> + core1 { >>>>> + cpu = <&cpu9>; >>>>> + }; >>>>> + core2 { >>>>> + cpu = <&cpu10>; >>>>> + }; >>>>> + core3 { >>>>> + cpu = <&cpu11>; >>>>> + }; >>>>> + }; >>>>> + cluster3 { >>>>> + core0 { >>>>> + cpu = <&cpu12>; >>>>> + }; >>>>> + core1 { >>>>> + cpu = <&cpu13>; >>>>> + }; >>>>> + core2 { >>>>> + cpu = <&cpu14>; >>>>> + }; >>>>> + core3 { >>>>> + cpu = <&cpu15>; >>>>> + }; >>>>> + }; >>>>> + }; >>>>> + >>>>> + cpu0: cpu at 20000 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>> >>>> Change to "arm,cortex-a57","arm,armv8"? >>>> >>> >>> Ok?but I think should be "hisilicon,hip05","arm,armv8". >>> >>>>> + reg = <0x20000>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu1: cpu at 20001 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20001>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu2: cpu at 20002 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20002>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu3: cpu at 20003 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20003>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu4: cpu at 20100 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20100>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu5: cpu at 20101 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20101>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu6: cpu at 20102 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20102>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu7: cpu at 20103 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20103>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu8: cpu at 20200 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20200>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu9: cpu at 20201 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20201>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu10: cpu at 20202 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20202>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu11: cpu at 20203 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20203>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu12: cpu at 20300 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20300>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu13: cpu at 20301 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20301>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu14: cpu at 20302 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20302>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + >>>>> + cpu15: cpu at 20303 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x20303>; >>>>> + enable-method = "psci"; >>>>> + }; >>>>> + }; >>>>> + >>>>> + gic: interrupt-controller at 8d000000 { >>>>> + compatible = "arm,gic-v3"; >>>>> + #interrupt-cells = <3>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + ranges; >>>>> + interrupt-controller; >>>>> + #redistributor-regions = <1>; >>>>> + redistributor-stride = <0x0 0x30000>; >>>>> + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ >>>>> + <0x0 0x8d100000 0 0x300000>, /* GICR */ >>>>> + <0x0 0xfe000000 0 0x10000>, /* GICC */ >>>>> + <0x0 0xfe010000 0 0x10000>, /* GICH */ >>>>> + <0x0 0xfe020000 0 0x10000>; /* GICV */ >>>>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; >>>>> + >>>>> + its_totems: interrupt-controller at 8c000000 { >>>>> + compatible = "arm,gic-v3-its"; >>>>> + msi-controller; >>>>> + reg = <0x0 0x8c000000 0x0 0x1000000>; >>>>> + }; >>>>> + }; >>>>> + >>>>> + timer { >>>>> + compatible = "arm,armv8-timer"; >>>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >>>> >>>> Here have a question: >>>> In devcie tree binding file: Documentation/devicetree/bindings/arm/gic.txt, >>>> it only considers for maximum 8 cpus. So will we need change the >>>> binding file and also use GIC_CPU_MASK_SIMPLE(16) for 16 cores? >>>> >>> >>> Looks like should updtate gic.txt and use the GIC_CPU_MASK_SIMPLE(16) for 16 cores. >>> >>> Ding >>> >>>>> + }; >>>>> + >>>>> + pmu { >>>>> + compatible = "arm,armv8-pmuv3"; >>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>>>> + }; >>>>> + >>>>> + soc { >>>>> + compatible = "simple-bus"; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + ranges; >>>>> + >>>>> + refclk200mhz: refclk200mhz { >>>>> + compatible = "fixed-clock"; >>>>> + #clock-cells = <0>; >>>>> + clock-frequency = <200000000>; >>>>> + }; >>>>> + >>>>> + uart0: uart at 80300000 { >>>>> + compatible = "snps,dw-apb-uart"; >>>>> + reg = <0x0 0x80300000 0x0 0x10000>; >>>>> + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clocks = <&refclk200mhz>; >>>>> + clock-names = "apb_pclk"; >>>>> + reg-shift = <2>; >>>>> + reg-io-width = <4>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + uart1: uart at 80310000 { >>>>> + compatible = "snps,dw-apb-uart"; >>>>> + reg = <0x0 0x80310000 0x0 0x10000>; >>>>> + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clocks = <&refclk200mhz>; >>>>> + clock-names = "apb_pclk"; >>>>> + reg-shift = <2>; >>>>> + reg-io-width = <4>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + }; >>>>> +}; >>>>> -- >>>>> 1.9.0 >>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> linux-arm-kernel mailing list >>>>> linux-arm-kernel at lists.infradead.org >>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >>>> >>>> . >>>> >>> >>> >>> _______________________________________________ >>> linuxarm mailing list >>> linuxarm at huawei.com >>> http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm >>> >> >> > > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board
@ 2015-08-29 8:50 Ding Tianhong
2015-08-29 8:50 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong
0 siblings, 1 reply; 16+ messages in thread
From: Ding Tianhong @ 2015-08-29 8:50 UTC (permalink / raw)
To: linux-arm-kernel
Hip05-D02 Development Board is based on Cortex-A57, this patchset
contains initial support for Hip05-D02 Soc and Board. Initial support
is minimal and includes just the arch configuration, device tree
configuration.
PSCI is enabled in device tree and there is no problem to boot all the
16 cores, and the CPU hotplug is also working now, you can download and
compile the latest firmware based on the following link to run this
patch set.
https://github.com/hisilicon/estuary/blob/master/README
Ding Tianhong (2):
arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02
Board
arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board
.../bindings/arm/hisilicon/hisilicon.txt | 4 +
arch/arm64/boot/dts/hisilicon/Makefile | 2 +-
arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 +++
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 +++++++++++++++++++++
4 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi
--
1.9.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-08-29 8:50 [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Ding Tianhong @ 2015-08-29 8:50 ` Ding Tianhong 0 siblings, 0 replies; 16+ messages in thread From: Ding Tianhong @ 2015-08-29 8:50 UTC (permalink / raw) To: linux-arm-kernel Add initial dtsi file to support Hisilicon Hip05-D02 Board with support of CPUs in four clusters and each cluster has quard Cortex-A57. Also add dts file to support Hip05-D02 development board. Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/boot/dts/hisilicon/Makefile | 2 +- arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 36 ++++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 271 ++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/hisilicon/hip05-d02.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hip05.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile index fa81a6e..cd158b8 100644 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ b/arch/arm64/boot/dts/hisilicon/Makefile @@ -1,4 +1,4 @@ -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts new file mode 100644 index 0000000..ae34e25 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -0,0 +1,36 @@ +/** + * dts file for Hisilicon D02 Development Board + * + * Copyright (C) 2014,2015 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include "hip05.dtsi" + +/ { + model = "Hisilicon Hip05 D02 Development Board"; + compatible = "hisilicon,hip05-d02"; + + memory at 00000000 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x80000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi new file mode 100644 index 0000000..da12d94 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -0,0 +1,271 @@ +/** + * dts file for Hisilicon D02 Development Board + * + * Copyright (C) 2014,2015 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "hisilicon,hip05-d02"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + }; + + cpu0: cpu at 20000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20000>; + enable-method = "psci"; + }; + + cpu1: cpu at 20001 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20001>; + enable-method = "psci"; + }; + + cpu2: cpu at 20002 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20002>; + enable-method = "psci"; + }; + + cpu3: cpu at 20003 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20003>; + enable-method = "psci"; + }; + + cpu4: cpu at 20100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20100>; + enable-method = "psci"; + }; + + cpu5: cpu at 20101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20101>; + enable-method = "psci"; + }; + + cpu6: cpu at 20102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20102>; + enable-method = "psci"; + }; + + cpu7: cpu at 20103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20103>; + enable-method = "psci"; + }; + + cpu8: cpu at 20200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20200>; + enable-method = "psci"; + }; + + cpu9: cpu at 20201 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20201>; + enable-method = "psci"; + }; + + cpu10: cpu at 20202 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20202>; + enable-method = "psci"; + }; + + cpu11: cpu at 20203 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20203>; + enable-method = "psci"; + }; + + cpu12: cpu at 20300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20300>; + enable-method = "psci"; + }; + + cpu13: cpu at 20301 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20301>; + enable-method = "psci"; + }; + + cpu14: cpu at 20302 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20302>; + enable-method = "psci"; + }; + + cpu15: cpu at 20303 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x20303>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller at 8d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x30000>; + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ + <0x0 0x8d100000 0 0x300000>, /* GICR */ + <0x0 0xfe000000 0 0x10000>, /* GICC */ + <0x0 0xfe010000 0 0x10000>, /* GICH */ + <0x0 0xfe020000 0 0x10000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + + its_totems: interrupt-controller at 8c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x8c000000 0x0 0x1000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk200mhz: refclk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart0: uart at 80300000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80300000 0x0 0x10000>; + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclk200mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: uart at 80310000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80310000 0x0 0x10000>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclk200mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +}; -- 1.9.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2015-09-06 2:47 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-09-05 2:58 [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Ding Tianhong 2015-09-05 2:58 ` [PATCH 1/2] arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02 Board Ding Tianhong 2015-09-05 2:58 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong 2015-09-05 9:28 ` Marc Zyngier 2015-09-06 2:47 ` Ding Tianhong 2015-09-05 9:18 ` [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Marc Zyngier 2015-09-06 2:40 ` Ding Tianhong -- strict thread matches above, loose matches on Subject: below -- 2015-08-29 8:52 Ding Tianhong 2015-08-29 8:52 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong 2015-08-31 13:12 ` Leo Yan 2015-08-31 13:44 ` Ding Tianhong 2015-08-31 14:40 ` Leo Yan 2015-09-01 1:14 ` Ding Tianhong 2015-09-02 4:28 ` Ding Tianhong 2015-09-02 7:58 ` Marc Zyngier 2015-09-02 8:20 ` Ding Tianhong 2015-08-29 8:50 [PATCH 0/2] arm64: Support Hisilicon Hip05-D02 board Ding Tianhong 2015-08-29 8:50 ` [PATCH 2/2] arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board Ding Tianhong
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