* [PATCH v2 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings
2015-09-01 22:49 [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Adrian Alonso
@ 2015-09-01 22:49 ` Adrian Alonso
2015-09-07 1:01 ` Shawn Guo
2015-09-01 22:49 ` [PATCH v2 3/8] ARM: dts: imx: imx7d add iomuxc lpsr device node Adrian Alonso
` (6 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Adrian Alonso @ 2015-09-01 22:49 UTC (permalink / raw)
To: linux-arm-kernel
- Add imx7 SoC GPIO1 pad iomuxc settings
<mux_reg conf_reg input_reg mux_mode input_val>
- Fix UART input select daisy chain setting values
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
---
Chages for V2: Fix tab+space identation
arch/arm/boot/dts/imx7d-pinfunc.h | 122 +++++++++++++++++++++++++++++++++++++-
1 file changed, 119 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h
index a8d8149..eeda783 100644
--- a/arch/arm/boot/dts/imx7d-pinfunc.h
+++ b/arch/arm/boot/dts/imx7d-pinfunc.h
@@ -15,6 +15,122 @@
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
+#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
+#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
+#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
+#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
+#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
+#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
+#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
+#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
+#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
+#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
+#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
+#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
+#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
+#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
+#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
+#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
+#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
+#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
+#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
+#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
+#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
+#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0
+#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1
+#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0
+#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0
+#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1
+#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0
+#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0
+#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0
+#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0
+#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0
+#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1
+#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0
+#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0
+#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0
+#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0
+#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0
+#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0
+#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0
+#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0
+#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0
#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0
#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0
#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0
@@ -453,7 +569,7 @@
#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0
#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0
#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1
-#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x0000 0x0 0x0
+#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0
#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0
#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0
#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0
@@ -469,7 +585,7 @@
#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0
#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0
#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0
-#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x0000 0x0 0x0
+#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2
#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0
#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0
#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0
@@ -501,7 +617,7 @@
#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0
#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0
#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0
-#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2
#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0
#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0
#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings
2015-09-01 22:49 ` [PATCH v2 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings Adrian Alonso
@ 2015-09-07 1:01 ` Shawn Guo
2015-09-07 2:18 ` Duan Andy
0 siblings, 1 reply; 19+ messages in thread
From: Shawn Guo @ 2015-09-07 1:01 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Sep 01, 2015 at 05:49:07PM -0500, Adrian Alonso wrote:
> - Add imx7 SoC GPIO1 pad iomuxc settings
> <mux_reg conf_reg input_reg mux_mode input_val>
> - Fix UART input select daisy chain setting values
>
> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Fugang has a patch [1] doing the same thing. You guys please coordinate
on this.
Shawn
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/435713/focus=435716
> ---
> Chages for V2: Fix tab+space identation
>
> arch/arm/boot/dts/imx7d-pinfunc.h | 122 +++++++++++++++++++++++++++++++++++++-
> 1 file changed, 119 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h
> index a8d8149..eeda783 100644
> --- a/arch/arm/boot/dts/imx7d-pinfunc.h
> +++ b/arch/arm/boot/dts/imx7d-pinfunc.h
> @@ -15,6 +15,122 @@
> * <mux_reg conf_reg input_reg mux_mode input_val>
> */
>
> +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
> +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
> +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
> +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
> +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
> +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
> +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
> +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
> +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
> +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
> +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
> +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
> +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
> +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
> +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
> +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
> +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
> +#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
> +#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
> +#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
> +#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1
> +#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1
> +#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1
> +#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0
> #define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0
> #define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0
> #define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0
> @@ -453,7 +569,7 @@
> #define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0
> #define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0
> #define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1
> -#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x0000 0x0 0x0
> +#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0
> #define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0
> #define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0
> #define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0
> @@ -469,7 +585,7 @@
> #define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0
> #define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0
> #define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0
> -#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x0000 0x0 0x0
> +#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2
> #define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0
> #define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0
> #define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0
> @@ -501,7 +617,7 @@
> #define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0
> #define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0
> #define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0
> -#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0000 0x0 0x0
> +#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2
> #define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0
> #define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0
> #define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings
2015-09-07 1:01 ` Shawn Guo
@ 2015-09-07 2:18 ` Duan Andy
0 siblings, 0 replies; 19+ messages in thread
From: Duan Andy @ 2015-09-07 2:18 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawnguo@kernel.org> Sent: Monday, September 07, 2015 9:01 AM
> To: Alonso Lazcano Adrian-B38018
> Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org;
> linus.walleij at linaro.org; lznuaa at gmail.com; linux-gpio at vger.kernel.org;
> devicetree at vger.kernel.org; robh+dt at kernel.org; Huang Yongcai-B20788; Li
> Frank-B20596; Gong Yibin-B38343; Garg Nitin-B37173; Duan Fugang-B38611
> Subject: Re: [PATCH v2 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux
> settings
>
> On Tue, Sep 01, 2015 at 05:49:07PM -0500, Adrian Alonso wrote:
> > - Add imx7 SoC GPIO1 pad iomuxc settings
> > <mux_reg conf_reg input_reg mux_mode input_val>
> > - Fix UART input select daisy chain setting values
> >
> > Signed-off-by: Adrian Alonso <aalonso@freescale.com>
>
> Fugang has a patch [1] doing the same thing. You guys please coordinate
> on this.
>
> Shawn
>
Shawn, pls get this patch and drop my patch since the patch also includes two uart pads setting change that is more overall for pinfunc change.
Regards.
> [1]
> http://thread.gmane.org/gmane.linux.ports.arm.kernel/435713/focus=435716
>
> > ---
> > Chages for V2: Fix tab+space identation
> >
> > arch/arm/boot/dts/imx7d-pinfunc.h | 122
> > +++++++++++++++++++++++++++++++++++++-
> > 1 file changed, 119 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h
> > b/arch/arm/boot/dts/imx7d-pinfunc.h
> > index a8d8149..eeda783 100644
> > --- a/arch/arm/boot/dts/imx7d-pinfunc.h
> > +++ b/arch/arm/boot/dts/imx7d-pinfunc.h
> > @@ -15,6 +15,122 @@
> > * <mux_reg conf_reg input_reg mux_mode input_val>
> > */
> >
> > +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0
> 0x0000 0x0030 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT
> 0x0000 0x0030 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY
> 0x0000 0x0030 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B
> 0x0000 0x0030 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB
> 0x0000 0x0030 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1
> 0x0004 0x0034 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT
> 0x0004 0x0034 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3
> 0x0004 0x0034 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK
> 0x0004 0x0034 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT
> 0x0004 0x0034 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT
> 0x0004 0x0034 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2
> 0x0008 0x0038 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT
> 0x0008 0x0038 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1
> 0x0008 0x0038 0x0564 0x2 0x3
> > +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK
> 0x0008 0x0038 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1
> 0x0008 0x0038 0x0000 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT
> 0x0008 0x0038 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID
> 0x0008 0x0038 0x0734 0x7 0x3
> > +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3
> 0x000C 0x003C 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT
> 0x000C 0x003C 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2
> 0x000C 0x003C 0x0570 0x2 0x3
> > +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK
> 0x000C 0x003C 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2
> 0x000C 0x003C 0x0000 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT
> 0x000C 0x003C 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID
> 0x000C 0x003C 0x0730 0x7 0x3
> > +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4
> 0x0010 0x0040 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC
> 0x0010 0x0040 0x072C 0x1 0x1
> > +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4
> 0x0010 0x0040 0x0594 0x2 0x1
> > +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B
> 0x0010 0x0040 0x0710 0x3 0x4
> > +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL
> 0x0010 0x0040 0x05D4 0x4 0x2
> > +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT
> 0x0010 0x0040 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5
> 0x0014 0x0044 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR
> 0x0014 0x0044 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5
> 0x0014 0x0044 0x0598 0x2 0x1
> > +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B
> 0x0014 0x0044 0x0710 0x3 0x5
> > +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA
> 0x0014 0x0044 0x05D8 0x4 0x2
> > +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT
> 0x0014 0x0044 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6
> 0x0018 0x0048 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC
> 0x0018 0x0048 0x0728 0x1 0x1
> > +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6
> 0x0018 0x0048 0x059C 0x2 0x1
> > +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA
> 0x0018 0x0048 0x0714 0x3 0x4
> > +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL
> 0x0018 0x0048 0x05DC 0x4 0x2
> > +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT
> 0x0018 0x0048 0x0000 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4
> 0x0018 0x0048 0x0624 0x6 0x1
> > +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7
> 0x001C 0x004C 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR
> 0x001C 0x004C 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7
> 0x001C 0x004C 0x05A0 0x2 0x1
> > +#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA
> 0x001C 0x004C 0x0714 0x3 0x5
> > +#define MX7D_PAD_GPIO1_IO07__I2C2_SDA
> 0x001C 0x004C 0x05E0 0x4 0x2
> > +#define MX7D_PAD_GPIO1_IO07__CCM_STOP
> 0x001C 0x004C 0x0000 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO07__KPP_COL4
> 0x001C 0x004C 0x0604 0x6 0x1
> > +#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8
> 0x0014 0x026C 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT
> 0x0014 0x026C 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B
> 0x0014 0x026C 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX
> 0x0014 0x026C 0x0704 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX
> 0x0014 0x026C 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO08__I2C3_SCL
> 0x0014 0x026C 0x05E4 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO08__KPP_COL5
> 0x0014 0x026C 0x0608 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO08__PWM1_OUT
> 0x0014 0x026C 0x0000 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9
> 0x0018 0x0270 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO09__SD1_LCTL
> 0x0018 0x0270 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3
> 0x0018 0x0270 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX
> 0x0018 0x0270 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX
> 0x0018 0x0270 0x0704 0x3 0x1
> > +#define MX7D_PAD_GPIO1_IO09__I2C3_SDA
> 0x0018 0x0270 0x05E8 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY
> 0x0018 0x0270 0x04F4 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO09__KPP_ROW5
> 0x0018 0x0270 0x0628 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO09__PWM2_OUT
> 0x0018 0x0270 0x0000 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10
> 0x001C 0x0274 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO10__SD2_LCTL
> 0x001C 0x0274 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO
> 0x001C 0x0274 0x0568 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS
> 0x001C 0x0274 0x0700 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS
> 0x001C 0x0274 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO10__I2C4_SCL
> 0x001C 0x0274 0x05EC 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA
> 0x001C 0x0274 0x05A4 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO10__KPP_COL6
> 0x001C 0x0274 0x060C 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO10__PWM3_OUT
> 0x001C 0x0274 0x0000 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11
> 0x0020 0x0278 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO11__SD3_LCTL
> 0x0020 0x0278 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO11__ENET1_MDC
> 0x0020 0x0278 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS
> 0x0020 0x0278 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS
> 0x0020 0x0278 0x0700 0x3 0x1
> > +#define MX7D_PAD_GPIO1_IO11__I2C4_SDA
> 0x0020 0x0278 0x05F0 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB
> 0x0020 0x0278 0x05A8 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO11__KPP_ROW6
> 0x0020 0x0278 0x062C 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO11__PWM4_OUT
> 0x0020 0x0278 0x0000 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12
> 0x0024 0x027C 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT
> 0x0024 0x027C 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1
> 0x0024 0x027C 0x0564 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX
> 0x0024 0x027C 0x04DC 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO12__CM4_NMI
> 0x0024 0x027C 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1
> 0x0024 0x027C 0x04E4 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5
> 0x0024 0x027C 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID
> 0x0024 0x027C 0x0734 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13
> 0x0028 0x0280 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT
> 0x0028 0x0280 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2
> 0x0028 0x0280 0x0570 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX
> 0x0028 0x0280 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY
> 0x0028 0x0280 0x04F4 0x4 0x1
> > +#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2
> 0x0028 0x0280 0x04E8 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL
> 0x0028 0x0280 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID
> 0x0028 0x0280 0x0730 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14
> 0x002C 0x0284 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO14__SD3_CD_B
> 0x002C 0x0284 0x0738 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO
> 0x002C 0x0284 0x0574 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX
> 0x002C 0x0284 0x04E0 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B
> 0x002C 0x0284 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3
> 0x002C 0x0284 0x04EC 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0
> 0x002C 0x0284 0x06D8 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15
> 0x0030 0x0288 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO15__SD3_WP
> 0x0030 0x0288 0x073C 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO15__ENET2_MDC
> 0x0030 0x0288 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX
> 0x0030 0x0288 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B
> 0x0030 0x0288 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4
> 0x0030 0x0288 0x04F0 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1
> 0x0030 0x0288 0x06DC 0x6 0x0
> > #define MX7D_PAD_EPDC_DATA00__EPDC_DATA0
> 0x0034 0x02A4 0x0000 0x0 0x0
> > #define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD
> 0x0034 0x02A4 0x0000 0x1 0x0
> > #define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0
> 0x0034 0x02A4 0x0000 0x2 0x0
> > @@ -453,7 +569,7 @@
> > #define MX7D_PAD_LCD_DATA23__EIM_ADDR26
> 0x0124 0x0394 0x0000 0x4 0x0
> > #define MX7D_PAD_LCD_DATA23__GPIO3_IO28
> 0x0124 0x0394 0x0000 0x5 0x0
> > #define MX7D_PAD_LCD_DATA23__I2C4_SDA
> 0x0124 0x0394 0x05F0 0x6 0x1
> > -#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX
> 0x0128 0x0398 0x0000 0x0 0x0
> > +#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX
> 0x0128 0x0398 0x06F4 0x0 0x0
> > #define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX
> 0x0128 0x0398 0x0000 0x0 0x0
> > #define MX7D_PAD_UART1_RX_DATA__I2C1_SCL
> 0x0128 0x0398 0x05D4 0x1 0x0
> > #define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY
> 0x0128 0x0398 0x0000 0x2 0x0
> > @@ -469,7 +585,7 @@
> > #define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT
> 0x012C 0x039C 0x0000 0x4 0x0
> > #define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1
> 0x012C 0x039C 0x0000 0x5 0x0
> > #define MX7D_PAD_UART1_TX_DATA__ENET1_MDC
> 0x012C 0x039C 0x0000 0x6 0x0
> > -#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX
> 0x0130 0x03A0 0x0000 0x0 0x0
> > +#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX
> 0x0130 0x03A0 0x06FC 0x0 0x2
> > #define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX
> 0x0130 0x03A0 0x0000 0x0 0x0
> > #define MX7D_PAD_UART2_RX_DATA__I2C2_SCL
> 0x0130 0x03A0 0x05DC 0x1 0x0
> > #define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK
> 0x0130 0x03A0 0x0000 0x2 0x0
> > @@ -501,7 +617,7 @@
> > #define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT
> 0x013C 0x03AC 0x0000 0x4 0x0
> > #define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5
> 0x013C 0x03AC 0x0000 0x5 0x0
> > #define MX7D_PAD_UART3_TX_DATA__SD2_LCTL
> 0x013C 0x03AC 0x0000 0x6 0x0
> > -#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS
> 0x0140 0x03B0 0x0000 0x0 0x0
> > +#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS
> 0x0140 0x03B0 0x0700 0x0 0x2
> > #define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS
> 0x0140 0x03B0 0x0000 0x0 0x0
> > #define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC
> 0x0140 0x03B0 0x0728 0x1 0x0
> > #define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0
> 0x0140 0x03B0 0x0000 0x2 0x0
> > --
> > 2.1.4
> >
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 3/8] ARM: dts: imx: imx7d add iomuxc lpsr device node
2015-09-01 22:49 [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Adrian Alonso
2015-09-01 22:49 ` [PATCH v2 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings Adrian Alonso
@ 2015-09-01 22:49 ` Adrian Alonso
2015-09-01 22:49 ` [PATCH v2 4/8] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads Adrian Alonso
` (5 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Adrian Alonso @ 2015-09-01 22:49 UTC (permalink / raw)
To: linux-arm-kernel
Add device tree node to support iomuxc-lpsr controller
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
---
Changes for V2: Resend
arch/arm/boot/dts/imx7d.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index b738ce0..00f70db 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -446,6 +446,11 @@
status = "disabled";
};
+ iomuxc_lpsr: iomuxc-lpsr at 302c0000 {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c0000 0x10000>;
+ };
+
gpt1: gpt at 302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d0000 0x10000>;
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 4/8] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
2015-09-01 22:49 [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Adrian Alonso
2015-09-01 22:49 ` [PATCH v2 2/8] ARM: imx: imx7d-pinfunc: add gpio1 pad iomux settings Adrian Alonso
2015-09-01 22:49 ` [PATCH v2 3/8] ARM: dts: imx: imx7d add iomuxc lpsr device node Adrian Alonso
@ 2015-09-01 22:49 ` Adrian Alonso
2015-09-01 22:49 ` [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag Adrian Alonso
` (4 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Adrian Alonso @ 2015-09-01 22:49 UTC (permalink / raw)
To: linux-arm-kernel
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
---
Changes for V2: Resend
arch/arm/boot/dts/imx7d-sdb.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index fdd1d7c..63af4ea 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -406,3 +406,18 @@
};
};
+
+&iomuxc_lpsr {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_2>;
+
+ imx7d-sdb {
+ pinctrl_hog_2: hoggrp-2 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x59
+ MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ >;
+ };
+ };
+};
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
2015-09-01 22:49 [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Adrian Alonso
` (2 preceding siblings ...)
2015-09-01 22:49 ` [PATCH v2 4/8] ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads Adrian Alonso
@ 2015-09-01 22:49 ` Adrian Alonso
2015-09-07 1:28 ` Shawn Guo
2015-09-01 22:49 ` [PATCH v2 6/8] pinctrl: freescale: imx: add shared input select reg support Adrian Alonso
` (3 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Adrian Alonso @ 2015-09-01 22:49 UTC (permalink / raw)
To: linux-arm-kernel
- Add ZERO_OFFSET_VALID flag, on imx7d mux_conf reg
offset is zero for iomuxc-lspr controller
- Do default initialization on parse group function.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
---
Changes for V2: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 23 +++++++++++++----------
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 95db9e8..9f019be 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
unsigned long config;
- if (!pin_reg || pin_reg->conf_reg == -1) {
+ if (pin_reg->conf_reg == -1) {
seq_printf(s, "N/A");
return;
}
@@ -536,21 +536,29 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
+ u32 mux_reg;
u32 conf_reg;
unsigned int pin_id;
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = &grp->pins[i];
+ mux_reg = be32_to_cpu(*list++);
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
+ if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
conf_reg = -1;
}
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ if (info->flags & ZERO_OFFSET_VALID)
+ pin_id = mux_reg / 4;
+ else
+ pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+
pin_reg = &info->pin_regs[pin_id];
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
@@ -684,7 +692,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
{
struct imx_pinctrl *ipctl;
struct resource *res;
- int ret, i;
+ int ret;
if (!info || !info->pins || !info->npins) {
dev_err(&pdev->dev, "wrong pinctrl info\n");
@@ -702,11 +710,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!info->pin_regs)
return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- info->pin_regs[i].mux_reg = -1;
- info->pin_regs[i].conf_reg = -1;
- }
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ipctl->base))
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 26f8f1c..67c07c2 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
};
#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
2015-09-01 22:49 ` [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag Adrian Alonso
@ 2015-09-07 1:28 ` Shawn Guo
2015-09-08 16:05 ` Alonso Adrian
0 siblings, 1 reply; 19+ messages in thread
From: Shawn Guo @ 2015-09-07 1:28 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Sep 01, 2015 at 05:49:10PM -0500, Adrian Alonso wrote:
> - Add ZERO_OFFSET_VALID flag, on imx7d mux_conf reg
> offset is zero for iomuxc-lspr controller
> - Do default initialization on parse group function.
>
> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
I do not follow why this patch is needed at all. All the register
validity check are done against -1, and zero offset is already supported
by the driver in the current form. Or am I missing anything?
Shawn
> ---
> Changes for V2: Resend
>
> drivers/pinctrl/freescale/pinctrl-imx.c | 23 +++++++++++++----------
> drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
> index 95db9e8..9f019be 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.c
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.c
> @@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
> unsigned long config;
>
> - if (!pin_reg || pin_reg->conf_reg == -1) {
> + if (pin_reg->conf_reg == -1) {
> seq_printf(s, "N/A");
> return;
> }
> @@ -536,21 +536,29 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
> return -ENOMEM;
>
> for (i = 0; i < grp->npins; i++) {
> - u32 mux_reg = be32_to_cpu(*list++);
> + u32 mux_reg;
> u32 conf_reg;
> unsigned int pin_id;
> struct imx_pin_reg *pin_reg;
> struct imx_pin *pin = &grp->pins[i];
>
> + mux_reg = be32_to_cpu(*list++);
> + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
> + mux_reg = -1;
> +
> if (info->flags & SHARE_MUX_CONF_REG) {
> conf_reg = mux_reg;
> } else {
> conf_reg = be32_to_cpu(*list++);
> - if (!conf_reg)
> + if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
> conf_reg = -1;
> }
>
> - pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
> + if (info->flags & ZERO_OFFSET_VALID)
> + pin_id = mux_reg / 4;
> + else
> + pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
> +
> pin_reg = &info->pin_regs[pin_id];
> pin->pin = pin_id;
> grp->pin_ids[i] = pin_id;
> @@ -684,7 +692,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> {
> struct imx_pinctrl *ipctl;
> struct resource *res;
> - int ret, i;
> + int ret;
>
> if (!info || !info->pins || !info->npins) {
> dev_err(&pdev->dev, "wrong pinctrl info\n");
> @@ -702,11 +710,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> if (!info->pin_regs)
> return -ENOMEM;
>
> - for (i = 0; i < info->npins; i++) {
> - info->pin_regs[i].mux_reg = -1;
> - info->pin_regs[i].conf_reg = -1;
> - }
> -
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> ipctl->base = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(ipctl->base))
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
> index 26f8f1c..67c07c2 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.h
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.h
> @@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
> };
>
> #define SHARE_MUX_CONF_REG 0x1
> +#define ZERO_OFFSET_VALID 0x2
>
> #define NO_MUX 0x0
> #define NO_PAD 0x0
> --
> 2.1.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
2015-09-07 1:28 ` Shawn Guo
@ 2015-09-08 16:05 ` Alonso Adrian
2015-09-18 13:52 ` Shawn Guo
0 siblings, 1 reply; 19+ messages in thread
From: Alonso Adrian @ 2015-09-08 16:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi Shawn,
See comments below
Regards
________________________________________
From: Shawn Guo <shawnguo@kernel.org>
Sent: Sunday, September 6, 2015 8:28 PM
To: Alonso Lazcano Adrian-B38018
Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org; linus.walleij at linaro.org; lznuaa at gmail.com; devicetree at vger.kernel.org; Li Frank-B20596; Garg Nitin-B37173; Huang Yongcai-B20788; linux-gpio at vger.kernel.org; robh+dt at kernel.org; Gong Yibin-B38343
Subject: Re: [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
On Tue, Sep 01, 2015 at 05:49:10PM -0500, Adrian Alonso wrote:
> - Add ZERO_OFFSET_VALID flag, on imx7d mux_conf reg
> offset is zero for iomuxc-lspr controller
> - Do default initialization on parse group function.
>
> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
I do not follow why this patch is needed at all. All the register
validity check are done against -1, and zero offset is already supported
by the driver in the current form. Or am I missing anything?
Shawn
> ---
> Changes for V2: Resend
>
> drivers/pinctrl/freescale/pinctrl-imx.c | 23 +++++++++++++----------
> drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
> index 95db9e8..9f019be 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.c
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.c
> @@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
> unsigned long config;
>
> - if (!pin_reg || pin_reg->conf_reg == -1) {
> + if (pin_reg->conf_reg == -1) {
> seq_printf(s, "N/A");
> return;
> }
> @@ -536,21 +536,29 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
> return -ENOMEM;
>
> for (i = 0; i < grp->npins; i++) {
> - u32 mux_reg = be32_to_cpu(*list++);
> + u32 mux_reg;
> u32 conf_reg;
> unsigned int pin_id;
> struct imx_pin_reg *pin_reg;
> struct imx_pin *pin = &grp->pins[i];
>
> + mux_reg = be32_to_cpu(*list++);
> + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
> + mux_reg = -1;
> +
> if (info->flags & SHARE_MUX_CONF_REG) {
> conf_reg = mux_reg;
> } else {
> conf_reg = be32_to_cpu(*list++);
> - if (!conf_reg)
> + if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
> conf_reg = -1;
> }
>
[Adrian] The below assignment is the important thing that this patch does,
it allows the pad_id to be zero and match the pad id's according to the mux_reg offset.
> - pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
> + if (info->flags & ZERO_OFFSET_VALID)
> + pin_id = mux_reg / 4;
> + else
> + pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
> +
> pin_reg = &info->pin_regs[pin_id];
> pin->pin = pin_id;
> grp->pin_ids[i] = pin_id;
> @@ -684,7 +692,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> {
> struct imx_pinctrl *ipctl;
> struct resource *res;
> - int ret, i;
> + int ret;
>
> if (!info || !info->pins || !info->npins) {
> dev_err(&pdev->dev, "wrong pinctrl info\n");
> @@ -702,11 +710,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> if (!info->pin_regs)
> return -ENOMEM;
>
> - for (i = 0; i < info->npins; i++) {
> - info->pin_regs[i].mux_reg = -1;
> - info->pin_regs[i].conf_reg = -1;
> - }
> -
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> ipctl->base = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(ipctl->base))
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
> index 26f8f1c..67c07c2 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.h
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.h
> @@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
> };
>
> #define SHARE_MUX_CONF_REG 0x1
> +#define ZERO_OFFSET_VALID 0x2
>
> #define NO_MUX 0x0
> #define NO_PAD 0x0
> --
> 2.1.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
2015-09-08 16:05 ` Alonso Adrian
@ 2015-09-18 13:52 ` Shawn Guo
2015-09-18 16:27 ` Alonso Adrian
0 siblings, 1 reply; 19+ messages in thread
From: Shawn Guo @ 2015-09-18 13:52 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Sep 08, 2015 at 04:05:32PM +0000, Alonso Adrian wrote:
> Hi Shawn,
>
> See comments below
Please use bottom posting, not top posting.
...
> > @@ -536,21 +536,29 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
> > return -ENOMEM;
> >
> > for (i = 0; i < grp->npins; i++) {
> > - u32 mux_reg = be32_to_cpu(*list++);
> > + u32 mux_reg;
> > u32 conf_reg;
> > unsigned int pin_id;
> > struct imx_pin_reg *pin_reg;
> > struct imx_pin *pin = &grp->pins[i];
> >
> > + mux_reg = be32_to_cpu(*list++);
> > + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
> > + mux_reg = -1;
> > +
> > if (info->flags & SHARE_MUX_CONF_REG) {
> > conf_reg = mux_reg;
> > } else {
> > conf_reg = be32_to_cpu(*list++);
> > - if (!conf_reg)
> > + if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
> > conf_reg = -1;
> > }
> >
> [Adrian] The below assignment is the important thing that this patch does,
> it allows the pad_id to be zero and match the pad id's according to the mux_reg offset.
> > - pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
> > + if (info->flags & ZERO_OFFSET_VALID)
> > + pin_id = mux_reg / 4;
> > + else
> > + pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
> > +
Ah, yes. So the only code change we need is just the line below, right?
pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
Shawn
> > pin_reg = &info->pin_regs[pin_id];
> > pin->pin = pin_id;
> > grp->pin_ids[i] = pin_id;
> > @@ -684,7 +692,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> > {
> > struct imx_pinctrl *ipctl;
> > struct resource *res;
> > - int ret, i;
> > + int ret;
> >
> > if (!info || !info->pins || !info->npins) {
> > dev_err(&pdev->dev, "wrong pinctrl info\n");
> > @@ -702,11 +710,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> > if (!info->pin_regs)
> > return -ENOMEM;
> >
> > - for (i = 0; i < info->npins; i++) {
> > - info->pin_regs[i].mux_reg = -1;
> > - info->pin_regs[i].conf_reg = -1;
> > - }
> > -
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > ipctl->base = devm_ioremap_resource(&pdev->dev, res);
> > if (IS_ERR(ipctl->base))
> > diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
> > index 26f8f1c..67c07c2 100644
> > --- a/drivers/pinctrl/freescale/pinctrl-imx.h
> > +++ b/drivers/pinctrl/freescale/pinctrl-imx.h
> > @@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info {
> > };
> >
> > #define SHARE_MUX_CONF_REG 0x1
> > +#define ZERO_OFFSET_VALID 0x2
> >
> > #define NO_MUX 0x0
> > #define NO_PAD 0x0
> > --
> > 2.1.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
2015-09-18 13:52 ` Shawn Guo
@ 2015-09-18 16:27 ` Alonso Adrian
0 siblings, 0 replies; 19+ messages in thread
From: Alonso Adrian @ 2015-09-18 16:27 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo at kernel.org]
> Sent: Friday, September 18, 2015 8:53 AM
> To: Alonso Lazcano Adrian-B38018 <aalonso@freescale.com>
> Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org;
> linus.walleij at linaro.org; lznuaa at gmail.com; devicetree at vger.kernel.org; Li
> Frank-B20596 <Frank.Li@freescale.com>; Garg Nitin-B37173
> <nitin.garg@freescale.com>; Huang Yongcai-B20788
> <Anson.Huang@freescale.com>; linux-gpio at vger.kernel.org;
> robh+dt at kernel.org; Gong Yibin-B38343 <yibin.gong@freescale.com>
> Subject: Re: [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID
> flag
>
> On Tue, Sep 08, 2015 at 04:05:32PM +0000, Alonso Adrian wrote:
> > Hi Shawn,
> >
> > See comments below
>
> Please use bottom posting, not top posting.
>
> ...
>
> > > @@ -536,21 +536,29 @@ static int imx_pinctrl_parse_groups(struct
> device_node *np,
> > > return -ENOMEM;
> > >
> > > for (i = 0; i < grp->npins; i++) {
> > > - u32 mux_reg = be32_to_cpu(*list++);
> > > + u32 mux_reg;
> > > u32 conf_reg;
> > > unsigned int pin_id;
> > > struct imx_pin_reg *pin_reg;
> > > struct imx_pin *pin = &grp->pins[i];
> > >
> > > + mux_reg = be32_to_cpu(*list++);
> > > + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
> > > + mux_reg = -1;
> > > +
> > > if (info->flags & SHARE_MUX_CONF_REG) {
> > > conf_reg = mux_reg;
> > > } else {
> > > conf_reg = be32_to_cpu(*list++);
> > > - if (!conf_reg)
> > > + if (!(info->flags & ZERO_OFFSET_VALID) &&
> > > + !conf_reg)
> > > conf_reg = -1;
> > > }
> > >
> > [Adrian] The below assignment is the important thing that this patch
> > does, it allows the pad_id to be zero and match the pad id's according to the
> mux_reg offset.
> > > - pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
> > > + if (info->flags & ZERO_OFFSET_VALID)
> > > + pin_id = mux_reg / 4;
> > > + else
> > > + pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
> > > +
>
> Ah, yes. So the only code change we need is just the line below, right?
>
> pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
>
> Shawn
[Adrian] Yes that will work, let me resend a new patch series with this change, Thanks.
>
> > > pin_reg = &info->pin_regs[pin_id];
> > > pin->pin = pin_id;
> > > grp->pin_ids[i] = pin_id; @@ -684,7 +692,7 @@ int
> > > imx_pinctrl_probe(struct platform_device *pdev, {
> > > struct imx_pinctrl *ipctl;
> > > struct resource *res;
> > > - int ret, i;
> > > + int ret;
> > >
> > > if (!info || !info->pins || !info->npins) {
> > > dev_err(&pdev->dev, "wrong pinctrl info\n"); @@
> > > -702,11 +710,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> > > if (!info->pin_regs)
> > > return -ENOMEM;
> > >
> > > - for (i = 0; i < info->npins; i++) {
> > > - info->pin_regs[i].mux_reg = -1;
> > > - info->pin_regs[i].conf_reg = -1;
> > > - }
> > > -
> > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > ipctl->base = devm_ioremap_resource(&pdev->dev, res);
> > > if (IS_ERR(ipctl->base))
> > > diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h
> > > b/drivers/pinctrl/freescale/pinctrl-imx.h
> > > index 26f8f1c..67c07c2 100644
> > > --- a/drivers/pinctrl/freescale/pinctrl-imx.h
> > > +++ b/drivers/pinctrl/freescale/pinctrl-imx.h
> > > @@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info { };
> > >
> > > #define SHARE_MUX_CONF_REG 0x1
> > > +#define ZERO_OFFSET_VALID 0x2
> > >
> > > #define NO_MUX 0x0
> > > #define NO_PAD 0x0
> > > --
> > > 2.1.4
> > >
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > linux-arm-kernel at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 6/8] pinctrl: freescale: imx: add shared input select reg support
2015-09-01 22:49 [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Adrian Alonso
` (3 preceding siblings ...)
2015-09-01 22:49 ` [PATCH v2 5/8] pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag Adrian Alonso
@ 2015-09-01 22:49 ` Adrian Alonso
2015-09-07 2:12 ` Shawn Guo
2015-09-01 22:49 ` [PATCH v2 7/8] pinctrl: freescale: imx7d: support iomux lpsr controller Adrian Alonso
` (2 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Adrian Alonso @ 2015-09-01 22:49 UTC (permalink / raw)
To: linux-arm-kernel
- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
which share select_input register for daisy chain settings
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
---
Changes for V2: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++++++++++++++++++++++++++-
drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 9f019be..597319d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
@@ -39,6 +40,7 @@ struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
+ void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
};
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
- writel(pin->input_val, ipctl->base + pin->input_reg);
+ if (info->flags & SHARE_INPUT_SELECT_REG)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
@@ -690,6 +697,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
int ret;
@@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
+ if (info->flags & SHARE_INPUT_SELECT_REG) {
+ np = of_get_child_by_name(dev_np->parent, "iomuxc");
+ if (np) {
+ ipctl->input_sel_base = of_iomap(np, 0);
+ if (IS_ERR(ipctl->input_sel_base)) {
+ of_node_put(np);
+ dev_err(&pdev->dev,
+ "iomuxc base address not found\n");
+ return PTR_ERR(ipctl->input_sel_base);
+ }
+ } else {
+ dev_err(&pdev->dev, "iomuxc device node not foud\n");
+ return -EINVAL;
+ }
+ of_node_put(np);
+ }
+
imx_pinctrl_desc.name = dev_name(&pdev->dev);
imx_pinctrl_desc.pins = info->pins;
imx_pinctrl_desc.npins = info->npins;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 67c07c2..d11a827 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -86,6 +86,7 @@ struct imx_pinctrl_soc_info {
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
+#define SHARE_INPUT_SELECT_REG 0x4
#define NO_MUX 0x0
#define NO_PAD 0x0
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 6/8] pinctrl: freescale: imx: add shared input select reg support
2015-09-01 22:49 ` [PATCH v2 6/8] pinctrl: freescale: imx: add shared input select reg support Adrian Alonso
@ 2015-09-07 2:12 ` Shawn Guo
2015-09-08 16:13 ` Alonso Adrian
0 siblings, 1 reply; 19+ messages in thread
From: Shawn Guo @ 2015-09-07 2:12 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Sep 01, 2015 at 05:49:11PM -0500, Adrian Alonso wrote:
> - Add shared input select register support
> - imx7d has two iomux controllers iomuxc and iomuxc-lpsr
> which share select_input register for daisy chain settings
>
> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
> ---
> Changes for V2: Resend
>
> drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++++++++++++++++++++++++++-
> drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
> 2 files changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
> index 9f019be..597319d 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.c
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.c
> @@ -18,6 +18,7 @@
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/pinctrl/machine.h>
> #include <linux/pinctrl/pinconf.h>
> #include <linux/pinctrl/pinctrl.h>
> @@ -39,6 +40,7 @@ struct imx_pinctrl {
> struct device *dev;
> struct pinctrl_dev *pctl;
> void __iomem *base;
> + void __iomem *input_sel_base;
> const struct imx_pinctrl_soc_info *info;
> };
>
> @@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
> * Regular select input register can never be at offset
> * 0, and we only print register value for regular case.
> */
> - writel(pin->input_val, ipctl->base + pin->input_reg);
> + if (info->flags & SHARE_INPUT_SELECT_REG)
This can be replaced by a NULL checking on input_sel_base.
> + writel(pin->input_val, ipctl->input_sel_base +
> + pin->input_reg);
> + else
> + writel(pin->input_val, ipctl->base +
> + pin->input_reg);
> dev_dbg(ipctl->dev,
> "==>select_input: offset 0x%x val 0x%x\n",
> pin->input_reg, pin->input_val);
> @@ -690,6 +697,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
> int imx_pinctrl_probe(struct platform_device *pdev,
> struct imx_pinctrl_soc_info *info)
> {
> + struct device_node *dev_np = pdev->dev.of_node;
> + struct device_node *np;
> struct imx_pinctrl *ipctl;
> struct resource *res;
> int ret;
> @@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> if (IS_ERR(ipctl->base))
> return PTR_ERR(ipctl->base);
>
> + if (info->flags & SHARE_INPUT_SELECT_REG) {
> + np = of_get_child_by_name(dev_np->parent, "iomuxc");
This doesn't scale well. First of all, we do not generally recommend
searching node by name, because most of time node name is not enforced
to be stable, and some nodes are named quite arbitrarily. Secondly, we
do not know if the hardware people will move select_input registers to
somewhere else than IOMUXC in the future.
Hence, I suggest you have a device tree phandle pointing the device
where select_input registers are located. In that case, flag
SHARE_INPUT_SELECT_REG can even be saved completely.
> + if (np) {
> + ipctl->input_sel_base = of_iomap(np, 0);
> + if (IS_ERR(ipctl->input_sel_base)) {
> + of_node_put(np);
> + dev_err(&pdev->dev,
> + "iomuxc base address not found\n");
> + return PTR_ERR(ipctl->input_sel_base);
> + }
> + } else {
> + dev_err(&pdev->dev, "iomuxc device node not foud\n");
s/foud/found
Shawn
> + return -EINVAL;
> + }
> + of_node_put(np);
> + }
> +
> imx_pinctrl_desc.name = dev_name(&pdev->dev);
> imx_pinctrl_desc.pins = info->pins;
> imx_pinctrl_desc.npins = info->npins;
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
> index 67c07c2..d11a827 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.h
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.h
> @@ -86,6 +86,7 @@ struct imx_pinctrl_soc_info {
>
> #define SHARE_MUX_CONF_REG 0x1
> #define ZERO_OFFSET_VALID 0x2
> +#define SHARE_INPUT_SELECT_REG 0x4
>
> #define NO_MUX 0x0
> #define NO_PAD 0x0
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v2 6/8] pinctrl: freescale: imx: add shared input select reg support
2015-09-07 2:12 ` Shawn Guo
@ 2015-09-08 16:13 ` Alonso Adrian
0 siblings, 0 replies; 19+ messages in thread
From: Alonso Adrian @ 2015-09-08 16:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi Shawn,
See comments below.
Regards
Adrian
________________________________________
From: Shawn Guo <shawnguo@kernel.org>
Sent: Sunday, September 6, 2015 9:12 PM
To: Alonso Lazcano Adrian-B38018
Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org; linus.walleij at linaro.org; lznuaa at gmail.com; linux-gpio at vger.kernel.org; devicetree at vger.kernel.org; robh+dt at kernel.org; Huang Yongcai-B20788; Li Frank-B20596; Gong Yibin-B38343; Garg Nitin-B37173
Subject: Re: [PATCH v2 6/8] pinctrl: freescale: imx: add shared input select reg support
On Tue, Sep 01, 2015 at 05:49:11PM -0500, Adrian Alonso wrote:
> - Add shared input select register support
> - imx7d has two iomux controllers iomuxc and iomuxc-lpsr
> which share select_input register for daisy chain settings
>
> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
> ---
> Changes for V2: Resend
>
> drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++++++++++++++++++++++++++-
> drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
> 2 files changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
> index 9f019be..597319d 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.c
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.c
> @@ -18,6 +18,7 @@
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/pinctrl/machine.h>
> #include <linux/pinctrl/pinconf.h>
> #include <linux/pinctrl/pinctrl.h>
> @@ -39,6 +40,7 @@ struct imx_pinctrl {
> struct device *dev;
> struct pinctrl_dev *pctl;
> void __iomem *base;
> + void __iomem *input_sel_base;
> const struct imx_pinctrl_soc_info *info;
> };
>
> @@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
> * Regular select input register can never be at offset
> * 0, and we only print register value for regular case.
> */
> - writel(pin->input_val, ipctl->base + pin->input_reg);
> + if (info->flags & SHARE_INPUT_SELECT_REG)
This can be replaced by a NULL checking on input_sel_base.
[Adrian] Yes, but I will prefer to keep this flag check instead to keep code consisten on how to handle
special cases, that way is easier to spot when input select register is shared.
> + writel(pin->input_val, ipctl->input_sel_base +
> + pin->input_reg);
> + else
> + writel(pin->input_val, ipctl->base +
> + pin->input_reg);
> dev_dbg(ipctl->dev,
> "==>select_input: offset 0x%x val 0x%x\n",
> pin->input_reg, pin->input_val);
> @@ -690,6 +697,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
> int imx_pinctrl_probe(struct platform_device *pdev,
> struct imx_pinctrl_soc_info *info)
> {
> + struct device_node *dev_np = pdev->dev.of_node;
> + struct device_node *np;
> struct imx_pinctrl *ipctl;
> struct resource *res;
> int ret;
> @@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
> if (IS_ERR(ipctl->base))
> return PTR_ERR(ipctl->base);
>
> + if (info->flags & SHARE_INPUT_SELECT_REG) {
> + np = of_get_child_by_name(dev_np->parent, "iomuxc");
This doesn't scale well. First of all, we do not generally recommend
searching node by name, because most of time node name is not enforced
to be stable, and some nodes are named quite arbitrarily. Secondly, we
do not know if the hardware people will move select_input registers to
somewhere else than IOMUXC in the future.
Hence, I suggest you have a device tree phandle pointing the device
where select_input registers are located. In that case, flag
SHARE_INPUT_SELECT_REG can even be saved completely.
[Adrian] Agree, let me rework this :)
> + if (np) {
> + ipctl->input_sel_base = of_iomap(np, 0);
> + if (IS_ERR(ipctl->input_sel_base)) {
> + of_node_put(np);
> + dev_err(&pdev->dev,
> + "iomuxc base address not found\n");
> + return PTR_ERR(ipctl->input_sel_base);
> + }
> + } else {
> + dev_err(&pdev->dev, "iomuxc device node not foud\n");
s/foud/found
Shawn
> + return -EINVAL;
> + }
> + of_node_put(np);
> + }
> +
> imx_pinctrl_desc.name = dev_name(&pdev->dev);
> imx_pinctrl_desc.pins = info->pins;
> imx_pinctrl_desc.npins = info->npins;
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
> index 67c07c2..d11a827 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.h
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.h
> @@ -86,6 +86,7 @@ struct imx_pinctrl_soc_info {
>
> #define SHARE_MUX_CONF_REG 0x1
> #define ZERO_OFFSET_VALID 0x2
> +#define SHARE_INPUT_SELECT_REG 0x4
>
> #define NO_MUX 0x0
> #define NO_PAD 0x0
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 7/8] pinctrl: freescale: imx7d: support iomux lpsr controller
2015-09-01 22:49 [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Adrian Alonso
` (4 preceding siblings ...)
2015-09-01 22:49 ` [PATCH v2 6/8] pinctrl: freescale: imx: add shared input select reg support Adrian Alonso
@ 2015-09-01 22:49 ` Adrian Alonso
2015-09-01 22:49 ` [PATCH v2 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings Adrian Alonso
2015-09-07 0:56 ` [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Shawn Guo
7 siblings, 0 replies; 19+ messages in thread
From: Adrian Alonso @ 2015-09-01 22:49 UTC (permalink / raw)
To: linux-arm-kernel
iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr
- Add iomuxc-lpsr gpio group id's
- Use flag ZERO_OFFSET_VALID and SHARE_INPUT_SELECT_REG to
properly set pads from iomuxc-lpsr domain
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
---
Changes for V2: Add imx7d_lpsr_pads enums
drivers/pinctrl/freescale/pinctrl-imx7d.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530..b4d77e4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
MX7D_PAD_ENET1_COL = 154,
};
+enum imx7d_lpsr_pads {
+ MX7D_PAD_GPIO1_IO00 = 0,
+ MX7D_PAD_GPIO1_IO01 = 1,
+ MX7D_PAD_GPIO1_IO02 = 2,
+ MX7D_PAD_GPIO1_IO03 = 3,
+ MX7D_PAD_GPIO1_IO04 = 4,
+ MX7D_PAD_GPIO1_IO05 = 5,
+ MX7D_PAD_GPIO1_IO06 = 6,
+ MX7D_PAD_GPIO1_IO07 = 7,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
+};
+
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
+static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
+ .pins = imx7d_lpsr_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
+ .flags = SHARE_INPUT_SELECT_REG | ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
+ { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info },
{ /* sentinel */ }
};
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
2015-09-01 22:49 [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Adrian Alonso
` (5 preceding siblings ...)
2015-09-01 22:49 ` [PATCH v2 7/8] pinctrl: freescale: imx7d: support iomux lpsr controller Adrian Alonso
@ 2015-09-01 22:49 ` Adrian Alonso
2015-09-07 2:42 ` Shawn Guo
2015-09-07 0:56 ` [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Shawn Guo
7 siblings, 1 reply; 19+ messages in thread
From: Adrian Alonso @ 2015-09-01 22:49 UTC (permalink / raw)
To: linux-arm-kernel
Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..c7310fc 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,10 +1,19 @@
* Freescale i.MX7 Dual IOMUX Controller
+iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
+as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
+power state rentetion capabilities on gpios that are part of iomuxc-lpsr
+(GPIO1_IO7..GPIO1_IO0).
+
+Pheriparials using pads from iomuxc-lpsr support low state retention power
+state, under LPSR mode GPIO's state of pads are retain.
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx7d-iomuxc"
+- compatible: "fsl-imx7d-iomuxc-lpsr"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
@@ -25,3 +34,37 @@ PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
+
+Examples:
+While iomuxc-lpsr is intended to be used by dedicated peripherals to take
+advantages of LPSR power mode, is also possible that an IP to use pads from
+any of the iomux controllers. For example the I2C1 IP can use SCL pad from
+iomuxc-lpsr controller and SDA pad from iomuxc controller as:
+
+i2c1: i2c@30a20000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
+ status = "okay";
+};
+
+iomuxc-lpsr at 302c0000 {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c0000 0x10000>;
+
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
+ >;
+ };
+};
+
+iomuxc at 30330000 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x30330000 0x10000>;
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
+ >;
+ };
+};
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
2015-09-01 22:49 ` [PATCH v2 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings Adrian Alonso
@ 2015-09-07 2:42 ` Shawn Guo
2015-09-08 16:15 ` Alonso Adrian
0 siblings, 1 reply; 19+ messages in thread
From: Shawn Guo @ 2015-09-07 2:42 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Sep 01, 2015 at 05:49:13PM -0500, Adrian Alonso wrote:
> Add iomuxc-lpsr devicetree bindings documentation
> Provide documentation context as well an example on
> pheriperals that could use pad from either iomuxc controller
> supported by iMX7D SoC
>
> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
> ---
> Changes for V2: New patch on imx7d iomuxc-lpsr patch series
>
> .../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
> index 8bbf25d..c7310fc 100644
> --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
> @@ -1,10 +1,19 @@
> * Freescale i.MX7 Dual IOMUX Controller
>
> +iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
> +as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
> +power state rentetion capabilities on gpios that are part of iomuxc-lpsr
> +(GPIO1_IO7..GPIO1_IO0).
I think the speciality of the select_input registers should be
mentioned too.
> +
> +Pheriparials using pads from iomuxc-lpsr support low state retention power
> +state, under LPSR mode GPIO's state of pads are retain.
> +
> Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
> and usage.
>
> Required properties:
> - compatible: "fsl,imx7d-iomuxc"
> +- compatible: "fsl-imx7d-iomuxc-lpsr"
s/fsl-imx7d-iomuxc-lpsr/fsl,imx7d-iomuxc-lpsr
Shawn
> - fsl,pins: each entry consists of 6 integers and represents the mux and config
> setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
> input_val> are specified using a PIN_FUNC_ID macro, which can be found in
> @@ -25,3 +34,37 @@ PAD_CTL_DSE_X1 (0 << 0)
> PAD_CTL_DSE_X2 (1 << 0)
> PAD_CTL_DSE_X3 (2 << 0)
> PAD_CTL_DSE_X4 (3 << 0)
> +
> +Examples:
> +While iomuxc-lpsr is intended to be used by dedicated peripherals to take
> +advantages of LPSR power mode, is also possible that an IP to use pads from
> +any of the iomux controllers. For example the I2C1 IP can use SCL pad from
> +iomuxc-lpsr controller and SDA pad from iomuxc controller as:
> +
> +i2c1: i2c at 30a20000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
> + status = "okay";
> +};
> +
> +iomuxc-lpsr at 302c0000 {
> + compatible = "fsl,imx7d-iomuxc-lpsr";
> + reg = <0x302c0000 0x10000>;
> +
> + pinctrl_i2c1_1: i2c1grp-1 {
> + fsl,pins = <
> + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
> + >;
> + };
> +};
> +
> +iomuxc at 30330000 {
> + compatible = "fsl,imx7d-iomuxc";
> + reg = <0x30330000 0x10000>;
> +
> + pinctrl_i2c1_2: i2c1grp-2 {
> + fsl,pins = <
> + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
> + >;
> + };
> +};
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v2 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
2015-09-07 2:42 ` Shawn Guo
@ 2015-09-08 16:15 ` Alonso Adrian
0 siblings, 0 replies; 19+ messages in thread
From: Alonso Adrian @ 2015-09-08 16:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi Shawn,
See comments below.
Regards
Adrian
________________________________________
From: Shawn Guo <shawnguo@kernel.org>
Sent: Sunday, September 6, 2015 9:42 PM
To: Alonso Lazcano Adrian-B38018
Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org; linus.walleij at linaro.org; lznuaa at gmail.com; linux-gpio at vger.kernel.org; devicetree at vger.kernel.org; robh+dt at kernel.org; Huang Yongcai-B20788; Li Frank-B20596; Gong Yibin-B38343; Garg Nitin-B37173
Subject: Re: [PATCH v2 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
On Tue, Sep 01, 2015 at 05:49:13PM -0500, Adrian Alonso wrote:
> Add iomuxc-lpsr devicetree bindings documentation
> Provide documentation context as well an example on
> pheriperals that could use pad from either iomuxc controller
> supported by iMX7D SoC
>
> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
> ---
> Changes for V2: New patch on imx7d iomuxc-lpsr patch series
>
> .../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
> index 8bbf25d..c7310fc 100644
> --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
> @@ -1,10 +1,19 @@
> * Freescale i.MX7 Dual IOMUX Controller
>
> +iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
> +as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
> +power state rentetion capabilities on gpios that are part of iomuxc-lpsr
> +(GPIO1_IO7..GPIO1_IO0).
I think the speciality of the select_input registers should be
mentioned too.
[Adrian] Agree will add notes for shared select input.
> +
> +Pheriparials using pads from iomuxc-lpsr support low state retention power
> +state, under LPSR mode GPIO's state of pads are retain.
> +
> Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
> and usage.
>
> Required properties:
> - compatible: "fsl,imx7d-iomuxc"
> +- compatible: "fsl-imx7d-iomuxc-lpsr"
s/fsl-imx7d-iomuxc-lpsr/fsl,imx7d-iomuxc-lpsr
[Adrian] Will fix this, thanks.
Shawn
> - fsl,pins: each entry consists of 6 integers and represents the mux and config
> setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
> input_val> are specified using a PIN_FUNC_ID macro, which can be found in
> @@ -25,3 +34,37 @@ PAD_CTL_DSE_X1 (0 << 0)
> PAD_CTL_DSE_X2 (1 << 0)
> PAD_CTL_DSE_X3 (2 << 0)
> PAD_CTL_DSE_X4 (3 << 0)
> +
> +Examples:
> +While iomuxc-lpsr is intended to be used by dedicated peripherals to take
> +advantages of LPSR power mode, is also possible that an IP to use pads from
> +any of the iomux controllers. For example the I2C1 IP can use SCL pad from
> +iomuxc-lpsr controller and SDA pad from iomuxc controller as:
> +
> +i2c1: i2c at 30a20000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
> + status = "okay";
> +};
> +
> +iomuxc-lpsr at 302c0000 {
> + compatible = "fsl,imx7d-iomuxc-lpsr";
> + reg = <0x302c0000 0x10000>;
> +
> + pinctrl_i2c1_1: i2c1grp-1 {
> + fsl,pins = <
> + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
> + >;
> + };
> +};
> +
> +iomuxc at 30330000 {
> + compatible = "fsl,imx7d-iomuxc";
> + reg = <0x30330000 0x10000>;
> +
> + pinctrl_i2c1_2: i2c1grp-2 {
> + fsl,pins = <
> + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
> + >;
> + };
> +};
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances
2015-09-01 22:49 [PATCH v2 1/8] pinctrl: freescale: imx: fix system crash if enable two pinctl instances Adrian Alonso
` (6 preceding siblings ...)
2015-09-01 22:49 ` [PATCH v2 8/8] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings Adrian Alonso
@ 2015-09-07 0:56 ` Shawn Guo
7 siblings, 0 replies; 19+ messages in thread
From: Shawn Guo @ 2015-09-07 0:56 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Sep 01, 2015 at 05:49:06PM -0500, Adrian Alonso wrote:
> From: Robin Gong <b38343@freescale.com>
>
> Fix system chrash caused by groups whose number is smaller than the number
> of groups of the last pinctl instance which is not initialized.
>
> iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing
> the second instance (iomuxc) the chrash below occurs.
>
> Uncompressing Linux... done, booting the kernel.
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.2.0-next-20150901-00006-gebfa43c (aalonso at bluefly)
> [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7)
> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin instruction cache
> [ 0.000000] Machine model: Freescale i.MX7 SabreSD Board
> [ 0.661012] [<802a6cb0>] (strcmp) from [<802cc80c>] (imx_dt_node_to_map+0x58/0x208)
> [ 0.668879] [<802cc80c>] (imx_dt_node_to_map) from [<802cbe24>] (pinctrl_dt_to_map+0x174/0x2b0)
> [ 0.677654] [<802cbe24>] (pinctrl_dt_to_map) from [<802c8f18>] (pinctrl_get+0x100/0x424)
> [ 0.685878] [<802c8f18>] (pinctrl_get) from [<802c9510>] (pinctrl_register+0x26c/0x480)
> [ 0.694104] [<802c9510>] (pinctrl_register) from [<802ccf3c>] (imx_pinctrl_probe+0x580/0x6e8)
> [ 0.702706] [<802ccf3c>] (imx_pinctrl_probe) from [<80351b58>] (platform_drv_probe+0x44/0xa4)
> [ 0.711455] [<80351b58>] (platform_drv_probe) from [<803503ec>] (driver_probe_device+0x174/0x2b4)
> [ 0.720405] [<803503ec>] (driver_probe_device) from [<803505fc>] (__driver_attach+0x8c/0x90)
> [ 0.728982] [<803505fc>] (__driver_attach) from [<8034e930>] (bus_for_each_dev+0x6c/0xa0)
> [ 0.737381] [<8034e930>] (bus_for_each_dev) from [<8034fb88>] (bus_add_driver+0x148/0x1f0)
> [ 0.745804] [<8034fb88>] (bus_add_driver) from [<80350c00>] (driver_register+0x78/0xf8)
> [ 0.753880] [<80350c00>] (driver_register) from [<800097d0>] (do_one_initcall+0x8c/0x1d4)
> [ 0.762282] [<800097d0>] (do_one_initcall) from [<80987dac>] (kernel_init_freeable+0x144/0x1e4)
> [ 0.771061] [<80987dac>] (kernel_init_freeable) from [<806d9c7c>] (kernel_init+0x8/0xe8)
> [ 0.779285] [<806d9c7c>] (kernel_init) from [<8000f628>] (ret_from_fork+0x14/0x2c)
> [ 0.786981] Code: e3520000 e5e32001 1afffffb e12fff1e (e4d03001)
>
> Signed-off-by: Robin Gong <b38343@freescale.com>
> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Please always remember to copy kernel at pengutronix.de on i.MX related
patches.
> ---
> Chages for V2:
> - Reorder patch series
> - Add platform boot up information on kernel error
> - Move gpr_index to imx_pinctrl_soc_info
>
> drivers/pinctrl/freescale/pinctrl-imx.c | 3 +--
> drivers/pinctrl/freescale/pinctrl-imx.h | 1 +
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
> index d7b98ba..95db9e8 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.c
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.c
> @@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
> struct device_node *child;
> struct imx_pmx_func *func;
> struct imx_pin_group *grp;
> - static u32 grp_index;
> u32 i = 0;
>
> dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
> @@ -599,7 +598,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
>
> for_each_child_of_node(np, child) {
> func->groups[i] = child->name;
> - grp = &info->groups[grp_index++];
> + grp = &info->groups[info->grp_index++];
> imx_pinctrl_parse_groups(child, grp, info, i++);
> }
>
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
> index 49e55d3..26f8f1c 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.h
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.h
> @@ -81,6 +81,7 @@ struct imx_pinctrl_soc_info {
> struct imx_pmx_func *functions;
> unsigned int nfunctions;
> unsigned int flags;
> + u32 grp_index;
I would suggest you move this around to group it with 'groups'
variables, something like below.
struct imx_pin_group *groups;
unsigned int ngroups;
unsigned int group_index;
Shawn
> };
>
> #define SHARE_MUX_CONF_REG 0x1
> --
> 2.1.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread