* [GIT PULL 00/31] perf/core improvements and fixes
@ 2018-03-13 12:04 Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 11/31] perf vendor events: Drop incomplete multiple mapfile support Arnaldo Carvalho de Melo
` (11 more replies)
0 siblings, 12 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
Hi Ingo,
Please consider pulling,
- Arnaldo
Test results at the end of this message, as usual.
The following changes since commit 33801b94741d6c3be9713c10aa627477216c21e2:
perf/core: Fix installing cgroup events on CPU (2018-03-12 15:28:51 +0100)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.17-20180313
for you to fetch changes up to 1b442ed71f0b32d07db03efba150d4592875f988:
perf test: Fix exit code for record+probe_libc_inet_pton.sh (2018-03-12 15:25:20 -0300)
----------------------------------------------------------------
perf/core improvements and fixes:
- Add support for pmu events vendor subdirectories, move vendor event
files (JSON format) to "arm" and "cavium" subdirectories (John Garry)
- Enable ThunderX2 B0 events in the "cavium" vendor event files (Ganapatrao Kulkarni)
- Show zero counters as well in 'perf report --stat' (Ingo Molnar)
- Record physical addresses in samples in 'perf c2c record', so that
the NUMA node can be displayed for cacheline addresses (Jiri Olsa)
- Fix kernel MMAP name setup when --vmlinux is used (Jiri Olsa)
- Display llvm eBPF compiling command in debug output (Jiri Olsa)
- Add libdw DWARF post unwind support for ARM64 (Jean Pihet, Kim Phillips)
- Unwind with libdw doesn't take symfs into account (Martin Vuille)
- Fix exit code for record+probe_libc_inet_pton.sh 'perf test' entry (Sandipan Das)
- Fix code dump when using transaction events with 'perf stat -T' (Thomas Richter)
- Do not call perf_dafault_config() twice in 'perf record' (Yisheng Xie)
- Fix top.call-graph config variable processing in 'perf top' (Yisheng Xie)
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
----------------------------------------------------------------
Ganapatrao Kulkarni (1):
perf vendor events arm64: Enable JSON events for ThunderX2 B0
Ingo Molnar (1):
perf report: Show zero counters as well in 'perf report --stat'
Jiri Olsa (11):
perf env: Free memory nodes data
perf tools: Add mem2node object
perf tests: Add mem2node object test
perf c2c record: Record physical addresses in samples
perf c2c report: Make calc_width work with struct c2c_hist_entry
perf c2c report: Call calc_width() only for displayed entries
perf c2c report: Display node for cacheline address
perf c2c report: Add span header over cacheline data
perf c2c report: Add cacheline address count column
perf llvm: Display eBPF compiling command in debug output
perf machine: Fix mmap name setup
John Garry (11):
perf vendor events: Drop incomplete multiple mapfile support
perf vendor events: Fix error code in json_events()
perf vendor events: Drop support for unused topic directories
perf vendor events: Add support for pmu events vendor subdirectory
perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory
perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory
perf vendor events: Add support for arch standard events
perf vendor events arm64: Add armv8-recommended.json
perf vendor events arm64: Fixup ThunderX2 to use recommended events
perf vendor events arm64: fixup A53 to use recommended events
perf vendor events arm64: add HiSilicon hip08 JSON file
Kim Phillips (1):
perf tools arm64: Add libdw DWARF post unwind support for ARM64
Martin Vuille (1):
perf unwind: Unwind with libdw doesn't take symfs into account
Sandipan Das (1):
perf test: Fix exit code for record+probe_libc_inet_pton.sh
Thomas Richter (2):
perf stat: Fix core dump when flag T is used
perf stat: Make function perf_stat_evsel_id_init static
Yisheng Xie (2):
perf record: Avoid duplicate call of perf_default_config()
perf top: Fix top.call-graph config option reading
tools/perf/Documentation/perf-c2c.txt | 2 +-
tools/perf/Makefile.config | 2 +-
tools/perf/arch/arm64/include/arch-tests.h | 12 +
tools/perf/arch/arm64/tests/Build | 2 +
tools/perf/arch/arm64/tests/arch-tests.c | 16 +
tools/perf/arch/arm64/util/Build | 1 +
tools/perf/arch/arm64/util/unwind-libdw.c | 60 +++
tools/perf/builtin-c2c.c | 223 +++++++++-
tools/perf/builtin-record.c | 8 +-
tools/perf/builtin-stat.c | 9 +-
tools/perf/builtin-top.c | 6 +-
tools/perf/pmu-events/Build | 2 +
tools/perf/pmu-events/README | 15 +-
.../arch/arm64/{ => arm}/cortex-a53/branch.json | 14 +-
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 8 +
.../arch/arm64/arm/cortex-a53/cache.json | 27 ++
.../arch/arm64/{ => arm}/cortex-a53/memory.json | 14 +-
.../arch/arm64/arm/cortex-a53/other.json | 28 ++
.../arch/arm64/{ => arm}/cortex-a53/pipeline.json | 20 +-
.../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++
.../arch/arm64/cavium/thunderx2-imp-def.json | 62 ---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 32 ++
.../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 -
.../pmu-events/arch/arm64/cortex-a53/cache.json | 27 --
.../pmu-events/arch/arm64/cortex-a53/other.json | 32 --
.../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 ++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 6 +-
tools/perf/pmu-events/jevents.c | 288 ++++++++++---
tools/perf/tests/Build | 1 +
tools/perf/tests/builtin-test.c | 4 +
tools/perf/tests/mem2node.c | 75 ++++
.../tests/shell/record+probe_libc_inet_pton.sh | 5 +-
tools/perf/tests/tests.h | 1 +
tools/perf/ui/stdio/hist.c | 6 +-
tools/perf/util/Build | 1 +
tools/perf/util/env.c | 4 +
tools/perf/util/llvm-utils.c | 14 +
tools/perf/util/machine.c | 28 +-
tools/perf/util/mem2node.c | 134 ++++++
tools/perf/util/mem2node.h | 19 +
tools/perf/util/stat.c | 2 +-
tools/perf/util/stat.h | 2 -
tools/perf/util/unwind-libdw.c | 2 +-
43 files changed, 1533 insertions(+), 277 deletions(-)
create mode 100644 tools/perf/arch/arm64/include/arch-tests.h
create mode 100644 tools/perf/arch/arm64/tests/arch-tests.c
create mode 100644 tools/perf/arch/arm64/util/unwind-libdw.c
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json (76%)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json (50%)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json (97%)
create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
create mode 100644 tools/perf/tests/mem2node.c
create mode 100644 tools/perf/util/mem2node.c
create mode 100644 tools/perf/util/mem2node.h
Test results:
The first ones are container (docker) based builds of tools/perf with and
without libelf support. Where clang is available, it is also used to build
perf with/without libelf.
The objtool and samples/bpf/ builds are disabled now that I'm switching from
using the sources in a local volume to fetching them from a http server to
build it inside the container, to make it easier to build in a container cluster.
Those will come back later.
Several are cross builds, the ones with -x-ARCH and the android one, and those
may not have all the features built, due to lack of multi-arch devel packages,
available and being used so far on just a few, like
debian:experimental-x-{arm64,mipsel}.
The 'perf test' one will perform a variety of tests exercising
tools/perf/util/, tools/lib/{bpf,traceevent,etc}, as well as run perf commands
with a variety of command line event specifications to then intercept the
sys_perf_event syscall to check that the perf_event_attr fields are set up as
expected, among a variety of other unit tests.
Then there is the 'make -C tools/perf build-test' ones, that build tools/perf/
with a variety of feature sets, exercising the build with an incomplete set of
features as well as with a complete one. It is planned to have it run on each
of the containers mentioned above, using some container orchestration
infrastructure. Get in contact if interested in helping having this in place.
# dm
1 alpine:3.4 : Ok gcc (Alpine 5.3.0) 5.3.0
2 alpine:3.5 : Ok gcc (Alpine 6.2.1) 6.2.1 20160822
3 alpine:3.6 : Ok gcc (Alpine 6.3.0) 6.3.0
4 alpine:3.7 : Ok gcc (Alpine 6.4.0) 6.4.0
5 alpine:edge : Ok gcc (Alpine 6.4.0) 6.4.0
6 amazonlinux:1 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-11)
7 amazonlinux:2 : Ok gcc (GCC) 7.2.1 20170915 (Red Hat 7.2.1-2)
8 android-ndk:r12b-arm : Ok arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease)
9 android-ndk:r15c-arm : Ok arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease)
10 centos:5 : Ok gcc (GCC) 4.1.2 20080704 (Red Hat 4.1.2-55)
11 centos:6 : Ok gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18)
12 centos:7 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16)
13 debian:7 : Ok gcc (Debian 4.7.2-5) 4.7.2
14 debian:8 : Ok gcc (Debian 4.9.2-10+deb8u1) 4.9.2
15 debian:9 : Ok gcc (Debian 6.3.0-18) 6.3.0 20170516
16 debian:experimental : Ok gcc (Debian 7.2.0-17) 7.2.1 20171205
17 debian:experimental-x-arm64 : Ok aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
18 debian:experimental-x-mips : Ok mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
19 debian:experimental-x-mips64 : Ok mips64-linux-gnuabi64-gcc (Debian 7.2.0-11) 7.2.0
20 debian:experimental-x-mipsel : Ok mipsel-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
21 fedora:20 : Ok gcc (GCC) 4.8.3 20140911 (Red Hat 4.8.3-7)
22 fedora:21 : Ok gcc (GCC) 4.9.2 20150212 (Red Hat 4.9.2-6)
23 fedora:22 : Ok gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6)
24 fedora:23 : Ok gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6)
25 fedora:24 : Ok gcc (GCC) 6.3.1 20161221 (Red Hat 6.3.1-1)
26 fedora:24-x-ARC-uClibc : Ok arc-linux-gcc (ARCompact ISA Linux uClibc toolchain 2017.09-rc2) 7.1.1 20170710
27 fedora:25 : Ok gcc (GCC) 6.4.1 20170727 (Red Hat 6.4.1-1)
28 fedora:26 : Ok gcc (GCC) 7.2.1 20170915 (Red Hat 7.2.1-2)
29 fedora:27 : Ok gcc (GCC) 7.3.1 20180303 (Red Hat 7.3.1-5)
30 fedora:rawhide : Ok gcc (GCC) 7.2.1 20170829 (Red Hat 7.2.1-1)
31 gentoo-stage3-amd64:latest : Ok gcc (Gentoo 6.4.0-r1 p1.3) 6.4.0
32 mageia:5 : Ok gcc (GCC) 4.9.2
33 mageia:6 : Ok gcc (Mageia 5.4.0-5.mga6) 5.4.0
34 opensuse:42.1 : Ok gcc (SUSE Linux) 4.8.5
35 opensuse:42.2 : Ok gcc (SUSE Linux) 4.8.5
36 opensuse:42.3 : Ok gcc (SUSE Linux) 4.8.5
37 opensuse:tumbleweed : Ok gcc (SUSE Linux) 7.3.0
38 oraclelinux:6 : Ok gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18)
39 oraclelinux:7 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16)
40 ubuntu:12.04.5 : Ok gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3
41 ubuntu:14.04.4 : Ok gcc (Ubuntu 4.8.4-2ubuntu1~14.04.3) 4.8.4
42 ubuntu:14.04.4-x-linaro-arm64 : Ok aarch64-linux-gnu-gcc (Linaro GCC 5.4-2017.05) 5.4.1 20170404
43 ubuntu:15.04 : Ok gcc (Ubuntu 4.9.2-10ubuntu13) 4.9.2
44 ubuntu:16.04 : Ok gcc (Ubuntu 5.4.0-6ubuntu1~16.04.5) 5.4.0 20160609
45 ubuntu:16.04-x-arm : Ok arm-linux-gnueabihf-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
46 ubuntu:16.04-x-arm64 : Ok aarch64-linux-gnu-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
47 ubuntu:16.04-x-powerpc : Ok powerpc-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
48 ubuntu:16.04-x-powerpc64 : Ok powerpc64-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.1) 5.4.0 20160609
49 ubuntu:16.04-x-powerpc64el : Ok powerpc64le-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
50 ubuntu:16.04-x-s390 : Ok s390x-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
51 ubuntu:16.10 : Ok gcc (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005
52 ubuntu:17.04 : Ok gcc (Ubuntu 6.3.0-12ubuntu2) 6.3.0 20170406
53 ubuntu:17.10 : Ok gcc (Ubuntu 7.2.0-8ubuntu3) 7.2.0
54 ubuntu:18.04 : Ok gcc (Ubuntu 7.2.0-16ubuntu1) 7.2.0
# uname -a
Linux jouet 4.16.0-rc4 #1 SMP Mon Mar 5 12:18:05 -03 2018 x86_64 x86_64 x86_64 GNU/Linux
# perf test
1: vmlinux symtab matches kallsyms : Ok
2: Detect openat syscall event : Ok
3: Detect openat syscall event on all cpus : Ok
4: Read samples using the mmap interface : Ok
5: Test data source output : Ok
6: Parse event definition strings : Ok
7: Simple expression parser : Ok
8: PERF_RECORD_* events & perf_sample fields : Ok
9: Parse perf pmu format : Ok
10: DSO data read : Ok
11: DSO data cache : Ok
12: DSO data reopen : Ok
13: Roundtrip evsel->name : Ok
14: Parse sched tracepoints fields : Ok
15: syscalls:sys_enter_openat event fields : Ok
16: Setup struct perf_event_attr : Ok
17: Match and link multiple hists : Ok
18: 'import perf' in python : Ok
19: Breakpoint overflow signal handler : Ok
20: Breakpoint overflow sampling : Ok
21: Number of exit events of a simple workload : Ok
22: Software clock events period values : Ok
23: Object code reading : Ok
24: Sample parsing : Ok
25: Use a dummy software event to keep tracking : Ok
26: Parse with no sample_id_all bit set : Ok
27: Filter hist entries : Ok
28: Lookup mmap thread : Ok
29: Share thread mg : Ok
30: Sort output of hist entries : Ok
31: Cumulate child hist entries : Ok
32: Track with sched_switch : Ok
33: Filter fds with revents mask in a fdarray : Ok
34: Add fd to a fdarray, making it autogrow : Ok
35: kmod_path__parse : Ok
36: Thread map : Ok
37: LLVM search and compile :
37.1: Basic BPF llvm compile : Ok
37.2: kbuild searching : Ok
37.3: Compile source for BPF prologue generation : Ok
37.4: Compile source for BPF relocation : Ok
38: Session topology : Ok
39: BPF filter :
39.1: Basic BPF filtering : Ok
39.2: BPF pinning : Ok
39.3: BPF prologue generation : Ok
39.4: BPF relocation checker : Ok
40: Synthesize thread map : Ok
41: Remove thread map : Ok
42: Synthesize cpu map : Ok
43: Synthesize stat config : Ok
44: Synthesize stat : Ok
45: Synthesize stat round : Ok
46: Synthesize attr update : Ok
47: Event times : Ok
48: Read backward ring buffer : Ok
49: Print cpu map : Ok
50: Probe SDT events : Ok
51: is_printable_array : Ok
52: Print bitmap : Ok
53: perf hooks : Ok
54: builtin clang support : Skip (not compiled in)
55: unit_number__scnprintf : Ok
56: mem2node : Ok
57: x86 rdpmc : Ok
58: Convert perf time to TSC : Ok
59: DWARF unwind : Ok
60: x86 instruction decoder - new instructions : Ok
61: Use vfs_getname probe to get syscall args filenames : Ok
62: Check open filename arg using perf trace + vfs_getname: Ok
63: probe libc's inet_pton & backtrace it with ping : Ok
64: Add vfs_getname probe to get syscall args filenames : Ok
#
$ make -C tools/perf build-test
make: Entering directory '/home/acme/git/perf/tools/perf'
- tarpkg: ./tests/perf-targz-src-pkg .
make_no_libperl_O: make NO_LIBPERL=1
make_no_newt_O: make NO_NEWT=1
make_debug_O: make DEBUG=1
make_with_clangllvm_O: make LIBCLANGLLVM=1
make_no_demangle_O: make NO_DEMANGLE=1
make_no_libelf_O: make NO_LIBELF=1
make_with_babeltrace_O: make LIBBABELTRACE=1
make_pure_O: make
make_no_libaudit_O: make NO_LIBAUDIT=1
make_no_libdw_dwarf_unwind_O: make NO_LIBDW_DWARF_UNWIND=1
make_no_ui_O: make NO_NEWT=1 NO_SLANG=1 NO_GTK2=1
make_perf_o_O: make perf.o
make_tags_O: make tags
make_no_libnuma_O: make NO_LIBNUMA=1
make_util_pmu_bison_o_O: make util/pmu-bison.o
make_install_prefix_O: make install prefix=/tmp/krava
make_no_libpython_O: make NO_LIBPYTHON=1
make_no_libunwind_O: make NO_LIBUNWIND=1
make_doc_O: make doc
make_minimal_O: make NO_LIBPERL=1 NO_LIBPYTHON=1 NO_NEWT=1 NO_GTK2=1 NO_DEMANGLE=1 NO_LIBELF=1 NO_LIBUNWIND=1 NO_BACKTRACE=1 NO_LIBNUMA=1 NO_LIBAUDIT=1 NO_LIBBIONIC=1 NO_LIBDW_DWARF_UNWIND=1 NO_AUXTRACE=1 NO_LIBBPF=1 NO_LIBCRYPTO=1 NO_SDT=1 NO_JVMTI=1
make_no_gtk2_O: make NO_GTK2=1
make_install_O: make install
make_install_bin_O: make install-bin
make_help_O: make help
make_static_O: make LDFLAGS=-static
make_no_auxtrace_O: make NO_AUXTRACE=1
make_no_backtrace_O: make NO_BACKTRACE=1
make_install_prefix_slash_O: make install prefix=/tmp/krava/
make_no_scripts_O: make NO_LIBPYTHON=1 NO_LIBPERL=1
make_no_slang_O: make NO_SLANG=1
make_util_map_o_O: make util/map.o
make_no_libbionic_O: make NO_LIBBIONIC=1
make_no_libbpf_O: make NO_LIBBPF=1
make_clean_all_O: make clean all
OK
make: Leaving directory '/home/acme/git/perf/tools/perf'
$
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 11/31] perf vendor events: Drop incomplete multiple mapfile support
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 12/31] perf vendor events: Fix error code in json_events() Arnaldo Carvalho de Melo
` (10 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
Currently jevents supports multiple mapfiles, but this is only in the
form where mapfile basename starts with 'mapfile.csv'
At the moment, no architectures actually use multiple mapfiles, so drop
the support for now.
This patch also solves a nuisance where, when the mapfile is edited and
the text editor may create a backup, jevents may use the backup, as
shown:
jevents: Many mapfiles? Using pmu-events/arch/arm64/mapfile.csv~, ignoring pmu-events/arch/arm64/mapfile.csv
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-2-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/README | 5 ++---
tools/perf/pmu-events/jevents.c | 10 ++--------
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index c2ee3e4417fe..2407abc1d441 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -11,9 +11,8 @@ tree tools/perf/pmu-events/arch/foo.
- Regular files with '.json' extension in the name are assumed to be
JSON files, each of which describes a set of PMU events.
- - Regular files with basename starting with 'mapfile.csv' are assumed
- to be a CSV file that maps a specific CPU to its set of PMU events.
- (see below for mapfile format)
+ - The CSV file that maps a specific CPU to its set of PMU events is to
+ be named 'mapfile.csv' (see below for mapfile format).
- Directories are traversed, but all other files are ignored.
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index b578aa26e375..9e0a21e74a67 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -798,16 +798,10 @@ static int process_one_file(const char *fpath, const struct stat *sb,
* after processing all JSON files (so we can write out the
* mapping table after all PMU events tables).
*
- * TODO: Allow for multiple mapfiles? Punt for now.
*/
if (level == 1 && is_file) {
- if (!strncmp(bname, "mapfile.csv", 11)) {
- if (mapfile) {
- pr_info("%s: Many mapfiles? Using %s, ignoring %s\n",
- prog, mapfile, fpath);
- } else {
- mapfile = strdup(fpath);
- }
+ if (!strcmp(bname, "mapfile.csv")) {
+ mapfile = strdup(fpath);
return 0;
}
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 12/31] perf vendor events: Fix error code in json_events()
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 11/31] perf vendor events: Drop incomplete multiple mapfile support Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 13/31] perf vendor events: Drop support for unused topic directories Arnaldo Carvalho de Melo
` (9 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
When EXPECT macro fails an assertion, the error code is not properly set
after the first loop of tokens in function json_events().
This is because err is set to the return value from func function
pointer call, which must be 0 to continue to loop, yet it is not reset
for for each loop. I assume that this was not the intention, so change
the code so err is set appropriately in EXPECT macro itself.
In addition to this, the indention in EXPECT macro is tidied. The
current indention alludes that the 2 statements following the if
statement are in the body, which is not true.
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-3-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/jevents.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 9e0a21e74a67..edff989fbcea 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -249,9 +249,10 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)
jsmntok_t *loc = (t); \
if (!(t)->start && (t) > tokens) \
loc = (t) - 1; \
- pr_err("%s:%d: " m ", got %s\n", fn, \
- json_line(map, loc), \
- json_name(t)); \
+ pr_err("%s:%d: " m ", got %s\n", fn, \
+ json_line(map, loc), \
+ json_name(t)); \
+ err = -EIO; \
goto out_free; \
} } while (0)
@@ -416,7 +417,7 @@ int json_events(const char *fn,
char *metric_name, char *metric_group),
void *data)
{
- int err = -EIO;
+ int err;
size_t size;
jsmntok_t *tokens, *tok;
int i, j, len;
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 13/31] perf vendor events: Drop support for unused topic directories
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 11/31] perf vendor events: Drop incomplete multiple mapfile support Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 12/31] perf vendor events: Fix error code in json_events() Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 14/31] perf vendor events: Add support for pmu events vendor subdirectory Arnaldo Carvalho de Melo
` (8 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
Currently a topic subdirectory is supported in the pmu-events dir, in
the following sample structure: /arch/platform/subtopic/mysubtopic.json
Upto 256 levels of topic subdirectories are supported. So this means
that JSONs may be located in a topic dir as well as the platform dir.
This topic subdirectory causes problems if we want to add support for a
vendor dir in the pmu-events structure (in the form
arch/platform/vendor), in that we cannot differentiate between a vendor
dir and a topic dir.
Since the topic dir feature is not used, drop it so it does not block
adding vendor subdirectory support.
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-4-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/jevents.c | 37 ++++++++++---------------------------
1 file changed, 10 insertions(+), 27 deletions(-)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index edff989fbcea..1d02fafdc34d 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -256,25 +256,18 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)
goto out_free; \
} } while (0)
-#define TOPIC_DEPTH 256
-static char *topic_array[TOPIC_DEPTH];
-static int topic_level;
+static char *topic;
static char *get_topic(void)
{
- char *tp_old, *tp = NULL;
+ char *tp;
int i;
- for (i = 0; i < topic_level + 1; i++) {
- int n;
-
- tp_old = tp;
- n = asprintf(&tp, "%s%s", tp ?: "", topic_array[i]);
- if (n < 0) {
- pr_info("%s: asprintf() error %s\n", prog);
- return NULL;
- }
- free(tp_old);
+ /* tp is free'd in process_one_file() */
+ i = asprintf(&tp, "%s", topic);
+ if (i < 0) {
+ pr_info("%s: asprintf() error %s\n", prog);
+ return NULL;
}
for (i = 0; i < (int) strlen(tp); i++) {
@@ -291,25 +284,15 @@ static char *get_topic(void)
return tp;
}
-static int add_topic(int level, char *bname)
+static int add_topic(char *bname)
{
- char *topic;
-
- level -= 2;
-
- if (level >= TOPIC_DEPTH)
- return -EINVAL;
-
+ free(topic);
topic = strdup(bname);
if (!topic) {
pr_info("%s: strdup() error %s for file %s\n", prog,
strerror(errno), bname);
return -ENOMEM;
}
-
- free(topic_array[topic_level]);
- topic_array[topic_level] = topic;
- topic_level = level;
return 0;
}
@@ -824,7 +807,7 @@ static int process_one_file(const char *fpath, const struct stat *sb,
}
}
- if (level > 1 && add_topic(level, bname))
+ if (level > 1 && add_topic(bname))
return -ENOMEM;
/*
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 14/31] perf vendor events: Add support for pmu events vendor subdirectory
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (2 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 13/31] perf vendor events: Drop support for unused topic directories Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 15/31] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory Arnaldo Carvalho de Melo
` (7 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
For some architectures (like arm), it is required to support a vendor
subdirectory and not locate all the JSONs for a specific vendor in the
same folder.
This is because all the events for the same vendor will be placed in the
same pmu events table, which may cause conflict. This conflict would be
in the instance that a vendor's custom implemented events do have the
same meaning on different platforms, so events in the pmu table would
conflict. In addition, per list command may show events which are not
even supported for a given platform.
This patch adds support for a arch/vendor/platform directory hierarchy,
while maintaining backwards-compatibility for existing arch/platform
structure. In this, each platform would always have its own pmu events
table.
In generated file pmu_events.c, each platform table name is in the
format pme{_vendor}_platform, like this:
struct pmu_events_map pmu_events_map[] = {
{
.cpuid = "0x00000000420f5160",
.version = "v1",
.type = "core",
.table = pme_cavium_thunderx2
},
{
.cpuid = 0,
.version = 0,
.type = 0,
.table = 0,
},
};
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-5-git-send-email-john.garry at huawei.com
[ Add missing limits.h include, fixing the build on at least all Alpine Linux versions tested (3.4 to 3.7 + edge) ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/README | 4 +++
tools/perf/pmu-events/jevents.c | 65 +++++++++++++++++++++++++++++++++++++----
2 files changed, 63 insertions(+), 6 deletions(-)
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 2407abc1d441..655286ff8767 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU:
Cache.json Memory.json Virtual-Memory.json
Frontend.json Pipeline.json
+The JSONs folder for a CPU model/family may be placed in the root arch
+folder, or may be placed in a vendor sub-folder under the arch folder
+for instances where the arch and vendor are not the same.
+
Using the JSON files and the mapfile, 'jevents' generates the C source file,
'pmu-events.c', which encodes the two sets of tables:
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 1d02fafdc34d..b08dffeac4bd 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -39,6 +39,7 @@
#include <unistd.h>
#include <stdarg.h>
#include <libgen.h>
+#include <limits.h>
#include <dirent.h>
#include <sys/time.h> /* getrlimit */
#include <sys/resource.h> /* getrlimit */
@@ -572,7 +573,7 @@ static char *file_name_to_table_name(char *fname)
* Derive rest of table name from basename of the JSON file,
* replacing hyphens and stripping out .json suffix.
*/
- n = asprintf(&tblname, "pme_%s", basename(fname));
+ n = asprintf(&tblname, "pme_%s", fname);
if (n < 0) {
pr_info("%s: asprintf() error %s for file %s\n", prog,
strerror(errno), fname);
@@ -582,7 +583,7 @@ static char *file_name_to_table_name(char *fname)
for (i = 0; i < strlen(tblname); i++) {
c = tblname[i];
- if (c == '-')
+ if (c == '-' || c == '/')
tblname[i] = '_';
else if (c == '.') {
tblname[i] = '\0';
@@ -739,25 +740,77 @@ static int get_maxfds(void)
static FILE *eventsfp;
static char *mapfile;
+static int is_leaf_dir(const char *fpath)
+{
+ DIR *d;
+ struct dirent *dir;
+ int res = 1;
+
+ d = opendir(fpath);
+ if (!d)
+ return 0;
+
+ while ((dir = readdir(d)) != NULL) {
+ if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
+ res = 0;
+ break;
+ } else if (dir->d_type == DT_UNKNOWN) {
+ char path[PATH_MAX];
+ struct stat st;
+
+ sprintf(path, "%s/%s", fpath, dir->d_name);
+ if (stat(path, &st))
+ break;
+
+ if (S_ISDIR(st.st_mode)) {
+ res = 0;
+ break;
+ }
+ }
+ }
+
+ closedir(d);
+
+ return res;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
- char *tblname, *bname = (char *) fpath + ftwbuf->base;
+ char *tblname, *bname;
int is_dir = typeflag == FTW_D;
int is_file = typeflag == FTW_F;
int level = ftwbuf->level;
int err = 0;
+ if (level == 2 && is_dir) {
+ /*
+ * For level 2 directory, bname will include parent name,
+ * like vendor/platform. So search back from platform dir
+ * to find this.
+ */
+ bname = (char *) fpath + ftwbuf->base - 2;
+ for (;;) {
+ if (*bname == '/')
+ break;
+ bname--;
+ }
+ bname++;
+ } else
+ bname = (char *) fpath + ftwbuf->base;
+
pr_debug("%s %d %7jd %-20s %s\n",
is_file ? "f" : is_dir ? "d" : "x",
level, sb->st_size, bname, fpath);
- /* base dir */
- if (level == 0)
+ /* base dir or too deep */
+ if (level == 0 || level > 3)
return 0;
+
/* model directory, reset topic */
- if (level == 1 && is_dir) {
+ if ((level == 1 && is_dir && is_leaf_dir(fpath)) ||
+ (level == 2 && is_dir)) {
if (close_table)
print_events_table_suffix(eventsfp);
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 15/31] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (3 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 14/31] perf vendor events: Add support for pmu events vendor subdirectory Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 16/31] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory Arnaldo Carvalho de Melo
` (6 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
Since jevents now supports vendor subdirectory, relocate
the ThunderX2 JSON to Cavium subdirectory.
Signed-off-by: John Garry <john.garry@huawei.com>
Tested-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-6-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../cavium/{thunderx2-imp-def.json => thunderx2/core-imp-def.json} | 0
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename tools/perf/pmu-events/arch/arm64/cavium/{thunderx2-imp-def.json => thunderx2/core-imp-def.json} (100%)
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
rename to tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index e61c9ca6cf9e..952a05cbf675 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
-0x00000000420f5160,v1,cavium,core
+0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 16/31] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (4 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 15/31] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 17/31] perf vendor events: Add support for arch standard events Arnaldo Carvalho de Melo
` (5 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
Since jevents now supports vendor subdirectory, relocate the Cortex-A53
JSONs to arm subdirectory.
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-7-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/bus.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/cache.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/other.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json | 0
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
7 files changed, 1 insertion(+), 1 deletion(-)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/bus.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/cache.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/other.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json (100%)
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 952a05cbf675..cf14e23b6404 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
+0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
-0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 17/31] perf vendor events: Add support for arch standard events
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (5 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 16/31] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json Arnaldo Carvalho de Melo
` (4 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
For some architectures (like arm), there are architecture- defined
events. Sometimes these events may be "recommended" according to the
architecture standard, in that the implementer is free ignore the
"recommendation" and create its custom event.
This patch adds support for parsing standard events from arch-defined
JSONs, and fixing up vendor events when they have implemented these
events as standard.
Support is also ensured that the vendor may implement their own custom
events.
A new step is added to the pmu events parsing to fix up the vendor
events with the arch-standard events.
The arch-defined JSONs must be placed in the arch root folder for
preprocessing prior to tree JSON processing.
In the vendor JSON, to specify that the arch event is supported, the
keyword "ArchStdEvent" should be used, like this:
[
{
"ArchStdEvent": "L1D_CACHE_WR",
},
]
Matching is based on the "EventName" field in the architecture JSON.
No other JSON objects are strictly required. However, for other objects
added, these take precedence over architecture defined standard events,
thus supporting separate events which have the same event code.
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-8-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/Build | 2 +
tools/perf/pmu-events/README | 6 ++
tools/perf/pmu-events/jevents.c | 167 +++++++++++++++++++++++++++++++++++++++-
3 files changed, 172 insertions(+), 3 deletions(-)
diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build
index 999a4e878162..17783913d330 100644
--- a/tools/perf/pmu-events/Build
+++ b/tools/perf/pmu-events/Build
@@ -1,10 +1,12 @@
hostprogs := jevents
jevents-y += json.o jsmn.o jevents.o
+CHOSTFLAGS_jevents.o = -I$(srctree)/tools/include
pmu-events-y += pmu-events.o
JDIR = pmu-events/arch/$(SRCARCH)
JSON = $(shell [ -d $(JDIR) ] && \
find $(JDIR) -name '*.json' -o -name 'mapfile.csv')
+
#
# Locate/process JSON files in pmu-events/arch/
# directory and create tables in pmu-events.c.
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 655286ff8767..e62b09b6a844 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -16,6 +16,12 @@ tree tools/perf/pmu-events/arch/foo.
- Directories are traversed, but all other files are ignored.
+ - To reduce JSON event duplication per architecture, platform JSONs may
+ use "ArchStdEvent" keyword to dereference an "Architecture standard
+ events", defined in architecture standard JSONs.
+ Architecture standard JSONs must be located in the architecture root
+ folder. Matching is based on the "EventName" field.
+
The PMU events supported by a CPU model are expected to grouped into topics
such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic
should be placed in a separate JSON file - where the file name identifies
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index b08dffeac4bd..1c018445e757 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -45,6 +45,7 @@
#include <sys/resource.h> /* getrlimit */
#include <ftw.h>
#include <sys/stat.h>
+#include <linux/list.h>
#include "jsmn.h"
#include "json.h"
#include "jevents.h"
@@ -351,6 +352,81 @@ static int print_events_table_entry(void *data, char *name, char *event,
return 0;
}
+struct event_struct {
+ struct list_head list;
+ char *name;
+ char *event;
+ char *desc;
+ char *long_desc;
+ char *pmu;
+ char *unit;
+ char *perpkg;
+ char *metric_expr;
+ char *metric_name;
+ char *metric_group;
+};
+
+#define ADD_EVENT_FIELD(field) do { if (field) { \
+ es->field = strdup(field); \
+ if (!es->field) \
+ goto out_free; \
+} } while (0)
+
+#define FREE_EVENT_FIELD(field) free(es->field)
+
+#define TRY_FIXUP_FIELD(field) do { if (es->field && !*field) {\
+ *field = strdup(es->field); \
+ if (!*field) \
+ return -ENOMEM; \
+} } while (0)
+
+#define FOR_ALL_EVENT_STRUCT_FIELDS(op) do { \
+ op(name); \
+ op(event); \
+ op(desc); \
+ op(long_desc); \
+ op(pmu); \
+ op(unit); \
+ op(perpkg); \
+ op(metric_expr); \
+ op(metric_name); \
+ op(metric_group); \
+} while (0)
+
+static LIST_HEAD(arch_std_events);
+
+static void free_arch_std_events(void)
+{
+ struct event_struct *es, *next;
+
+ list_for_each_entry_safe(es, next, &arch_std_events, list) {
+ FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD);
+ list_del(&es->list);
+ free(es);
+ }
+}
+
+static int save_arch_std_events(void *data, char *name, char *event,
+ char *desc, char *long_desc, char *pmu,
+ char *unit, char *perpkg, char *metric_expr,
+ char *metric_name, char *metric_group)
+{
+ struct event_struct *es;
+ struct stat *sb = data;
+
+ es = malloc(sizeof(*es));
+ if (!es)
+ return -ENOMEM;
+ memset(es, 0, sizeof(*es));
+ FOR_ALL_EVENT_STRUCT_FIELDS(ADD_EVENT_FIELD);
+ list_add_tail(&es->list, &arch_std_events);
+ return 0;
+out_free:
+ FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD);
+ free(es);
+ return -ENOMEM;
+}
+
static void print_events_table_suffix(FILE *outfp)
{
fprintf(outfp, "{\n");
@@ -392,6 +468,32 @@ static char *real_event(const char *name, char *event)
return event;
}
+static int
+try_fixup(const char *fn, char *arch_std, char **event, char **desc,
+ char **name, char **long_desc, char **pmu, char **filter,
+ char **perpkg, char **unit, char **metric_expr, char **metric_name,
+ char **metric_group, unsigned long long eventcode)
+{
+ /* try to find matching event from arch standard values */
+ struct event_struct *es;
+
+ list_for_each_entry(es, &arch_std_events, list) {
+ if (!strcmp(arch_std, es->name)) {
+ if (!eventcode && es->event) {
+ /* allow EventCode to be overridden */
+ free(*event);
+ *event = NULL;
+ }
+ FOR_ALL_EVENT_STRUCT_FIELDS(TRY_FIXUP_FIELD);
+ return 0;
+ }
+ }
+
+ pr_err("%s: could not find matching %s for %s\n",
+ prog, arch_std, fn);
+ return -1;
+}
+
/* Call func with each event in the json file */
int json_events(const char *fn,
int (*func)(void *data, char *name, char *event, char *desc,
@@ -427,6 +529,7 @@ int json_events(const char *fn,
char *metric_expr = NULL;
char *metric_name = NULL;
char *metric_group = NULL;
+ char *arch_std = NULL;
unsigned long long eventcode = 0;
struct msrmap *msr = NULL;
jsmntok_t *msrval = NULL;
@@ -512,6 +615,10 @@ int json_events(const char *fn,
addfield(map, &metric_expr, "", "", val);
for (s = metric_expr; *s; s++)
*s = tolower(*s);
+ } else if (json_streq(map, field, "ArchStdEvent")) {
+ addfield(map, &arch_std, "", "", val);
+ for (s = arch_std; *s; s++)
+ *s = tolower(*s);
}
/* ignore unknown fields */
}
@@ -536,8 +643,21 @@ int json_events(const char *fn,
if (name)
fixname(name);
+ if (arch_std) {
+ /*
+ * An arch standard event is referenced, so try to
+ * fixup any unassigned values.
+ */
+ err = try_fixup(fn, arch_std, &event, &desc, &name,
+ &long_desc, &pmu, &filter, &perpkg,
+ &unit, &metric_expr, &metric_name,
+ &metric_group, eventcode);
+ if (err)
+ goto free_strings;
+ }
err = func(data, name, real_event(name, event), desc, long_desc,
pmu, unit, perpkg, metric_expr, metric_name, metric_group);
+free_strings:
free(event);
free(desc);
free(name);
@@ -550,6 +670,8 @@ int json_events(const char *fn,
free(metric_expr);
free(metric_name);
free(metric_group);
+ free(arch_std);
+
if (err)
break;
tok += j;
@@ -774,6 +896,32 @@ static int is_leaf_dir(const char *fpath)
return res;
}
+static int is_json_file(const char *name)
+{
+ const char *suffix;
+
+ if (strlen(name) < 5)
+ return 0;
+
+ suffix = name + strlen(name) - 5;
+
+ if (strncmp(suffix, ".json", 5) == 0)
+ return 1;
+ return 0;
+}
+
+static int preprocess_arch_std_files(const char *fpath, const struct stat *sb,
+ int typeflag, struct FTW *ftwbuf)
+{
+ int level = ftwbuf->level;
+ int is_file = typeflag == FTW_F;
+
+ if (level == 1 && is_file && is_json_file(fpath))
+ return json_events(fpath, save_arch_std_events, (void *)sb);
+
+ return 0;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
@@ -851,9 +999,7 @@ static int process_one_file(const char *fpath, const struct stat *sb,
* ignore it. It could be a readme.txt for instance.
*/
if (is_file) {
- char *suffix = bname + strlen(bname) - 5;
-
- if (strncmp(suffix, ".json", 5)) {
+ if (!is_json_file(bname)) {
pr_info("%s: Ignoring file without .json suffix %s\n", prog,
fpath);
return 0;
@@ -959,12 +1105,26 @@ int main(int argc, char *argv[])
maxfds = get_maxfds();
mapfile = NULL;
+ rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0);
+ if (rc && verbose) {
+ pr_info("%s: Error preprocessing arch standard files %s\n",
+ prog, ldirname);
+ goto empty_map;
+ } else if (rc < 0) {
+ /* Make build fail */
+ free_arch_std_events();
+ return 1;
+ } else if (rc) {
+ goto empty_map;
+ }
+
rc = nftw(ldirname, process_one_file, maxfds, 0);
if (rc && verbose) {
pr_info("%s: Error walking file tree %s\n", prog, ldirname);
goto empty_map;
} else if (rc < 0) {
/* Make build fail */
+ free_arch_std_events();
return 1;
} else if (rc) {
goto empty_map;
@@ -989,5 +1149,6 @@ int main(int argc, char *argv[])
empty_map:
fclose(eventsfp);
create_empty_mapping(output_file);
+ free_arch_std_events();
return 0;
}
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (6 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 17/31] perf vendor events: Add support for arch standard events Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 14:26 ` Ingo Molnar
2018-03-13 12:04 ` [PATCH 19/31] perf vendor events arm64: Fixup ThunderX2 to use recommended events Arnaldo Carvalho de Melo
` (3 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available
here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.com
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++
1 file changed, 452 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
new file mode 100644
index 000000000000..6328828c018c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
@@ -0,0 +1,452 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE_RD",
+ "BriefDescription": "L1D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write",
+ "EventCode": "0x41",
+ "EventName": "L1D_CACHE_WR",
+ "BriefDescription": "L1D cache access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "L1D_CACHE_REFILL_RD",
+ "BriefDescription": "L1D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "L1D_CACHE_REFILL_WR",
+ "BriefDescription": "L1D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, inner",
+ "EventCode": "0x44",
+ "EventName": "L1D_CACHE_REFILL_INNER",
+ "BriefDescription": "L1D cache refill, inner"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, outer",
+ "EventCode": "0x45",
+ "EventName": "L1D_CACHE_REFILL_OUTER",
+ "BriefDescription": "L1D cache refill, outer"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
+ "EventCode": "0x46",
+ "EventName": "L1D_CACHE_WB_VICTIM",
+ "BriefDescription": "L1D cache Write-Back, victim"
+ },
+ {
+ "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x47",
+ "EventName": "L1D_CACHE_WB_CLEAN",
+ "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache invalidate",
+ "EventCode": "0x48",
+ "EventName": "L1D_CACHE_INVAL",
+ "BriefDescription": "L1D cache invalidate"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "L1D_TLB_REFILL_RD",
+ "BriefDescription": "L1D tlb refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "L1D_TLB_REFILL_WR",
+ "BriefDescription": "L1D tlb refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "L1D_TLB_RD",
+ "BriefDescription": "L1D tlb access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "L1D_TLB_WR",
+ "BriefDescription": "L1D tlb access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, read",
+ "EventCode": "0x50",
+ "EventName": "L2D_CACHE_RD",
+ "BriefDescription": "L2D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, write",
+ "EventCode": "0x51",
+ "EventName": "L2D_CACHE_WR",
+ "BriefDescription": "L2D cache access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, read",
+ "EventCode": "0x52",
+ "EventName": "L2D_CACHE_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, write",
+ "EventCode": "0x53",
+ "EventName": "L2D_CACHE_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache Write-Back, victim",
+ "EventCode": "0x56",
+ "EventName": "L2D_CACHE_WB_VICTIM",
+ "BriefDescription": "L2D cache Write-Back, victim"
+ },
+ {
+ "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x57",
+ "EventName": "L2D_CACHE_WB_CLEAN",
+ "BriefDescription": "L2D cache Write-Back, cleaning and coherency"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache invalidate",
+ "EventCode": "0x58",
+ "EventName": "L2D_CACHE_INVAL",
+ "BriefDescription": "L2D cache invalidate"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
+ "EventCode": "0x5c",
+ "EventName": "L2D_TLB_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB refill, write",
+ "EventCode": "0x5d",
+ "EventName": "L2D_TLB_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB access, read",
+ "EventCode": "0x5e",
+ "EventName": "L2D_TLB_RD",
+ "BriefDescription": "L2D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB access, write",
+ "EventCode": "0x5f",
+ "EventName": "L2D_TLB_WR",
+ "BriefDescription": "L2D cache access, write"
+ },
+ {
+ "PublicDescription": "Bus access read",
+ "EventCode": "0x60",
+ "EventName": "BUS_ACCESS_RD",
+ "BriefDescription": "Bus access read"
+ },
+ {
+ "PublicDescription": "Bus access write",
+ "EventCode": "0x61",
+ "EventName": "BUS_ACCESS_WR",
+ "BriefDescription": "Bus access write"
+ }
+ {
+ "PublicDescription": "Bus access, Normal, Cacheable, Shareable",
+ "EventCode": "0x62",
+ "EventName": "BUS_ACCESS_SHARED",
+ "BriefDescription": "Bus access, Normal, Cacheable, Shareable"
+ }
+ {
+ "PublicDescription": "Bus access, not Normal, Cacheable, Shareable",
+ "EventCode": "0x63",
+ "EventName": "BUS_ACCESS_NOT_SHARED",
+ "BriefDescription": "Bus access, not Normal, Cacheable, Shareable"
+ }
+ {
+ "PublicDescription": "Bus access, Normal",
+ "EventCode": "0x64",
+ "EventName": "BUS_ACCESS_NORMAL",
+ "BriefDescription": "Bus access, Normal"
+ }
+ {
+ "PublicDescription": "Bus access, peripheral",
+ "EventCode": "0x65",
+ "EventName": "BUS_ACCESS_PERIPH",
+ "BriefDescription": "Bus access, peripheral"
+ }
+ {
+ "PublicDescription": "Data memory access, read",
+ "EventCode": "0x66",
+ "EventName": "MEM_ACCESS_RD",
+ "BriefDescription": "Data memory access, read"
+ }
+ {
+ "PublicDescription": "Data memory access, write",
+ "EventCode": "0x67",
+ "EventName": "MEM_ACCESS_WR",
+ "BriefDescription": "Data memory access, write"
+ }
+ {
+ "PublicDescription": "Unaligned access, read",
+ "EventCode": "0x68",
+ "EventName": "UNALIGNED_LD_SPEC",
+ "BriefDescription": "Unaligned access, read"
+ }
+ {
+ "PublicDescription": "Unaligned access, write",
+ "EventCode": "0x69",
+ "EventName": "UNALIGNED_ST_SPEC",
+ "BriefDescription": "Unaligned access, write"
+ }
+ {
+ "PublicDescription": "Unaligned access",
+ "EventCode": "0x6a",
+ "EventName": "UNALIGNED_LDST_SPEC",
+ "BriefDescription": "Unaligned access"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX",
+ "EventCode": "0x6c",
+ "EventName": "LDREX_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass",
+ "EventCode": "0x6d",
+ "EventName": "STREX_PASS_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail",
+ "EventCode": "0x6e",
+ "EventName": "STREX_FAIL_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX",
+ "EventCode": "0x6f",
+ "EventName": "STREX_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, load",
+ "EventCode": "0x70",
+ "EventName": "LD_SPEC",
+ "BriefDescription": "Operation speculatively executed, load"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, store"
+ "EventCode": "0x71",
+ "EventName": "ST_SPEC",
+ "BriefDescription": "Operation speculatively executed, store"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, load or store",
+ "EventCode": "0x72",
+ "EventName": "LDST_SPEC",
+ "BriefDescription": "Operation speculatively executed, load or store"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, integer data processing",
+ "EventCode": "0x73",
+ "EventName": "DP_SPEC",
+ "BriefDescription": "Operation speculatively executed, integer data processing"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction",
+ "EventCode": "0x74",
+ "EventName": "ASE_SPEC",
+ "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction",
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, floating-point instruction",
+ "EventCode": "0x75",
+ "EventName": "VFP_SPEC",
+ "BriefDescription": "Operation speculatively executed, floating-point instruction"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, software change of the PC",
+ "EventCode": "0x76",
+ "EventName": "PC_WRITE_SPEC",
+ "BriefDescription": "Operation speculatively executed, software change of the PC"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, Cryptographic instruction",
+ "EventCode": "0x77",
+ "EventName": "CRYPTO_SPEC",
+ "BriefDescription": "Operation speculatively executed, Cryptographic instruction"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, immediate branch"
+ "EventCode": "0x78",
+ "EventName": "BR_IMMED_SPEC",
+ "BriefDescription": "Branch speculatively executed, immediate branch"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, procedure return"
+ "EventCode": "0x79",
+ "EventName": "BR_RETURN_SPEC",
+ "BriefDescription": "Branch speculatively executed, procedure return"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, indirect branch"
+ "EventCode": "0x7a",
+ "EventName": "BR_INDIRECT_SPEC",
+ "BriefDescription": "Branch speculatively executed, indirect branch"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, ISB"
+ "EventCode": "0x7c",
+ "EventName": "ISB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, ISB"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, DSB"
+ "EventCode": "0x7d",
+ "EventName": "DSB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, DSB"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, DMB"
+ "EventCode": "0x7e",
+ "EventName": "DMB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, DMB"
+ }
+ {
+ "PublicDescription": "Exception taken, Other synchronous"
+ "EventCode": "0x81",
+ "EventName": "EXC_UNDEF",
+ "BriefDescription": "Exception taken, Other synchronous"
+ }
+ {
+ "PublicDescription": "Exception taken, Supervisor Call"
+ "EventCode": "0x82",
+ "EventName": "EXC_SVC",
+ "BriefDescription": "Exception taken, Supervisor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Instruction Abort"
+ "EventCode": "0x83",
+ "EventName": "EXC_PABORT",
+ "BriefDescription": "Exception taken, Instruction Abort"
+ }
+ {
+ "PublicDescription": "Exception taken, Data Abort and SError"
+ "EventCode": "0x84",
+ "EventName": "EXC_DABORT",
+ "BriefDescription": "Exception taken, Data Abort and SError"
+ }
+ {
+ "PublicDescription": "Exception taken, IRQ"
+ "EventCode": "0x86",
+ "EventName": "EXC_IRQ",
+ "BriefDescription": "Exception taken, IRQ"
+ }
+ {
+ "PublicDescription": "Exception taken, FIQ"
+ "EventCode": "0x87",
+ "EventName": "EXC_FIQ",
+ "BriefDescription": "Exception taken, FIQ"
+ }
+ {
+ "PublicDescription": "Exception taken, Secure Monitor Call"
+ "EventCode": "0x88",
+ "EventName": "EXC_SMC",
+ "BriefDescription": "Exception taken, Secure Monitor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Hypervisor Call"
+ "EventCode": "0x8a",
+ "EventName": "EXC_HVC",
+ "BriefDescription": "Exception taken, Hypervisor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Instruction Abort not taken locally"
+ "EventCode": "0x8b",
+ "EventName": "EXC_TRAP_PABORT",
+ "BriefDescription": "Exception taken, Instruction Abort not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, Data Abort or SError not taken locally"
+ "EventCode": "0x8c",
+ "EventName": "EXC_TRAP_DABORT",
+ "BriefDescription": "Exception taken, Data Abort or SError not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, Other traps not taken locally"
+ "EventCode": "0x8d",
+ "EventName": "EXC_TRAP_OTHER",
+ "BriefDescription": "Exception taken, Other traps not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, IRQ not taken locally"
+ "EventCode": "0x8e",
+ "EventName": "EXC_TRAP_IRQ",
+ "BriefDescription": "Exception taken, IRQ not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, FIQ not taken locally"
+ "EventCode": "0x8f",
+ "EventName": "EXC_TRAP_FIQ",
+ "BriefDescription": "Exception taken, FIQ not taken locally"
+ }
+ {
+ "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire"
+ "EventCode": "0x90",
+ "EventName": "RC_LD_SPEC",
+ "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire"
+ }
+ {
+ "PublicDescription": "Release consistency operation speculatively executed, Store-Release"
+ "EventCode": "0x91",
+ "EventName": "RC_ST_SPEC",
+ "BriefDescription": "Release consistency operation speculatively executed, Store-Release"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, read"
+ "EventCode": "0xa0",
+ "EventName": "L3D_CACHE_RD",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, read"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, write"
+ "EventCode": "0xa1",
+ "EventName": "L3D_CACHE_WR",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, write"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache refill, read"
+ "EventCode": "0xa2",
+ "EventName": "L3D_CACHE_REFILL_RD",
+ "BriefDescription": "Attributable Level 3 data or unified cache refill, read"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache refill, write"
+ "EventCode": "0xa3",
+ "EventName": "L3D_CACHE_REFILL_WR",
+ "BriefDescription": "Attributable Level 3 data or unified cache refill, write"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
+ "EventCode": "0xa6",
+ "EventName": "L3D_CACHE_WB_VICTIM",
+ "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
+ "EventCode": "0xa7",
+ "EventName": "L3D_CACHE_WB_CLEAN",
+ "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, invalidate"
+ "EventCode": "0xa8",
+ "EventName": "L3D_CACHE_INVAL",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, invalidate"
+ }
+]
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 19/31] perf vendor events arm64: Fixup ThunderX2 to use recommended events
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (7 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 20/31] perf vendor events arm64: fixup A53 " Arnaldo Carvalho de Melo
` (2 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
This patch fixes the Cavium ThunderX2 JSON to use event definitions from
the ARMv8 recommended events.
Signed-off-by: John Garry <john.garry@huawei.com>
Tested-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-10-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++-----------------
1 file changed, 10 insertions(+), 40 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index 2db45c40ebc7..bc03c06c3918 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -1,62 +1,32 @@
[
{
- "PublicDescription": "Attributable Level 1 data cache access, read",
- "EventCode": "0x40",
- "EventName": "l1d_cache_rd",
- "BriefDescription": "L1D cache read",
+ "ArchStdEvent": "L1D_CACHE_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache access, write ",
- "EventCode": "0x41",
- "EventName": "l1d_cache_wr",
- "BriefDescription": "L1D cache write",
+ "ArchStdEvent": "L1D_CACHE_WR",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, read",
- "EventCode": "0x42",
- "EventName": "l1d_cache_refill_rd",
- "BriefDescription": "L1D cache refill read",
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, write",
- "EventCode": "0x43",
- "EventName": "l1d_cache_refill_wr",
- "BriefDescription": "L1D refill write",
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, read",
- "EventCode": "0x4C",
- "EventName": "l1d_tlb_refill_rd",
- "BriefDescription": "L1D tlb refill read",
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, write",
- "EventCode": "0x4D",
- "EventName": "l1d_tlb_refill_wr",
- "BriefDescription": "L1D tlb refill write",
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
- "EventCode": "0x4E",
- "EventName": "l1d_tlb_rd",
- "BriefDescription": "L1D tlb read",
+ "ArchStdEvent": "L1D_TLB_RD",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
- "EventCode": "0x4F",
- "EventName": "l1d_tlb_wr",
- "BriefDescription": "L1D tlb write",
+ "ArchStdEvent": "L1D_TLB_WR",
},
{
- "PublicDescription": "Bus access read",
- "EventCode": "0x60",
- "EventName": "bus_access_rd",
- "BriefDescription": "Bus access read",
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
{
- "PublicDescription": "Bus access write",
- "EventCode": "0x61",
- "EventName": "bus_access_wr",
- "BriefDescription": "Bus access write",
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 20/31] perf vendor events arm64: fixup A53 to use recommended events
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (8 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 19/31] perf vendor events arm64: Fixup ThunderX2 to use recommended events Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 21/31] perf vendor events arm64: add HiSilicon hip08 JSON file Arnaldo Carvalho de Melo
2018-03-13 12:05 ` [PATCH 24/31] perf vendor events arm64: Enable JSON events for ThunderX2 B0 Arnaldo Carvalho de Melo
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
This patch fixes the ARM Cortex-A53 json to use event definition from
the ARMv8 recommended events.
In addition to this change, other changes were made:
- remove stray ','
- remove mirrored events in memory.json and bus.json
- fixed indentation to be consistent with other ARM
JSONs
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-11-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../arch/arm64/arm/cortex-a53/branch.json | 14 +++----
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 ++---------
.../arch/arm64/arm/cortex-a53/cache.json | 40 ++++++++++----------
.../arch/arm64/arm/cortex-a53/memory.json | 14 +------
.../arch/arm64/arm/cortex-a53/other.json | 44 ++++++++++------------
.../arch/arm64/arm/cortex-a53/pipeline.json | 20 +++++-----
6 files changed, 62 insertions(+), 92 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
index 3b6208763e50..0b0e6b26605b 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
@@ -1,25 +1,23 @@
[
- {,
- "EventCode": "0x7A",
- "EventName": "BR_INDIRECT_SPEC",
- "BriefDescription": "Branch speculatively executed - Indirect branch"
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
},
- {,
+ {
"EventCode": "0xC9",
"EventName": "BR_COND",
"BriefDescription": "Conditional branch executed"
},
- {,
+ {
"EventCode": "0xCA",
"EventName": "BR_INDIRECT_MISPRED",
"BriefDescription": "Indirect branch mispredicted"
},
- {,
+ {
"EventCode": "0xCB",
"EventName": "BR_INDIRECT_MISPRED_ADDR",
"BriefDescription": "Indirect branch mispredicted because of address miscompare"
},
- {,
+ {
"EventCode": "0xCC",
"EventName": "BR_COND_MISPRED",
"BriefDescription": "Conditional branch mispredicted"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
index 480d9f7460ab..ce33b2553277 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
@@ -1,22 +1,8 @@
[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
- "EventCode": "0xC0",
- "EventName": "EXT_MEM_REQ",
- "BriefDescription": "External memory request"
- },
- {,
- "EventCode": "0xC1",
- "EventName": "EXT_MEM_REQ_NC",
- "BriefDescription": "Non-cacheable external memory request"
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
index 11baad6344b9..5dfbec43c9f9 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
@@ -1,27 +1,27 @@
[
- {,
- "EventCode": "0xC2",
- "EventName": "PREFETCH_LINEFILL",
- "BriefDescription": "Linefill because of prefetch"
+ {
+ "EventCode": "0xC2",
+ "EventName": "PREFETCH_LINEFILL",
+ "BriefDescription": "Linefill because of prefetch"
},
- {,
- "EventCode": "0xC3",
- "EventName": "PREFETCH_LINEFILL_DROP",
- "BriefDescription": "Instruction Cache Throttle occurred"
+ {
+ "EventCode": "0xC3",
+ "EventName": "PREFETCH_LINEFILL_DROP",
+ "BriefDescription": "Instruction Cache Throttle occurred"
},
- {,
- "EventCode": "0xC4",
- "EventName": "READ_ALLOC_ENTER",
- "BriefDescription": "Entering read allocate mode"
+ {
+ "EventCode": "0xC4",
+ "EventName": "READ_ALLOC_ENTER",
+ "BriefDescription": "Entering read allocate mode"
},
- {,
- "EventCode": "0xC5",
- "EventName": "READ_ALLOC",
- "BriefDescription": "Read allocate mode"
+ {
+ "EventCode": "0xC5",
+ "EventName": "READ_ALLOC",
+ "BriefDescription": "Read allocate mode"
},
- {,
- "EventCode": "0xC8",
- "EventName": "EXT_SNOOP",
- "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+ {
+ "EventCode": "0xC8",
+ "EventName": "EXT_SNOOP",
+ "BriefDescription": "SCU Snooped data from another CPU for this CPU"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
index 480d9f7460ab..25ae642ba381 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
@@ -1,20 +1,10 @@
[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
- },
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
+ {
"EventCode": "0xC0",
"EventName": "EXT_MEM_REQ",
"BriefDescription": "External memory request"
},
- {,
+ {
"EventCode": "0xC1",
"EventName": "EXT_MEM_REQ_NC",
"BriefDescription": "Non-cacheable external memory request"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
index 73a22402d003..6cc6cbd7bf0b 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
@@ -1,32 +1,28 @@
[
- {,
- "EventCode": "0x86",
- "EventName": "EXC_IRQ",
- "BriefDescription": "Exception taken, IRQ"
+ {
+ "ArchStdEvent": "EXC_IRQ",
},
- {,
- "EventCode": "0x87",
- "EventName": "EXC_FIQ",
- "BriefDescription": "Exception taken, FIQ"
+ {
+ "ArchStdEvent": "EXC_FIQ",
},
- {,
- "EventCode": "0xC6",
- "EventName": "PRE_DECODE_ERR",
- "BriefDescription": "Pre-decode error"
+ {
+ "EventCode": "0xC6",
+ "EventName": "PRE_DECODE_ERR",
+ "BriefDescription": "Pre-decode error"
},
- {,
- "EventCode": "0xD0",
- "EventName": "L1I_CACHE_ERR",
- "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+ {
+ "EventCode": "0xD0",
+ "EventName": "L1I_CACHE_ERR",
+ "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
},
- {,
- "EventCode": "0xD1",
- "EventName": "L1D_CACHE_ERR",
- "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+ {
+ "EventCode": "0xD1",
+ "EventName": "L1D_CACHE_ERR",
+ "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
},
- {,
- "EventCode": "0xD2",
- "EventName": "TLB_ERR",
- "BriefDescription": "TLB memory error"
+ {
+ "EventCode": "0xD2",
+ "EventName": "TLB_ERR",
+ "BriefDescription": "TLB memory error"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
index 3149fb90555a..f45a6b5d0025 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
@@ -1,50 +1,50 @@
[
- {,
+ {
"EventCode": "0xC7",
"EventName": "STALL_SB_FULL",
"BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
},
- {,
+ {
"EventCode": "0xE0",
"EventName": "OTHER_IQ_DEP_STALL",
"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
},
- {,
+ {
"EventCode": "0xE1",
"EventName": "IC_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
},
- {,
+ {
"EventCode": "0xE2",
"EventName": "IUTLB_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
},
- {,
+ {
"EventCode": "0xE3",
"EventName": "DECODE_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
},
- {,
+ {
"EventCode": "0xE4",
"EventName": "OTHER_INTERLOCK_STALL",
"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
},
- {,
+ {
"EventCode": "0xE5",
"EventName": "AGU_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
},
- {,
+ {
"EventCode": "0xE6",
"EventName": "SIMD_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
},
- {,
+ {
"EventCode": "0xE7",
"EventName": "LD_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
},
- {,
+ {
"EventCode": "0xE8",
"EventName": "ST_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 21/31] perf vendor events arm64: add HiSilicon hip08 JSON file
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (9 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 20/31] perf vendor events arm64: fixup A53 " Arnaldo Carvalho de Melo
@ 2018-03-13 12:04 ` Arnaldo Carvalho de Melo
2018-03-13 12:05 ` [PATCH 24/31] perf vendor events arm64: Enable JSON events for ThunderX2 B0 Arnaldo Carvalho de Melo
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:04 UTC (permalink / raw)
To: linux-arm-kernel
From: John Garry <john.garry@huawei.com>
This patch adds the HiSilicon hip08 JSON file. This platform follows the
ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable.
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linuxarm at huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-12-git-send-email-john.garry at huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 +++++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
2 files changed, 123 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
new file mode 100644
index 000000000000..9f0f15d15f75
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
@@ -0,0 +1,122 @@
+[
+ {
+ "ArchStdEvent": "L1D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache prefetch access count",
+ "EventCode": "0x102e",
+ "EventName": "L1I_CACHE_PRF",
+ "BriefDescription": "L1I cache prefetch access count",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
+ "EventCode": "0x102f",
+ "EventName": "L1I_CACHE_PRF_REFILL",
+ "BriefDescription": "L1I cache miss due to prefetch access count",
+ },
+ {
+ "PublicDescription": "Instruction queue is empty",
+ "EventCode": "0x1043",
+ "EventName": "IQ_IS_EMPTY",
+ "BriefDescription": "Instruction queue is empty",
+ },
+ {
+ "PublicDescription": "Instruction fetch stall cycles",
+ "EventCode": "0x1044",
+ "EventName": "IF_IS_STALL",
+ "BriefDescription": "Instruction fetch stall cycles",
+ },
+ {
+ "PublicDescription": "Instructions can receive, but not send",
+ "EventCode": "0x2014",
+ "EventName": "FETCH_BUBBLE",
+ "BriefDescription": "Instructions can receive, but not send",
+ },
+ {
+ "PublicDescription": "Prefetch request from LSU",
+ "EventCode": "0x6013",
+ "EventName": "PRF_REQ",
+ "BriefDescription": "Prefetch request from LSU",
+ },
+ {
+ "PublicDescription": "Hit on prefetched data",
+ "EventCode": "0x6014",
+ "EventName": "HIT_ON_PRF",
+ "BriefDescription": "Hit on prefetched data",
+ },
+ {
+ "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
+ "EventCode": "0x7001",
+ "EventName": "EXE_STALL_CYCLE",
+ "BriefDescription": "Cycles of that the number of issue ups are less than 4",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ "EventCode": "0x7004",
+ "EventName": "MEM_STALL_ANYLOAD",
+ "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ "EventCode": "0x7006",
+ "EventName": "MEM_STALL_L1MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ "EventCode": "0x7007",
+ "EventName": "MEM_STALL_L2MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index cf14e23b6404..8f11aeb003a9 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -14,3 +14,4 @@
#Family-model,Version,Filename,EventType
0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
+0x00000000480fd010,v1,hisilicon/hip08,core
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 24/31] perf vendor events arm64: Enable JSON events for ThunderX2 B0
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (10 preceding siblings ...)
2018-03-13 12:04 ` [PATCH 21/31] perf vendor events arm64: add HiSilicon hip08 JSON file Arnaldo Carvalho de Melo
@ 2018-03-13 12:05 ` Arnaldo Carvalho de Melo
11 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 12:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
There is MIDR change on ThunderX2 B0, adding an entry to mapfile to
enable JSON events for B0.
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ganapatrao Kulkarni <gpkulkarni@gklkml16.com>
Cc: Jayachandran C <jnair@caviumnetworks.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert Richter <robert.richter@cavium.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/20180307110803.32418-1-ganapatrao.kulkarni at cavium.com
[ Fixup wrt recent patchset by John Garry ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 8f11aeb003a9..f03e26ecb658 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -14,4 +14,5 @@
#Family-model,Version,Filename,EventType
0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
+0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.14.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 12:04 ` [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json Arnaldo Carvalho de Melo
@ 2018-03-13 14:26 ` Ingo Molnar
2018-03-13 14:34 ` John Garry
` (2 more replies)
0 siblings, 3 replies; 22+ messages in thread
From: Ingo Molnar @ 2018-03-13 14:26 UTC (permalink / raw)
To: linux-arm-kernel
* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> From: John Garry <john.garry@huawei.com>
>
> Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
>
> The JSON is copied from ARMv8 architecture reference manual, available
> here:
>
> https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Cc: Andi Kleen <ak@linux.intel.com>
> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> Cc: Jiri Olsa <jolsa@redhat.com>
> Cc: Namhyung Kim <namhyung@kernel.org>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: William Cohen <wcohen@redhat.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linuxarm at huawei.com
> Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.com
> Signed-off-by: John Garry <john.garry@huawei.com>
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
That's not a valid SOB chain, author != first-Signed-off-by.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 14:26 ` Ingo Molnar
@ 2018-03-13 14:34 ` John Garry
2018-03-13 15:08 ` Ingo Molnar
2018-03-13 15:22 ` Arnaldo Carvalho de Melo
2018-03-13 18:27 ` Arnaldo Carvalho de Melo
2 siblings, 1 reply; 22+ messages in thread
From: John Garry @ 2018-03-13 14:34 UTC (permalink / raw)
To: linux-arm-kernel
On 13/03/2018 14:26, Ingo Molnar wrote:
>
> * Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
>
>> From: John Garry <john.garry@huawei.com>
>>
>> Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
>>
>> The JSON is copied from ARMv8 architecture reference manual, available
>> here:
>>
>> https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
>>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
>> Cc: Andi Kleen <ak@linux.intel.com>
>> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>> Cc: Jiri Olsa <jolsa@redhat.com>
>> Cc: Namhyung Kim <namhyung@kernel.org>
>> Cc: Peter Zijlstra <peterz@infradead.org>
>> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: William Cohen <wcohen@redhat.com>
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: linuxarm at huawei.com
>> Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.com
>> Signed-off-by: John Garry <john.garry@huawei.com>
>> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> That's not a valid SOB chain, author != first-Signed-off-by.
>
Right, so my SOB can go first.
Let me know how to help remedy.
Thanks,
John
> Thanks,
>
> Ingo
>
> .
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 14:34 ` John Garry
@ 2018-03-13 15:08 ` Ingo Molnar
2018-03-13 15:23 ` Arnaldo Carvalho de Melo
2018-03-13 15:27 ` John Garry
0 siblings, 2 replies; 22+ messages in thread
From: Ingo Molnar @ 2018-03-13 15:08 UTC (permalink / raw)
To: linux-arm-kernel
* John Garry <john.garry@huawei.com> wrote:
> On 13/03/2018 14:26, Ingo Molnar wrote:
> >
> > * Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> >
> > > From: John Garry <john.garry@huawei.com>
> > >
> > > Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
> > >
> > > The JSON is copied from ARMv8 architecture reference manual, available
> > > here:
> > >
> > > https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
> > >
> > > Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> > > Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> > > Cc: Andi Kleen <ak@linux.intel.com>
> > > Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> > > Cc: Jiri Olsa <jolsa@redhat.com>
> > > Cc: Namhyung Kim <namhyung@kernel.org>
> > > Cc: Peter Zijlstra <peterz@infradead.org>
> > > Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> > > Cc: Will Deacon <will.deacon@arm.com>
> > > Cc: William Cohen <wcohen@redhat.com>
> > > Cc: linux-arm-kernel at lists.infradead.org
> > > Cc: linuxarm at huawei.com
> > > Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.com
> > > Signed-off-by: John Garry <john.garry@huawei.com>
> > > Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> >
> > That's not a valid SOB chain, author != first-Signed-off-by.
> >
>
> Right, so my SOB can go first.
>
> Let me know how to help remedy.
Well, it depends on what role Shaokun Zhang had in the creation of the patch: if
he co-authored the patch and you finished it then you can add him as:
Originally-from: Shaokun Zhang <zhangshaokun@hisilicon.com>
or if he tested/reviewed the patch then his entry should be Reviewed-by/Acked-by
or Tested-by.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 14:26 ` Ingo Molnar
2018-03-13 14:34 ` John Garry
@ 2018-03-13 15:22 ` Arnaldo Carvalho de Melo
2018-03-13 18:27 ` Arnaldo Carvalho de Melo
2 siblings, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 15:22 UTC (permalink / raw)
To: linux-arm-kernel
Em Tue, Mar 13, 2018 at 03:26:18PM +0100, Ingo Molnar escreveu:
>
> * Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
>
> > From: John Garry <john.garry@huawei.com>
> >
> > Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
> >
> > The JSON is copied from ARMv8 architecture reference manual, available
> > here:
> >
> > https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
> >
> > Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> > Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> > Cc: Andi Kleen <ak@linux.intel.com>
> > Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> > Cc: Jiri Olsa <jolsa@redhat.com>
> > Cc: Namhyung Kim <namhyung@kernel.org>
> > Cc: Peter Zijlstra <peterz@infradead.org>
> > Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: William Cohen <wcohen@redhat.com>
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: linuxarm at huawei.com
> > Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.com
> > Signed-off-by: John Garry <john.garry@huawei.com>
> > Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> That's not a valid SOB chain, author != first-Signed-off-by.
Ok, I'll fix that.
- Arnaldo
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 15:08 ` Ingo Molnar
@ 2018-03-13 15:23 ` Arnaldo Carvalho de Melo
2018-03-13 15:27 ` John Garry
1 sibling, 0 replies; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 15:23 UTC (permalink / raw)
To: linux-arm-kernel
Em Tue, Mar 13, 2018 at 04:08:38PM +0100, Ingo Molnar escreveu:
>
> * John Garry <john.garry@huawei.com> wrote:
>
> > On 13/03/2018 14:26, Ingo Molnar wrote:
> > >
> > > * Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> > >
> > > > From: John Garry <john.garry@huawei.com>
> > > >
> > > > Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
> > > >
> > > > The JSON is copied from ARMv8 architecture reference manual, available
> > > > here:
> > > >
> > > > https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
> > > >
> > > > Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> > > > Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> > > > Cc: Andi Kleen <ak@linux.intel.com>
> > > > Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> > > > Cc: Jiri Olsa <jolsa@redhat.com>
> > > > Cc: Namhyung Kim <namhyung@kernel.org>
> > > > Cc: Peter Zijlstra <peterz@infradead.org>
> > > > Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> > > > Cc: Will Deacon <will.deacon@arm.com>
> > > > Cc: William Cohen <wcohen@redhat.com>
> > > > Cc: linux-arm-kernel at lists.infradead.org
> > > > Cc: linuxarm at huawei.com
> > > > Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.com
> > > > Signed-off-by: John Garry <john.garry@huawei.com>
> > > > Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> > >
> > > That's not a valid SOB chain, author != first-Signed-off-by.
> > >
> >
> > Right, so my SOB can go first.
> >
> > Let me know how to help remedy.
>
> Well, it depends on what role Shaokun Zhang had in the creation of the patch: if
> he co-authored the patch and you finished it then you can add him as:
>
> Originally-from: Shaokun Zhang <zhangshaokun@hisilicon.com>
>
> or if he tested/reviewed the patch then his entry should be Reviewed-by/Acked-by
> or Tested-by.
yeah, please clarify what his role was and I'll do the necessary
changes, in addition to adding more code to my pre-commit scripts,
something long overdue...
- Arnaldo
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 15:08 ` Ingo Molnar
2018-03-13 15:23 ` Arnaldo Carvalho de Melo
@ 2018-03-13 15:27 ` John Garry
1 sibling, 0 replies; 22+ messages in thread
From: John Garry @ 2018-03-13 15:27 UTC (permalink / raw)
To: linux-arm-kernel
On 13/03/2018 15:08, Ingo Molnar wrote:
>
> * John Garry <john.garry@huawei.com> wrote:
>
>> On 13/03/2018 14:26, Ingo Molnar wrote:
>>>
>>> * Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
>>>
>>>> From: John Garry <john.garry@huawei.com>
>>>>
>>>> Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
>>>>
>>>> The JSON is copied from ARMv8 architecture reference manual, available
>>>> here:
>>>>
>>>> https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
>>>>
>>>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Originally-from: Shaokun Zhang <zhangshaokun@hisilicon.com>
>>>> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
>>>> Cc: Andi Kleen <ak@linux.intel.com>
>>>> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>>>> Cc: Jiri Olsa <jolsa@redhat.com>
>>>> Cc: Namhyung Kim <namhyung@kernel.org>
>>>> Cc: Peter Zijlstra <peterz@infradead.org>
>>>> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
>>>> Cc: Will Deacon <will.deacon@arm.com>
>>>> Cc: William Cohen <wcohen@redhat.com>
>>>> Cc: linux-arm-kernel at lists.infradead.org
>>>> Cc: linuxarm at huawei.com
>>>> Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.com
>>>> Signed-off-by: John Garry <john.garry@huawei.com>
>>>> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>>>
>>> That's not a valid SOB chain, author != first-Signed-off-by.
>>>
>>
>> Right, so my SOB can go first.
>>
>> Let me know how to help remedy.
>
> Well, it depends on what role Shaokun Zhang had in the creation of the patch: if
> he co-authored the patch and you finished it then you can add him as:
>
> Originally-from: Shaokun Zhang <zhangshaokun@hisilicon.com>
>
> or if he tested/reviewed the patch then his entry should be Reviewed-by/Acked-by
> or Tested-by.
>
Hi Ingo, Arnaldo,
I think it would be fair to say the former, that is: "he co-authored the
patch and you finished it".
Thanks,
John
> Thanks,
>
> Ingo
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 14:26 ` Ingo Molnar
2018-03-13 14:34 ` John Garry
2018-03-13 15:22 ` Arnaldo Carvalho de Melo
@ 2018-03-13 18:27 ` Arnaldo Carvalho de Melo
2018-03-14 1:54 ` Arnaldo Carvalho de Melo
2 siblings, 1 reply; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-13 18:27 UTC (permalink / raw)
To: linux-arm-kernel
Em Tue, Mar 13, 2018 at 03:26:18PM +0100, Ingo Molnar escreveu:
> * Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> > From: John Garry <john.garry@huawei.com>
> > Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
> > The JSON is copied from ARMv8 architecture reference manual, available
> > here:
> > https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
> > Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> > Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> > Cc: Andi Kleen <ak@linux.intel.com>
> > Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> > Cc: Jiri Olsa <jolsa@redhat.com>
> > Cc: Namhyung Kim <namhyung@kernel.org>
> > Cc: Peter Zijlstra <peterz@infradead.org>
> > Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: William Cohen <wcohen@redhat.com>
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: linuxarm at huawei.com
> > Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.com
> > Signed-off-by: John Garry <john.garry@huawei.com>
> > Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> That's not a valid SOB chain, author != first-Signed-off-by.
I removed that cset for now, can you please check if the
perf-core-for-mingo-4.17-20180313-2 tag is allright?
- Arnaldo
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-13 18:27 ` Arnaldo Carvalho de Melo
@ 2018-03-14 1:54 ` Arnaldo Carvalho de Melo
2018-03-14 7:17 ` Ingo Molnar
0 siblings, 1 reply; 22+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-14 1:54 UTC (permalink / raw)
To: linux-arm-kernel
Em Tue, Mar 13, 2018 at 03:27:30PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Tue, Mar 13, 2018 at 03:26:18PM +0100, Ingo Molnar escreveu:
> > That's not a valid SOB chain, author != first-Signed-off-by.
> I removed that cset for now, can you please check if the
> perf-core-for-mingo-4.17-20180313-2 tag is allright?
So, since there is this problem with powerpc and jevents, Ingo, please
hold on a bit more... Hopefully tomorrow things will be in a better
shape.
- Arnaldo
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
2018-03-14 1:54 ` Arnaldo Carvalho de Melo
@ 2018-03-14 7:17 ` Ingo Molnar
0 siblings, 0 replies; 22+ messages in thread
From: Ingo Molnar @ 2018-03-14 7:17 UTC (permalink / raw)
To: linux-arm-kernel
* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> Em Tue, Mar 13, 2018 at 03:27:30PM -0300, Arnaldo Carvalho de Melo escreveu:
> > Em Tue, Mar 13, 2018 at 03:26:18PM +0100, Ingo Molnar escreveu:
> > > That's not a valid SOB chain, author != first-Signed-off-by.
>
> > I removed that cset for now, can you please check if the
> > perf-core-for-mingo-4.17-20180313-2 tag is allright?
>
> So, since there is this problem with powerpc and jevents, Ingo, please
> hold on a bit more... Hopefully tomorrow things will be in a better
> shape.
Sure, no problem!
Thanks,
Ingo
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2018-03-14 7:17 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-13 12:04 [GIT PULL 00/31] perf/core improvements and fixes Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 11/31] perf vendor events: Drop incomplete multiple mapfile support Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 12/31] perf vendor events: Fix error code in json_events() Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 13/31] perf vendor events: Drop support for unused topic directories Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 14/31] perf vendor events: Add support for pmu events vendor subdirectory Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 15/31] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 16/31] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 17/31] perf vendor events: Add support for arch standard events Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json Arnaldo Carvalho de Melo
2018-03-13 14:26 ` Ingo Molnar
2018-03-13 14:34 ` John Garry
2018-03-13 15:08 ` Ingo Molnar
2018-03-13 15:23 ` Arnaldo Carvalho de Melo
2018-03-13 15:27 ` John Garry
2018-03-13 15:22 ` Arnaldo Carvalho de Melo
2018-03-13 18:27 ` Arnaldo Carvalho de Melo
2018-03-14 1:54 ` Arnaldo Carvalho de Melo
2018-03-14 7:17 ` Ingo Molnar
2018-03-13 12:04 ` [PATCH 19/31] perf vendor events arm64: Fixup ThunderX2 to use recommended events Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 20/31] perf vendor events arm64: fixup A53 " Arnaldo Carvalho de Melo
2018-03-13 12:04 ` [PATCH 21/31] perf vendor events arm64: add HiSilicon hip08 JSON file Arnaldo Carvalho de Melo
2018-03-13 12:05 ` [PATCH 24/31] perf vendor events arm64: Enable JSON events for ThunderX2 B0 Arnaldo Carvalho de Melo
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