* [PATCH] clk: sunxi-ng: h3: Allow parent change for ve clock
@ 2018-12-03 19:58 Jernej Skrabec
2018-12-04 7:44 ` Maxime Ripard
0 siblings, 1 reply; 2+ messages in thread
From: Jernej Skrabec @ 2018-12-03 19:58 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: sboyd, mturquette, linux-kernel, linux-sunxi, linux-clk,
linux-arm-kernel
Cedrus driver wants to set VE clock higher than it's possible without
changing parent rate.
In order to correct that, allow changing parent rate for VE clock.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index eb5c608428fa..e52155770f39 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -481,7 +481,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
- 0x13c, 16, 3, BIT(31), 0);
+ 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
--
2.19.2
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* Re: [PATCH] clk: sunxi-ng: h3: Allow parent change for ve clock
2018-12-03 19:58 [PATCH] clk: sunxi-ng: h3: Allow parent change for ve clock Jernej Skrabec
@ 2018-12-04 7:44 ` Maxime Ripard
0 siblings, 0 replies; 2+ messages in thread
From: Maxime Ripard @ 2018-12-04 7:44 UTC (permalink / raw)
To: Jernej Skrabec
Cc: sboyd, mturquette, linux-sunxi, linux-kernel, wens, linux-clk,
linux-arm-kernel
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On Mon, Dec 03, 2018 at 08:58:56PM +0100, Jernej Skrabec wrote:
> Cedrus driver wants to set VE clock higher than it's possible without
> changing parent rate.
>
> In order to correct that, allow changing parent rate for VE clock.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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2018-12-04 7:44 ` Maxime Ripard
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