From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Joseph Lo <josephl@nvidia.com>
Subject: [PATCH 13/19] arm64: dts: tegra210: add DFLL clock
Date: Tue, 4 Dec 2018 17:25:42 +0800 [thread overview]
Message-ID: <20181204092548.3038-14-josephl@nvidia.com> (raw)
In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com>
Add essential DFLL clock properties for Tegra210.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 2205d66b0443..a6db62157442 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
+#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
@@ -1131,6 +1132,24 @@
#nvidia,mipi-calibrate-cells = <1>;
};
+ dfll: clock@70110000 {
+ compatible = "nvidia,tegra210-dfll";
+ reg = <0 0x70110000 0 0x100>, /* DFLL control */
+ <0 0x70110000 0 0x100>, /* I2C output control */
+ <0 0x70110100 0 0x100>, /* Integrated I2C controller */
+ <0 0x70110200 0 0x100>; /* Look-up table RAM */
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA210_CLK_DFLL_REF>,
+ <&tegra_car TEGRA210_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
+ reset-names = "dvco";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ status = "disabled";
+ };
+
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
--
2.19.2
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next prev parent reply other threads:[~2018-12-04 9:43 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-04 9:25 [PATCH 00/19] Tegra210 DFLL support Joseph Lo
2018-12-04 9:25 ` [PATCH 01/19] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-07 13:41 ` Jon Hunter
2018-12-10 8:49 ` Joseph Lo
2018-12-10 8:59 ` Jon Hunter
2018-12-10 9:31 ` Joseph Lo
2018-12-10 9:44 ` Jon Hunter
2018-12-11 1:28 ` Joseph Lo
2018-12-11 9:16 ` Peter De Schrijver
2018-12-11 9:36 ` Joseph Lo
2018-12-11 9:15 ` Peter De Schrijver
2018-12-11 11:52 ` Jon Hunter
2018-12-12 1:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 02/19] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-07 13:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 03/19] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-04 15:36 ` Peter De Schrijver
2018-12-05 3:05 ` Joseph Lo
2018-12-05 9:37 ` Peter De Schrijver
2018-12-07 13:52 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 04/19] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-04 15:37 ` Peter De Schrijver
2018-12-05 3:10 ` Joseph Lo
2018-12-07 13:53 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 05/19] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-07 13:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 06/19] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-07 14:10 ` Jon Hunter
2018-12-11 6:23 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 07/19] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-04 15:53 ` Peter De Schrijver
2018-12-05 6:14 ` Joseph Lo
2018-12-07 14:26 ` Jon Hunter
2018-12-11 6:36 ` Joseph Lo
2018-12-07 15:09 ` Jon Hunter
2018-12-11 6:37 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 08/19] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-04 15:46 ` Peter De Schrijver
2018-12-05 6:20 ` Joseph Lo
2018-12-05 6:51 ` Joseph Lo
2018-12-05 9:11 ` Peter De Schrijver
2018-12-05 9:30 ` Joseph Lo
2018-12-07 14:34 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 09/19] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-07 14:39 ` Jon Hunter
2018-12-11 7:34 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 10/19] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-07 14:40 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 11/19] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-07 14:49 ` Jon Hunter
2018-12-11 8:48 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 12/19] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-04 9:30 ` Viresh Kumar
2018-12-04 11:22 ` Dmitry Osipenko
2018-12-05 3:25 ` Joseph Lo
2018-12-07 14:50 ` Jon Hunter
2018-12-04 9:25 ` Joseph Lo [this message]
2018-12-07 14:54 ` [PATCH 13/19] arm64: dts: tegra210: add DFLL clock Jon Hunter
2018-12-04 9:25 ` [PATCH 14/19] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 15/19] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-07 14:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-07 14:57 ` Jon Hunter
2018-12-11 8:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 17/19] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 18/19] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 19/19] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2018-12-07 15:04 ` Jon Hunter
2018-12-04 15:10 ` [PATCH 00/19] Tegra210 DFLL support Thierry Reding
2018-12-05 6:11 ` Joseph Lo
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