From: Jon Hunter <jonathanh@nvidia.com>
To: Joseph Lo <josephl@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 07/19] clk: tegra: dfll: support PWM regulator control
Date: Fri, 7 Dec 2018 15:09:10 +0000 [thread overview]
Message-ID: <3d0f52c6-770e-bae2-2396-87f32455b807@nvidia.com> (raw)
In-Reply-To: <20181204092548.3038-8-josephl@nvidia.com>
On 04/12/2018 09:25, Joseph Lo wrote:
> The DFLL hardware supports two modes (I2C and PWM) for voltage control
> when requesting a frequency. In this patch, we introduce PWM mode support.
>
> To support that, we re-organize the LUT for unifying the table for both
> cases of I2C and PWM mode. And generate that based on regulator info.
> For the PWM-based regulator, we get this info from DT. And do the same as
> the case of I2C LUT, which can help to map the PMIC voltage ID and voltages
> that the regulator supported.
>
> The other parts are the support code for initializing the DFLL hardware
> to support PWM mode. Also, the register debugfs file is slightly
> reworked to only show the i2c registers when I2C mode is in use.
>
> Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.
>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> drivers/clk/tegra/clk-dfll.c | 431 ++++++++++++++++++++++++++++++-----
> 1 file changed, 368 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
> index 609e363dabf8..c294a2989f31 100644
> --- a/drivers/clk/tegra/clk-dfll.c
> +++ b/drivers/clk/tegra/clk-dfll.c
> @@ -1,7 +1,7 @@
> /*
> * clk-dfll.c - Tegra DFLL clock source common code
> *
> - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
> + * Copyright (C) 2012-2018 NVIDIA Corporation. All rights reserved.
> *
> * Aleksandr Frid <afrid@nvidia.com>
> * Paul Walmsley <pwalmsley@nvidia.com>
> @@ -47,6 +47,7 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/pinctrl/consumer.h>
> #include <linux/pm_opp.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> @@ -243,6 +244,12 @@ enum dfll_tune_range {
> DFLL_TUNE_LOW = 1,
> };
>
> +
> +enum tegra_dfll_pmu_if {
> + TEGRA_DFLL_PMU_I2C = 0,
> + TEGRA_DFLL_PMU_PWM = 1,
> +};
> +
> /**
> * struct dfll_rate_req - target DFLL rate request data
> * @rate: target frequency, after the postscaling
> @@ -294,16 +301,25 @@ struct tegra_dfll {
> u32 ci;
> u32 cg;
> bool cg_scale;
> + u32 reg_init_uV;
>
> /* I2C interface parameters */
> u32 i2c_fs_rate;
> u32 i2c_reg;
> u32 i2c_slave_addr;
>
> - /* i2c_lut array entries are regulator framework selectors */
> - unsigned i2c_lut[MAX_DFLL_VOLTAGES];
> - int i2c_lut_size;
> - u8 lut_min, lut_max, lut_safe;
> + /* lut array entries are regulator framework selectors or PWM values*/
> + unsigned lut[MAX_DFLL_VOLTAGES];
> + unsigned lut_uv[MAX_DFLL_VOLTAGES];
> + int lut_size;
> + u8 lut_bottom, lut_min, lut_max, lut_safe;
> +
> + /* PWM interface */
> + enum tegra_dfll_pmu_if pmu_if;
> + unsigned long pwm_rate;
> + struct pinctrl *pwm_pin;
> + struct pinctrl_state *pwm_enable_state;
> + struct pinctrl_state *pwm_disable_state;
> };
>
> #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)
> @@ -489,6 +505,34 @@ static void dfll_set_mode(struct tegra_dfll *td,
> dfll_wmb(td);
> }
>
> +/*
> + * DVCO rate control
> + */
> +
> +static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min)
> +{
> + struct dev_pm_opp *opp;
> + unsigned long rate, prev_rate;
> + int uv, min_uv;
> +
> + min_uv = td->lut_uv[out_min];
> + for (rate = 0, prev_rate = 0; ; rate++) {
> + opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
> + if (IS_ERR(opp))
> + break;
> +
> + uv = dev_pm_opp_get_voltage(opp);
Can you fix the type of 'uv' here? It should be unsigned long.
Cheers
Jon
--
nvpublic
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next prev parent reply other threads:[~2018-12-07 15:09 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-04 9:25 [PATCH 00/19] Tegra210 DFLL support Joseph Lo
2018-12-04 9:25 ` [PATCH 01/19] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-07 13:41 ` Jon Hunter
2018-12-10 8:49 ` Joseph Lo
2018-12-10 8:59 ` Jon Hunter
2018-12-10 9:31 ` Joseph Lo
2018-12-10 9:44 ` Jon Hunter
2018-12-11 1:28 ` Joseph Lo
2018-12-11 9:16 ` Peter De Schrijver
2018-12-11 9:36 ` Joseph Lo
2018-12-11 9:15 ` Peter De Schrijver
2018-12-11 11:52 ` Jon Hunter
2018-12-12 1:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 02/19] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-07 13:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 03/19] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-04 15:36 ` Peter De Schrijver
2018-12-05 3:05 ` Joseph Lo
2018-12-05 9:37 ` Peter De Schrijver
2018-12-07 13:52 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 04/19] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-04 15:37 ` Peter De Schrijver
2018-12-05 3:10 ` Joseph Lo
2018-12-07 13:53 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 05/19] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-07 13:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 06/19] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-07 14:10 ` Jon Hunter
2018-12-11 6:23 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 07/19] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-04 15:53 ` Peter De Schrijver
2018-12-05 6:14 ` Joseph Lo
2018-12-07 14:26 ` Jon Hunter
2018-12-11 6:36 ` Joseph Lo
2018-12-07 15:09 ` Jon Hunter [this message]
2018-12-11 6:37 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 08/19] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-04 15:46 ` Peter De Schrijver
2018-12-05 6:20 ` Joseph Lo
2018-12-05 6:51 ` Joseph Lo
2018-12-05 9:11 ` Peter De Schrijver
2018-12-05 9:30 ` Joseph Lo
2018-12-07 14:34 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 09/19] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-07 14:39 ` Jon Hunter
2018-12-11 7:34 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 10/19] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-07 14:40 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 11/19] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-07 14:49 ` Jon Hunter
2018-12-11 8:48 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 12/19] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-04 9:30 ` Viresh Kumar
2018-12-04 11:22 ` Dmitry Osipenko
2018-12-05 3:25 ` Joseph Lo
2018-12-07 14:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 13/19] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 14/19] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 15/19] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-07 14:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-07 14:57 ` Jon Hunter
2018-12-11 8:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 17/19] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 18/19] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 19/19] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2018-12-07 15:04 ` Jon Hunter
2018-12-04 15:10 ` [PATCH 00/19] Tegra210 DFLL support Thierry Reding
2018-12-05 6:11 ` Joseph Lo
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