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From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-pm@vger.kernel.org, Viresh Kumar <viresh.kumar@linaro.org>,
	Joseph Lo <josephl@nvidia.com>,
	linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH V3 11/20] cpufreq: tegra124: do not handle the CPU rail
Date: Tue, 18 Dec 2018 17:12:23 +0800	[thread overview]
Message-ID: <20181218091232.23532-12-josephl@nvidia.com> (raw)
In-Reply-To: <20181218091232.23532-1-josephl@nvidia.com>

The Tegra124 cpufreq driver has no information to handle the Vdd-CPU
rail. So this driver shouldn't handle for the CPU clock switching from
DFLL to other PLL clocks. It was designed to work on DFLL clock only,
which handle the frequency/voltage scaling in the background.

This patch removes the driver dependency of the CPU rail, as well as not
allow it to be built as a module and remove the removal function. So it
can keep working on DFLL clock.

Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
*V3:
 - add ack tags
*V2:
 - update the commit message since we change the driver not able to be
 built as a module and remove the removal function in V2
---
 drivers/cpufreq/Kconfig.arm        |  4 +--
 drivers/cpufreq/tegra124-cpufreq.c | 41 ++----------------------------
 2 files changed, 4 insertions(+), 41 deletions(-)

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 688f10227793..1a6778e81f90 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -272,8 +272,8 @@ config ARM_TEGRA20_CPUFREQ
 	  This adds the CPUFreq driver support for Tegra20 SOCs.
 
 config ARM_TEGRA124_CPUFREQ
-	tristate "Tegra124 CPUFreq support"
-	depends on ARCH_TEGRA && CPUFREQ_DT && REGULATOR
+	bool "Tegra124 CPUFreq support"
+	depends on ARCH_TEGRA && CPUFREQ_DT
 	default y
 	help
 	  This adds the CPUFreq driver support for Tegra124 SOCs.
diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
index 43530254201a..a1bfde0a7950 100644
--- a/drivers/cpufreq/tegra124-cpufreq.c
+++ b/drivers/cpufreq/tegra124-cpufreq.c
@@ -22,11 +22,9 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_opp.h>
-#include <linux/regulator/consumer.h>
 #include <linux/types.h>
 
 struct tegra124_cpufreq_priv {
-	struct regulator *vdd_cpu_reg;
 	struct clk *cpu_clk;
 	struct clk *pllp_clk;
 	struct clk *pllx_clk;
@@ -60,14 +58,6 @@ static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv)
 	return ret;
 }
 
-static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv)
-{
-	clk_set_parent(priv->cpu_clk, priv->pllp_clk);
-	clk_disable_unprepare(priv->dfll_clk);
-	regulator_sync_voltage(priv->vdd_cpu_reg);
-	clk_set_parent(priv->cpu_clk, priv->pllx_clk);
-}
-
 static int tegra124_cpufreq_probe(struct platform_device *pdev)
 {
 	struct tegra124_cpufreq_priv *priv;
@@ -88,16 +78,10 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
 	if (!np)
 		return -ENODEV;
 
-	priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu");
-	if (IS_ERR(priv->vdd_cpu_reg)) {
-		ret = PTR_ERR(priv->vdd_cpu_reg);
-		goto out_put_np;
-	}
-
 	priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
 	if (IS_ERR(priv->cpu_clk)) {
 		ret = PTR_ERR(priv->cpu_clk);
-		goto out_put_vdd_cpu_reg;
+		goto out_put_np;
 	}
 
 	priv->dfll_clk = of_clk_get_by_name(np, "dfll");
@@ -129,15 +113,13 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
 		platform_device_register_full(&cpufreq_dt_devinfo);
 	if (IS_ERR(priv->cpufreq_dt_pdev)) {
 		ret = PTR_ERR(priv->cpufreq_dt_pdev);
-		goto out_switch_to_pllx;
+		goto out_put_pllp_clk;
 	}
 
 	platform_set_drvdata(pdev, priv);
 
 	return 0;
 
-out_switch_to_pllx:
-	tegra124_cpu_switch_to_pllx(priv);
 out_put_pllp_clk:
 	clk_put(priv->pllp_clk);
 out_put_pllx_clk:
@@ -146,34 +128,15 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
 	clk_put(priv->dfll_clk);
 out_put_cpu_clk:
 	clk_put(priv->cpu_clk);
-out_put_vdd_cpu_reg:
-	regulator_put(priv->vdd_cpu_reg);
 out_put_np:
 	of_node_put(np);
 
 	return ret;
 }
 
-static int tegra124_cpufreq_remove(struct platform_device *pdev)
-{
-	struct tegra124_cpufreq_priv *priv = platform_get_drvdata(pdev);
-
-	platform_device_unregister(priv->cpufreq_dt_pdev);
-	tegra124_cpu_switch_to_pllx(priv);
-
-	clk_put(priv->pllp_clk);
-	clk_put(priv->pllx_clk);
-	clk_put(priv->dfll_clk);
-	clk_put(priv->cpu_clk);
-	regulator_put(priv->vdd_cpu_reg);
-
-	return 0;
-}
-
 static struct platform_driver tegra124_cpufreq_platdrv = {
 	.driver.name	= "cpufreq-tegra124",
 	.probe		= tegra124_cpufreq_probe,
-	.remove		= tegra124_cpufreq_remove,
 };
 
 static int __init tegra_cpufreq_init(void)
-- 
2.20.1


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  parent reply	other threads:[~2018-12-18  9:16 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-18  9:12 [PATCH V3 00/20] Tegra210 DFLL support Joseph Lo
2018-12-18  9:12 ` [PATCH V3 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-18  9:56   ` Jon Hunter
2018-12-18 15:19   ` Rob Herring
2018-12-19  7:04     ` Joseph Lo
2018-12-18  9:12 ` [PATCH V3 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-18 15:44   ` Rob Herring
2018-12-18 18:02   ` Stephen Boyd
2018-12-18  9:12 ` [PATCH V3 03/20] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-18 15:45   ` Rob Herring
2018-12-18  9:12 ` [PATCH V3 04/20] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-18 15:47   ` Rob Herring
2018-12-18  9:12 ` [PATCH V3 05/20] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-18 18:02   ` Stephen Boyd
2018-12-18  9:12 ` [PATCH V3 06/20] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-18  9:58   ` Jon Hunter
2018-12-18 18:02   ` Stephen Boyd
2018-12-18  9:12 ` [PATCH V3 07/20] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-18 10:00   ` Jon Hunter
2018-12-18 18:41   ` Stephen Boyd
2018-12-18  9:12 ` [PATCH V3 08/20] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-18 10:05   ` Jon Hunter
2018-12-18 18:41   ` Stephen Boyd
2018-12-18  9:12 ` [PATCH V3 09/20] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-18 10:05   ` Jon Hunter
2018-12-18 18:42   ` Stephen Boyd
2018-12-18  9:12 ` [PATCH V3 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-18 18:00   ` Stephen Boyd
2018-12-19  7:08     ` Joseph Lo
2018-12-18  9:12 ` Joseph Lo [this message]
2018-12-18  9:37   ` [PATCH V3 11/20] cpufreq: tegra124: do not handle the CPU rail Rafael J. Wysocki
2018-12-19  6:24     ` Joseph Lo
2018-12-18  9:12 ` [PATCH V3 12/20] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-18  9:12 ` [PATCH V3 13/20] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2018-12-18  9:12 ` [PATCH V3 14/20] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-18  9:12 ` [PATCH V3 15/20] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-18  9:12 ` [PATCH V3 16/20] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-18  9:12 ` [PATCH V3 17/20] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-18  9:12 ` [PATCH V3 18/20] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-18  9:12 ` [PATCH V3 19/20] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-18  9:12 ` [PATCH V3 20/20] arm64: defconfig: Enable MAX8973 regulator Joseph Lo

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