From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Joseph Lo <josephl@nvidia.com>
Subject: [PATCH V3 17/20] arm64: dts: tegra210-p2371-2180: enable DFLL clock
Date: Tue, 18 Dec 2018 17:12:29 +0800 [thread overview]
Message-ID: <20181218091232.23532-18-josephl@nvidia.com> (raw)
In-Reply-To: <20181218091232.23532-1-josephl@nvidia.com>
Enable DFLL clock for Jetson TX1 platform.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
*V3:
- add ack tag
*V2:
- remove non exist DT bindings
- update the PWM DT bindings accordingly
---
.../boot/dts/nvidia/tegra210-p2371-2180.dts | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 37e3c46e753f..99c016bfc601 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -78,4 +78,25 @@
};
};
};
+
+ clock@70110000 {
+ status = "okay";
+
+ nvidia,cf = <6>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,sample-rate = <25000>;
+
+ nvidia,pwm-min-microvolts = <708000>;
+ nvidia,pwm-period = <2500>; /* 2.5us */
+ nvidia,pwm-to-pmic;
+ nvidia,pwm-tristate-microvolts = <1000000>;
+ nvidia,pwm-voltage-step-microvolts = <19200>;
+
+ pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
+ pinctrl-0 = <&dvfs_pwm_active_state>;
+ pinctrl-1 = <&dvfs_pwm_inactive_state>;
+ };
};
--
2.20.1
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next prev parent reply other threads:[~2018-12-18 9:17 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-18 9:12 [PATCH V3 00/20] Tegra210 DFLL support Joseph Lo
2018-12-18 9:12 ` [PATCH V3 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-18 9:56 ` Jon Hunter
2018-12-18 15:19 ` Rob Herring
2018-12-19 7:04 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-18 15:44 ` Rob Herring
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 03/20] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-18 15:45 ` Rob Herring
2018-12-18 9:12 ` [PATCH V3 04/20] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-18 15:47 ` Rob Herring
2018-12-18 9:12 ` [PATCH V3 05/20] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 06/20] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-18 9:58 ` Jon Hunter
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 07/20] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-18 10:00 ` Jon Hunter
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 08/20] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-18 10:05 ` Jon Hunter
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 09/20] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-18 10:05 ` Jon Hunter
2018-12-18 18:42 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-18 18:00 ` Stephen Boyd
2018-12-19 7:08 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 11/20] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-18 9:37 ` Rafael J. Wysocki
2018-12-19 6:24 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 12/20] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-18 9:12 ` [PATCH V3 13/20] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2018-12-18 9:12 ` [PATCH V3 14/20] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-18 9:12 ` [PATCH V3 15/20] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-18 9:12 ` [PATCH V3 16/20] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-18 9:12 ` Joseph Lo [this message]
2018-12-18 9:12 ` [PATCH V3 18/20] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-18 9:12 ` [PATCH V3 19/20] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-18 9:12 ` [PATCH V3 20/20] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
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