[PATCH] clk: at91: optimize clk_round_rate() for AUDIO_PLL

[PATCH] clk: at91: optimize clk_round_rate() for AUDIO_PLL

[Michał Mirosław]

This makes for 3 clk_round_rate() calls instead of 64 of them on
SAMA5D2-based board when searching for 12.288MHz clock.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
---
 drivers/clk/at91/clk-audio-pll.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
index 36d77146a3bd..3a358282784e 100644
--- a/drivers/clk/at91/clk-audio-pll.c
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -340,7 +340,11 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
 	pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
 		 rate, *parent_rate);
 
-	for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) {
+	if (!rate)
+		return 0;
+
+	best_parent_rate = clk_round_rate(pclk->clk, 1);
+	for (div = max(best_parent_rate / rate, 1ul); div <= AUDIO_PLL_QDPMC_MAX; div++) {
 		best_parent_rate = clk_round_rate(pclk->clk, rate * div);
 		tmp_rate = best_parent_rate / div;
 		tmp_diff = abs(rate - tmp_rate);
@@ -350,6 +354,8 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
 			best_rate = tmp_rate;
 			best_diff = tmp_diff;
 			tmp_qd = div;
+			if (!best_diff)
+				break;	/* got exact match */
 		}
 	}
 
-- 
2.19.2


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Re: [PATCH] clk: at91: optimize clk_round_rate() for AUDIO_PLL

[Stephen Boyd]

Quoting Michał Mirosław (2018-12-17 11:37:05)
> This makes for 3 clk_round_rate() calls instead of 64 of them on
> SAMA5D2-based board when searching for 12.288MHz clock.

Ok, but is that better? Worse? Can you more clearly describe what you're
doing here? And it's not breaking some other corner case?

> 
> Signed-off-by: Micha\u0142 Miros\u0142aw <mirq-linux@rere.qmqm.pl>

This got all broken. Something on your end?

> ---
>  drivers/clk/at91/clk-audio-pll.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
> index 36d77146a3bd..3a358282784e 100644
> --- a/drivers/clk/at91/clk-audio-pll.c
> +++ b/drivers/clk/at91/clk-audio-pll.c
> @@ -340,7 +340,11 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
>         pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
>                  rate, *parent_rate);
>  
> -       for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) {
> +       if (!rate)
> +               return 0;
> +
> +       best_parent_rate = clk_round_rate(pclk->clk, 1);
> +       for (div = max(best_parent_rate / rate, 1ul); div <= AUDIO_PLL_QDPMC_MAX; div++) {

Nitpick: Style is usually 1UL instead of lowercase 1ul.

>                 best_parent_rate = clk_round_rate(pclk->clk, rate * div);
>                 tmp_rate = best_parent_rate / div;
>                 tmp_diff = abs(rate - tmp_rate);
> @@ -350,6 +354,8 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
>                         best_rate = tmp_rate;
>                         best_diff = tmp_diff;
>                         tmp_qd = div;
> +                       if (!best_diff)
> +                               break;  /* got exact match */

Seems sensible to break immediately if exact match is found.
`

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Re: [PATCH] clk: at91: optimize clk_round_rate() for AUDIO_PLL

[Michał Mirosław]

On Mon, Dec 17, 2018 at 03:22:50PM -0800, Stephen Boyd wrote:
> Quoting Michał Mirosław (2018-12-17 11:37:05)
> > This makes for 3 clk_round_rate() calls instead of 64 of them on
> > SAMA5D2-based board when searching for 12.288MHz clock.
> Ok, but is that better? Worse? Can you more clearly describe what you're
> doing here? And it's not breaking some other corner case?
> > 
> > Signed-off-by: Micha\u0142 Miros\u0142aw <mirq-linux@rere.qmqm.pl>
> This got all broken. Something on your end?
[...]

linux-clk archives got it right:

https://lore.kernel.org/linux-clk/772b3869cc992d894d8c1b4296f21100bcbed30d.1545075103.git.mirq-linux@rere.qmqm.pl/T/#u

Best Regards,
Michał Mirosław

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Re: [PATCH] clk: at91: optimize clk_round_rate() for AUDIO_PLL

[Uwe Kleine-König]

Hello,

On Mon, Dec 17, 2018 at 03:22:50PM -0800, Stephen Boyd wrote:
> Quoting Michał Mirosław (2018-12-17 11:37:05)
> > This makes for 3 clk_round_rate() calls instead of 64 of them on
> > SAMA5D2-based board when searching for 12.288MHz clock.
> 
> Ok, but is that better? Worse? Can you more clearly describe what you're
> doing here? And it's not breaking some other corner case?

I think there isn't even a policy how clk_round_rate() actually behaves,
is there? If you could rely on it to (say) always round down cases like
these could maybe be handled easier? (But I didn't really look at the
patch, so this might not be one of these cases.)

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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