* [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs.
@ 2019-01-23 9:43 Josef Lusticky
2019-01-23 9:43 ` [PATCH 1/3] ARM: dts: sun5i: Add SPI0 pins Josef Lusticky
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Josef Lusticky @ 2019-01-23 9:43 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: maxime.ripard, wens, Josef Lusticky
This patch series adds SPI pinctrl nodes to sun5i SoCs.
While spi0 is common to all A10s, A13 and GR8 (PATCH 1/3),
spi2 has alternate pins on the PB bank only on A10s (already in sun5i-a10s.dtsi) and GR8 (PATCH 2/3).
The spi1_cs1 is only available on A10s (PATCH 3/3).
The spi1_cs1 is potentially available on GR8 as well
(at least it is specified in drivers/pinctrl/sunxi/pinctrl-sun5i.c),
but I was not able to find it in the datasheet.
The same applies to spi2_cs1.
Both spi1_cs1 and spi2_cs1 can be added later to sun5i-gr8.dtsi.
Josef Lusticky (3):
ARM: dts: sun5i: Add SPI0 pins
ARM: dts: sun5i: GR8: Add SPI2 PB pins
ARM: dts: sun5i: A10s: Add SPI1_CS1 PG13 pin
arch/arm/boot/dts/sun5i-a10s.dtsi | 5 +++++
arch/arm/boot/dts/sun5i-gr8.dtsi | 10 ++++++++++
arch/arm/boot/dts/sun5i.dtsi | 10 ++++++++++
3 files changed, 25 insertions(+)
--
2.20.1
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] ARM: dts: sun5i: Add SPI0 pins
2019-01-23 9:43 [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Josef Lusticky
@ 2019-01-23 9:43 ` Josef Lusticky
2019-01-23 9:43 ` [PATCH 2/3] ARM: dts: sun5i: GR8: Add SPI2 PB pins Josef Lusticky
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Josef Lusticky @ 2019-01-23 9:43 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: maxime.ripard, wens, Josef Lusticky
Add a separate pinctrl nodes for the SPI0 pins shared between
the A10s, A13 and GR8.
Signed-off-by: Josef Lusticky <josef@lusticky.cz>
---
arch/arm/boot/dts/sun5i.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 5497d985c54a..897340ee27c7 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -536,6 +536,16 @@
function = "nand0";
};
+ spi0_pc_pins: spi0-pc-pins {
+ pins = "PC2", "PC0", "PC1";
+ function = "spi0";
+ };
+
+ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
+ pins = "PC3";
+ function = "spi0";
+ };
+
spi2_pe_pins: spi2-pe-pins {
pins = "PE1", "PE2", "PE3";
function = "spi2";
--
2.20.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/3] ARM: dts: sun5i: GR8: Add SPI2 PB pins
2019-01-23 9:43 [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Josef Lusticky
2019-01-23 9:43 ` [PATCH 1/3] ARM: dts: sun5i: Add SPI0 pins Josef Lusticky
@ 2019-01-23 9:43 ` Josef Lusticky
2019-01-23 9:43 ` [PATCH 3/3] ARM: dts: sun5i: A10s: Add SPI1_CS1 PG13 pin Josef Lusticky
2019-01-23 10:36 ` [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Maxime Ripard
3 siblings, 0 replies; 5+ messages in thread
From: Josef Lusticky @ 2019-01-23 9:43 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: maxime.ripard, wens, Josef Lusticky
Add a separate pinctrl nodes for the SPI2 pins on the GR8 PB bank.
Signed-off-by: Josef Lusticky <josef@lusticky.cz>
---
arch/arm/boot/dts/sun5i-gr8.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index 98a8fd5e89e8..a26a6a7d7c6b 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -119,6 +119,16 @@
bias-pull-up;
};
+ spi2_pb_pins: spi2-pb-pins {
+ pins = "PB12", "PB13", "PB14";
+ function = "spi2";
+ };
+
+ spi2_cs0_pb_pin: spi2-cs0-pb-pin {
+ pins = "PB11";
+ function = "spi2";
+ };
+
uart1_cts_rts_pins: uart1-cts-rts-pins {
pins = "PG5", "PG6";
function = "uart1";
--
2.20.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/3] ARM: dts: sun5i: A10s: Add SPI1_CS1 PG13 pin
2019-01-23 9:43 [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Josef Lusticky
2019-01-23 9:43 ` [PATCH 1/3] ARM: dts: sun5i: Add SPI0 pins Josef Lusticky
2019-01-23 9:43 ` [PATCH 2/3] ARM: dts: sun5i: GR8: Add SPI2 PB pins Josef Lusticky
@ 2019-01-23 9:43 ` Josef Lusticky
2019-01-23 10:36 ` [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Maxime Ripard
3 siblings, 0 replies; 5+ messages in thread
From: Josef Lusticky @ 2019-01-23 9:43 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: maxime.ripard, wens, Josef Lusticky
Add a separate pinctrl node for the SPI1_CS1 pin on the A10s PG bank.
Signed-off-by: Josef Lusticky <josef@lusticky.cz>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 09c486b608b2..156fefc045ac 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -153,6 +153,11 @@
drive-strength = <30>;
};
+ spi1_cs1_pg_pin: spi1-cs1-pg-pin {
+ pins = "PG13";
+ function = "spi2";
+ };
+
spi2_pb_pins: spi2-pb-pins {
pins = "PB12", "PB13", "PB14";
function = "spi2";
--
2.20.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs.
2019-01-23 9:43 [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Josef Lusticky
` (2 preceding siblings ...)
2019-01-23 9:43 ` [PATCH 3/3] ARM: dts: sun5i: A10s: Add SPI1_CS1 PG13 pin Josef Lusticky
@ 2019-01-23 10:36 ` Maxime Ripard
3 siblings, 0 replies; 5+ messages in thread
From: Maxime Ripard @ 2019-01-23 10:36 UTC (permalink / raw)
To: Josef Lusticky; +Cc: wens, linux-arm-kernel
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Hi Joseph,
On Wed, Jan 23, 2019 at 10:43:31AM +0100, Josef Lusticky wrote:
> This patch series adds SPI pinctrl nodes to sun5i SoCs.
>
> While spi0 is common to all A10s, A13 and GR8 (PATCH 1/3),
> spi2 has alternate pins on the PB bank only on A10s (already in sun5i-a10s.dtsi) and GR8 (PATCH 2/3).
>
> The spi1_cs1 is only available on A10s (PATCH 3/3).
>
> The spi1_cs1 is potentially available on GR8 as well
> (at least it is specified in drivers/pinctrl/sunxi/pinctrl-sun5i.c),
> but I was not able to find it in the datasheet.
> The same applies to spi2_cs1.
>
> Both spi1_cs1 and spi2_cs1 can be added later to sun5i-gr8.dtsi.
Thanks for your patches, unfortunately, in order to keep the DT size
reasonable, if there's no user of the pinctrl node we don't merge
them. If you have a board that would use it, you can still send those
changes at the same time.
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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2019-01-23 9:43 [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Josef Lusticky
2019-01-23 9:43 ` [PATCH 1/3] ARM: dts: sun5i: Add SPI0 pins Josef Lusticky
2019-01-23 9:43 ` [PATCH 2/3] ARM: dts: sun5i: GR8: Add SPI2 PB pins Josef Lusticky
2019-01-23 9:43 ` [PATCH 3/3] ARM: dts: sun5i: A10s: Add SPI1_CS1 PG13 pin Josef Lusticky
2019-01-23 10:36 ` [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Maxime Ripard
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