* [PATCH 1/2] cpufreq: Add i.mx8mq support
@ 2019-02-12 12:21 Abel Vesa
2019-02-12 12:21 ` [PATCH 2/2] soc: imx8: Add cpufreq registering and speed grading check for i.MX8MQ Abel Vesa
2019-02-12 12:36 ` [PATCH 1/2] cpufreq: Add i.mx8mq support Lucas Stach
0 siblings, 2 replies; 5+ messages in thread
From: Abel Vesa @ 2019-02-12 12:21 UTC (permalink / raw)
To: Anson Huang, Rafael J. Wysocki, Viresh Kumar, Shawn Guo, Sascha Hauer
Cc: Rob Herring, Abel Vesa, Anson Huang, linux-pm,
Linux Kernel Mailing List, dl-linux-imx, Fabio Estevam,
linux-arm-kernel, Lucas Stach
From: Anson Huang <Anson.Huang@nxp.com>
Add i.MX8MQ cpufreq support, current version of
EVK board does NOT support voltage scale, but next
version will add this support, so this driver only
supports cpu frequency scale, voltage scale will
be added later once new board available.
A53 CPU clock normally is from ARM_PLL, but during
ARM_PLL relock window, it will be switched to
SYS1_PLL_800M to avoid clock missing, and after
arm pll relock done, it will be switched back.
Signed-off-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/cpufreq/Kconfig.arm | 8 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/imx8mq-cpufreq.c | 223 +++++++++++++++++++++++++++++++++++++++
3 files changed, 232 insertions(+)
create mode 100644 drivers/cpufreq/imx8mq-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 179a1d3..9d8001c 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -92,6 +92,14 @@ config ARM_IMX6Q_CPUFREQ
If in doubt, say N.
+config ARM_IMX8MQ_CPUFREQ
+ tristate "NXP i.MX8MQ cpufreq support"
+ select PM_OPP
+ help
+ This adds cpufreq driver support for NXP i.MX8MQ series SoCs.
+
+ If in doubt, say N.
+
config ARM_KIRKWOOD_CPUFREQ
def_bool MACH_KIRKWOOD
help
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 689b26c..fe5416c 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
+obj-$(CONFIG_ARM_IMX8MQ_CPUFREQ) += imx8mq-cpufreq.o
obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
diff --git a/drivers/cpufreq/imx8mq-cpufreq.c b/drivers/cpufreq/imx8mq-cpufreq.c
new file mode 100644
index 0000000..ee24fab
--- /dev/null
+++ b/drivers/cpufreq/imx8mq-cpufreq.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/pm_opp.h>
+#include <linux/platform_device.h>
+#include <linux/suspend.h>
+
+static struct device *cpu_dev;
+static bool free_opp;
+static struct cpufreq_frequency_table *freq_table;
+static struct mutex set_cpufreq_lock;
+static unsigned int transition_latency;
+static unsigned int suspend_freq;
+static struct clk *a53_clk;
+static struct clk *arm_a53_src_clk;
+static struct clk *arm_pll_clk;
+static struct clk *arm_pll_out_clk;
+static struct clk *sys1_pll_800m_clk;
+
+static int imx8mq_set_target(struct cpufreq_policy *policy, unsigned int index)
+{
+ struct dev_pm_opp *opp;
+ unsigned long freq_hz;
+ unsigned int old_freq, new_freq;
+ int ret;
+
+ mutex_lock(&set_cpufreq_lock);
+
+ new_freq = freq_table[index].frequency;
+ freq_hz = new_freq * 1000;
+ old_freq = policy->cur;
+
+ rcu_read_lock();
+ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
+ if (IS_ERR(opp)) {
+ rcu_read_unlock();
+ dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
+ mutex_unlock(&set_cpufreq_lock);
+ return PTR_ERR(opp);
+ }
+ rcu_read_unlock();
+
+ dev_dbg(cpu_dev, "%u MHz --> %u MHz\n",
+ old_freq / 1000, new_freq / 1000);
+
+ clk_set_parent(arm_a53_src_clk, sys1_pll_800m_clk);
+ clk_set_rate(arm_pll_clk, new_freq * 1000);
+ clk_set_parent(arm_a53_src_clk, arm_pll_out_clk);
+
+ /* Ensure the arm clock divider is what we expect */
+ ret = clk_set_rate(a53_clk, new_freq * 1000);
+ if (ret)
+ dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
+
+ mutex_unlock(&set_cpufreq_lock);
+ return ret;
+}
+
+static int imx8mq_cpufreq_init(struct cpufreq_policy *policy)
+{
+ int ret;
+
+ policy->clk = a53_clk;
+ policy->cur = clk_get_rate(a53_clk) / 1000;
+ policy->suspend_freq = suspend_freq;
+
+ ret = cpufreq_generic_init(policy, freq_table, transition_latency);
+ if (ret) {
+ dev_err(cpu_dev, "imx8mq cpufreq init failed!\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct cpufreq_driver imx8mq_cpufreq_driver = {
+ .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
+ .verify = cpufreq_generic_frequency_table_verify,
+ .target_index = imx8mq_set_target,
+ .get = cpufreq_generic_get,
+ .init = imx8mq_cpufreq_init,
+ .name = "imx8mq-cpufreq",
+ .attr = cpufreq_generic_attr,
+#ifdef CONFIG_PM
+ .suspend = cpufreq_generic_suspend,
+#endif
+};
+
+static int imx8mq_cpufreq_probe(struct platform_device *pdev)
+{
+ struct device_node *np;
+ int num, ret;
+
+ cpu_dev = get_cpu_device(0);
+ if (!cpu_dev) {
+ pr_err("failed to get cpu0 device\n");
+ return -ENODEV;
+ }
+
+ np = of_node_get(cpu_dev->of_node);
+ if (!np) {
+ dev_err(cpu_dev, "failed to find cpu0 node\n");
+ return -ENOENT;
+ }
+
+ a53_clk = clk_get(cpu_dev, "a53");
+ arm_a53_src_clk = clk_get(cpu_dev, "arm_a53_src");
+ arm_pll_clk = clk_get(cpu_dev, "arm_pll");
+ arm_pll_out_clk = clk_get(cpu_dev, "arm_pll_out");
+ sys1_pll_800m_clk = clk_get(cpu_dev, "sys1_pll_800m");
+ if (IS_ERR(a53_clk) || IS_ERR(arm_a53_src_clk)
+ || IS_ERR(arm_pll_out_clk) || IS_ERR(arm_pll_clk)
+ || IS_ERR(sys1_pll_800m_clk)) {
+ dev_err(cpu_dev, "failed to get clocks\n");
+ ret = -ENOENT;
+ goto put_clk;
+ }
+
+ /*
+ * We expect an OPP table supplied by platform.
+ * Just, incase the platform did not supply the OPP
+ * table, it will try to get it.
+ */
+ num = dev_pm_opp_get_opp_count(cpu_dev);
+ if (num < 0) {
+ ret = dev_pm_opp_of_add_table(cpu_dev);
+ if (ret < 0) {
+ dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
+ goto put_clk;
+ }
+
+ /* Because we have added the OPPs here, we must free them */
+ free_opp = true;
+
+ num = dev_pm_opp_get_opp_count(cpu_dev);
+ if (num < 0) {
+ ret = num;
+ dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
+ goto out_free_opp;
+ }
+ }
+
+ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
+ if (ret) {
+ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
+ goto out_free_opp;
+ }
+
+ /* use MAX freq to suspend */
+ suspend_freq = freq_table[num - 1].frequency;
+
+ if (of_property_read_u32(np, "clock-latency", &transition_latency))
+ transition_latency = CPUFREQ_ETERNAL;
+
+ mutex_init(&set_cpufreq_lock);
+
+ ret = cpufreq_register_driver(&imx8mq_cpufreq_driver);
+ if (ret) {
+ dev_err(cpu_dev, "failed register driver: %d\n", ret);
+ goto free_freq_table;
+ }
+
+ of_node_put(np);
+ dev_info(cpu_dev, "registered imx8mq-cpufreq\n");
+
+ return 0;
+
+free_freq_table:
+ dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
+out_free_opp:
+ if (free_opp)
+ dev_pm_opp_of_remove_table(cpu_dev);
+put_clk:
+ if (!IS_ERR(a53_clk))
+ clk_put(a53_clk);
+ if (!IS_ERR(arm_a53_src_clk))
+ clk_put(arm_a53_src_clk);
+ if (!IS_ERR(arm_pll_clk))
+ clk_put(arm_pll_clk);
+ if (!IS_ERR(arm_pll_out_clk))
+ clk_put(arm_pll_out_clk);
+ if (!IS_ERR(sys1_pll_800m_clk))
+ clk_put(sys1_pll_800m_clk);
+ of_node_put(np);
+ return ret;
+}
+
+static int imx8mq_cpufreq_remove(struct platform_device *pdev)
+{
+ cpufreq_unregister_driver(&imx8mq_cpufreq_driver);
+ dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
+ if (free_opp)
+ dev_pm_opp_of_remove_table(cpu_dev);
+ clk_put(a53_clk);
+ clk_put(arm_a53_src_clk);
+ clk_put(arm_pll_clk);
+ clk_put(arm_pll_out_clk);
+ clk_put(sys1_pll_800m_clk);
+
+ return 0;
+}
+
+static struct platform_driver imx8mq_cpufreq_platdrv = {
+ .driver = {
+ .name = "imx8mq-cpufreq",
+ },
+ .probe = imx8mq_cpufreq_probe,
+ .remove = imx8mq_cpufreq_remove,
+};
+module_platform_driver(imx8mq_cpufreq_platdrv);
+
+MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
+MODULE_DESCRIPTION("Freescale i.MX8MQ cpufreq driver");
+MODULE_LICENSE("GPL");
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] soc: imx8: Add cpufreq registering and speed grading check for i.MX8MQ
2019-02-12 12:21 [PATCH 1/2] cpufreq: Add i.mx8mq support Abel Vesa
@ 2019-02-12 12:21 ` Abel Vesa
2019-02-12 12:44 ` Lucas Stach
2019-02-12 12:36 ` [PATCH 1/2] cpufreq: Add i.mx8mq support Lucas Stach
1 sibling, 1 reply; 5+ messages in thread
From: Abel Vesa @ 2019-02-12 12:21 UTC (permalink / raw)
To: Anson Huang, Rafael J. Wysocki, Viresh Kumar, Shawn Guo, Sascha Hauer
Cc: Rob Herring, Abel Vesa, Anson Huang, linux-pm,
Linux Kernel Mailing List, dl-linux-imx, Fabio Estevam,
linux-arm-kernel, Lucas Stach
From: Anson Huang <Anson.Huang@nxp.com>
Register cpu-freq platform driver for i.MX8.
i.MX8MQ has different parts like consumer, industrial and auto etc.,
different parts have different cpufreq set-points, this patch adds
fuse check to select correct cpufreq set-points for each part. The
default dtb has all set-points available, then kernel will check fuse
to disable those unused set-points, definition as below:
OCOTP offset 0x440, bit [7:6]
'00' - Consumer 0C to 95C
'01' - Ext. Consumer -20C to 105C
'10' - Industrial -40C to 105C
'11' - Automotive -40C to 125C
cpu-freq set-points definition as below (datasheet Rev-E):
Normal Over-Drive
Consumer 1GHz@0.9V 1.5GHz@1V
Industrial 800MHz@0.9V 1.3GHz@1V
Signed-off-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/soc/imx/Makefile | 1 +
drivers/soc/imx/soc-imx8.c | 107 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 108 insertions(+)
create mode 100644 drivers/soc/imx/soc-imx8.c
diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 506a6f3..d6b529e0 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
+obj-$(CONFIG_ARCH_MXC) += soc-imx8.o
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
new file mode 100644
index 0000000..3896310
--- /dev/null
+++ b/drivers/soc/imx/soc-imx8.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP.
+ */
+
+#include <linux/cpu.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/pm_opp.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+
+#define OCOTP_CFG3 0x440
+#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
+#define OCOTP_CFG3_CONSUMER 0
+#define OCOTP_CFG3_EXT_CONSUMER 1
+#define OCOTP_CFG3_INDUSTRIAL 2
+#define OCOTP_CFG3_AUTO 3
+
+static void __init imx8mq_opp_check_speed_grading(struct device *cpu_dev)
+{
+ struct device_node *np;
+ void __iomem *base;
+ u32 val;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
+ if (!np) {
+ pr_warn("failed to find ocotp node\n");
+ return;
+ }
+
+ base = of_iomap(np, 0);
+ if (!base) {
+ pr_warn("failed to map ocotp\n");
+ goto put_node;
+ }
+ val = readl_relaxed(base + OCOTP_CFG3);
+ val >>= OCOTP_CFG3_MKT_SEGMENT_SHIFT;
+ val &= 0x3;
+
+ switch (val) {
+ case OCOTP_CFG3_CONSUMER:
+ if (dev_pm_opp_disable(cpu_dev, 800000000))
+ pr_warn("failed to disable 800MHz OPP!\n");
+ if (dev_pm_opp_disable(cpu_dev, 1300000000))
+ pr_warn("failed to disable 1.3GHz OPP!\n");
+ break;
+ case OCOTP_CFG3_INDUSTRIAL:
+ if (dev_pm_opp_disable(cpu_dev, 1000000000))
+ pr_warn("failed to disable 1GHz OPP!\n");
+ if (dev_pm_opp_disable(cpu_dev, 1500000000))
+ pr_warn("failed to disable 1.5GHz OPP!\n");
+ break;
+ default:
+ /* consumer part for default */
+ if (dev_pm_opp_disable(cpu_dev, 800000000))
+ pr_warn("failed to disable 800MHz OPP!\n");
+ if (dev_pm_opp_disable(cpu_dev, 1300000000))
+ pr_warn("failed to disable 1.3GHz OPP!\n");
+ break;
+ }
+
+ iounmap(base);
+
+put_node:
+ of_node_put(np);
+}
+
+static void __init imx8mq_opp_init(void)
+{
+ struct device_node *np;
+ struct device *cpu_dev = get_cpu_device(0);
+
+ if (!cpu_dev) {
+ pr_warn("failed to get cpu0 device\n");
+ return;
+ }
+ np = of_node_get(cpu_dev->of_node);
+ if (!np) {
+ pr_warn("failed to find cpu0 node\n");
+ return;
+ }
+
+ if (dev_pm_opp_of_add_table(cpu_dev)) {
+ pr_warn("failed to init OPP table\n");
+ goto put_node;
+ }
+
+ imx8mq_opp_check_speed_grading(cpu_dev);
+
+put_node:
+ of_node_put(np);
+}
+
+static int __init imx8_register_cpufreq(void)
+{
+ if (of_machine_is_compatible("fsl,imx8mq")) {
+ imx8mq_opp_init();
+ platform_device_register_simple("imx8mq-cpufreq", -1, NULL, 0);
+ }
+
+ return 0;
+}
+late_initcall(imx8_register_cpufreq);
--
2.7.4
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] cpufreq: Add i.mx8mq support
2019-02-12 12:21 [PATCH 1/2] cpufreq: Add i.mx8mq support Abel Vesa
2019-02-12 12:21 ` [PATCH 2/2] soc: imx8: Add cpufreq registering and speed grading check for i.MX8MQ Abel Vesa
@ 2019-02-12 12:36 ` Lucas Stach
2019-02-12 12:43 ` Abel Vesa
1 sibling, 1 reply; 5+ messages in thread
From: Lucas Stach @ 2019-02-12 12:36 UTC (permalink / raw)
To: Abel Vesa, Anson Huang, Rafael J. Wysocki, Viresh Kumar,
Shawn Guo, Sascha Hauer
Cc: Rob Herring, linux-pm, Linux Kernel Mailing List, dl-linux-imx,
Fabio Estevam, linux-arm-kernel
Hi Abel,
we really don't want another platform specific cpufreq driver in
mainline. The CPU clock change dance should be abstracted in the
imx8mq-clk driver, just like we do on i.MX5 and i.MX7. This would allow
us to reuse the cpufreq-dt driver, like we do on those platforms.
Regards,
Lucas
Am Dienstag, den 12.02.2019, 12:21 +0000 schrieb Abel Vesa:
> > From: Anson Huang <Anson.Huang@nxp.com>
>
> Add i.MX8MQ cpufreq support, current version of
> EVK board does NOT support voltage scale, but next
> version will add this support, so this driver only
> supports cpu frequency scale, voltage scale will
> be added later once new board available.
>
> A53 CPU clock normally is from ARM_PLL, but during
> ARM_PLL relock window, it will be switched to
> SYS1_PLL_800M to avoid clock missing, and after
> arm pll relock done, it will be switched back.
>
> > Signed-off-by: Anson Huang <anson.huang@nxp.com>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/cpufreq/Kconfig.arm | 8 ++
> drivers/cpufreq/Makefile | 1 +
> drivers/cpufreq/imx8mq-cpufreq.c | 223 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 232 insertions(+)
> create mode 100644 drivers/cpufreq/imx8mq-cpufreq.c
>
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 179a1d3..9d8001c 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -92,6 +92,14 @@ config ARM_IMX6Q_CPUFREQ
>
> > If in doubt, say N.
>
> +config ARM_IMX8MQ_CPUFREQ
> > + tristate "NXP i.MX8MQ cpufreq support"
> > + select PM_OPP
> > + help
> > + This adds cpufreq driver support for NXP i.MX8MQ series SoCs.
> +
> > + If in doubt, say N.
> +
> config ARM_KIRKWOOD_CPUFREQ
> > def_bool MACH_KIRKWOOD
> > help
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index 689b26c..fe5416c 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> > @@ -56,6 +56,7 @@ obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
> > obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
> > obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
> > obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
> > +obj-$(CONFIG_ARM_IMX8MQ_CPUFREQ) += imx8mq-cpufreq.o
> > obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
> > obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
> > obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
> diff --git a/drivers/cpufreq/imx8mq-cpufreq.c b/drivers/cpufreq/imx8mq-cpufreq.c
> new file mode 100644
> index 0000000..ee24fab
> --- /dev/null
> +++ b/drivers/cpufreq/imx8mq-cpufreq.c
> @@ -0,0 +1,223 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 NXP
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/cpu.h>
> +#include <linux/cpufreq.h>
> +#include <linux/err.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/of.h>
> +#include <linux/pm_opp.h>
> +#include <linux/platform_device.h>
> +#include <linux/suspend.h>
> +
> +static struct device *cpu_dev;
> +static bool free_opp;
> +static struct cpufreq_frequency_table *freq_table;
> +static struct mutex set_cpufreq_lock;
> +static unsigned int transition_latency;
> +static unsigned int suspend_freq;
> +static struct clk *a53_clk;
> +static struct clk *arm_a53_src_clk;
> +static struct clk *arm_pll_clk;
> +static struct clk *arm_pll_out_clk;
> +static struct clk *sys1_pll_800m_clk;
> +
> +static int imx8mq_set_target(struct cpufreq_policy *policy, unsigned int index)
> +{
> > + struct dev_pm_opp *opp;
> > + unsigned long freq_hz;
> > + unsigned int old_freq, new_freq;
> > + int ret;
> +
> > + mutex_lock(&set_cpufreq_lock);
> +
> > + new_freq = freq_table[index].frequency;
> > + freq_hz = new_freq * 1000;
> > + old_freq = policy->cur;
> +
> > + rcu_read_lock();
> > + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
> > + if (IS_ERR(opp)) {
> > + rcu_read_unlock();
> > + dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
> > + mutex_unlock(&set_cpufreq_lock);
> > + return PTR_ERR(opp);
> > + }
> > + rcu_read_unlock();
> +
> > + dev_dbg(cpu_dev, "%u MHz --> %u MHz\n",
> > + old_freq / 1000, new_freq / 1000);
> +
> > + clk_set_parent(arm_a53_src_clk, sys1_pll_800m_clk);
> > + clk_set_rate(arm_pll_clk, new_freq * 1000);
> > + clk_set_parent(arm_a53_src_clk, arm_pll_out_clk);
> +
> > + /* Ensure the arm clock divider is what we expect */
> > + ret = clk_set_rate(a53_clk, new_freq * 1000);
> > + if (ret)
> > + dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
> +
> > + mutex_unlock(&set_cpufreq_lock);
> > + return ret;
> +}
> +
> +static int imx8mq_cpufreq_init(struct cpufreq_policy *policy)
> +{
> > + int ret;
> +
> > + policy->clk = a53_clk;
> > + policy->cur = clk_get_rate(a53_clk) / 1000;
> > + policy->suspend_freq = suspend_freq;
> +
> > + ret = cpufreq_generic_init(policy, freq_table, transition_latency);
> > + if (ret) {
> > + dev_err(cpu_dev, "imx8mq cpufreq init failed!\n");
> > + return ret;
> > + }
> +
> > + return 0;
> +}
> +
> +static struct cpufreq_driver imx8mq_cpufreq_driver = {
> > + .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
> > + .verify = cpufreq_generic_frequency_table_verify,
> > + .target_index = imx8mq_set_target,
> > + .get = cpufreq_generic_get,
> > + .init = imx8mq_cpufreq_init,
> > + .name = "imx8mq-cpufreq",
> > + .attr = cpufreq_generic_attr,
> +#ifdef CONFIG_PM
> > + .suspend = cpufreq_generic_suspend,
> +#endif
> +};
> +
> +static int imx8mq_cpufreq_probe(struct platform_device *pdev)
> +{
> > + struct device_node *np;
> > + int num, ret;
> +
> > + cpu_dev = get_cpu_device(0);
> > + if (!cpu_dev) {
> > + pr_err("failed to get cpu0 device\n");
> > + return -ENODEV;
> > + }
> +
> > + np = of_node_get(cpu_dev->of_node);
> > + if (!np) {
> > + dev_err(cpu_dev, "failed to find cpu0 node\n");
> > + return -ENOENT;
> > + }
> +
> > + a53_clk = clk_get(cpu_dev, "a53");
> > + arm_a53_src_clk = clk_get(cpu_dev, "arm_a53_src");
> > + arm_pll_clk = clk_get(cpu_dev, "arm_pll");
> > + arm_pll_out_clk = clk_get(cpu_dev, "arm_pll_out");
> > + sys1_pll_800m_clk = clk_get(cpu_dev, "sys1_pll_800m");
> > + if (IS_ERR(a53_clk) || IS_ERR(arm_a53_src_clk)
> > + || IS_ERR(arm_pll_out_clk) || IS_ERR(arm_pll_clk)
> > + || IS_ERR(sys1_pll_800m_clk)) {
> > + dev_err(cpu_dev, "failed to get clocks\n");
> > + ret = -ENOENT;
> > + goto put_clk;
> > + }
> +
> > + /*
> > + * We expect an OPP table supplied by platform.
> > + * Just, incase the platform did not supply the OPP
> > + * table, it will try to get it.
> > + */
> > + num = dev_pm_opp_get_opp_count(cpu_dev);
> > + if (num < 0) {
> > + ret = dev_pm_opp_of_add_table(cpu_dev);
> > + if (ret < 0) {
> > + dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
> > + goto put_clk;
> > + }
> +
> > + /* Because we have added the OPPs here, we must free them */
> > + free_opp = true;
> +
> > + num = dev_pm_opp_get_opp_count(cpu_dev);
> > + if (num < 0) {
> > + ret = num;
> > + dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
> > + goto out_free_opp;
> > + }
> > + }
> +
> > + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
> > + if (ret) {
> > + dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
> > + goto out_free_opp;
> > + }
> +
> > + /* use MAX freq to suspend */
> > + suspend_freq = freq_table[num - 1].frequency;
> +
> > + if (of_property_read_u32(np, "clock-latency", &transition_latency))
> > + transition_latency = CPUFREQ_ETERNAL;
> +
> > + mutex_init(&set_cpufreq_lock);
> +
> > + ret = cpufreq_register_driver(&imx8mq_cpufreq_driver);
> > + if (ret) {
> > + dev_err(cpu_dev, "failed register driver: %d\n", ret);
> > + goto free_freq_table;
> > + }
> +
> > + of_node_put(np);
> > + dev_info(cpu_dev, "registered imx8mq-cpufreq\n");
> +
> > + return 0;
> +
> +free_freq_table:
> > + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
> +out_free_opp:
> > + if (free_opp)
> > + dev_pm_opp_of_remove_table(cpu_dev);
> +put_clk:
> > + if (!IS_ERR(a53_clk))
> > + clk_put(a53_clk);
> > + if (!IS_ERR(arm_a53_src_clk))
> > + clk_put(arm_a53_src_clk);
> > + if (!IS_ERR(arm_pll_clk))
> > + clk_put(arm_pll_clk);
> > + if (!IS_ERR(arm_pll_out_clk))
> > + clk_put(arm_pll_out_clk);
> > + if (!IS_ERR(sys1_pll_800m_clk))
> > + clk_put(sys1_pll_800m_clk);
> > + of_node_put(np);
> > + return ret;
> +}
> +
> +static int imx8mq_cpufreq_remove(struct platform_device *pdev)
> +{
> > + cpufreq_unregister_driver(&imx8mq_cpufreq_driver);
> > + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
> > + if (free_opp)
> > + dev_pm_opp_of_remove_table(cpu_dev);
> > + clk_put(a53_clk);
> > + clk_put(arm_a53_src_clk);
> > + clk_put(arm_pll_clk);
> > + clk_put(arm_pll_out_clk);
> > + clk_put(sys1_pll_800m_clk);
> +
> > + return 0;
> +}
> +
> +static struct platform_driver imx8mq_cpufreq_platdrv = {
> > + .driver = {
> > > + .name = "imx8mq-cpufreq",
> > + },
> > > + .probe = imx8mq_cpufreq_probe,
> > > + .remove = imx8mq_cpufreq_remove,
> +};
> +module_platform_driver(imx8mq_cpufreq_platdrv);
> +
> > +MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
> +MODULE_DESCRIPTION("Freescale i.MX8MQ cpufreq driver");
> +MODULE_LICENSE("GPL");
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] cpufreq: Add i.mx8mq support
2019-02-12 12:36 ` [PATCH 1/2] cpufreq: Add i.mx8mq support Lucas Stach
@ 2019-02-12 12:43 ` Abel Vesa
0 siblings, 0 replies; 5+ messages in thread
From: Abel Vesa @ 2019-02-12 12:43 UTC (permalink / raw)
To: Lucas Stach
Cc: Rob Herring, Anson Huang, linux-pm, Viresh Kumar,
Rafael J. Wysocki, Linux Kernel Mailing List, dl-linux-imx,
Sascha Hauer, Fabio Estevam, Shawn Guo, linux-arm-kernel
On 19-02-12 13:36:39, Lucas Stach wrote:
> Hi Abel,
>
> we really don't want another platform specific cpufreq driver in
> mainline. The CPU clock change dance should be abstracted in the
> imx8mq-clk driver, just like we do on i.MX5 and i.MX7. This would allow
> us to reuse the cpufreq-dt driver, like we do on those platforms.
>
Fair enough. This is what we had in our internal tree.
Will rewrite as suggested then.
Thanks.
> Regards,
> Lucas
>
> Am Dienstag, den 12.02.2019, 12:21 +0000 schrieb Abel Vesa:
> > > From: Anson Huang <Anson.Huang@nxp.com>
> >
> > Add i.MX8MQ cpufreq support, current version of
> > EVK board does NOT support voltage scale, but next
> > version will add this support, so this driver only
> > supports cpu frequency scale, voltage scale will
> > be added later once new board available.
> >
> > A53 CPU clock normally is from ARM_PLL, but during
> > ARM_PLL relock window, it will be switched to
> > SYS1_PLL_800M to avoid clock missing, and after
> > arm pll relock done, it will be switched back.
> >
> > > Signed-off-by: Anson Huang <anson.huang@nxp.com>
> > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > ---
> > drivers/cpufreq/Kconfig.arm | 8 ++
> > drivers/cpufreq/Makefile | 1 +
> > drivers/cpufreq/imx8mq-cpufreq.c | 223 +++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 232 insertions(+)
> > create mode 100644 drivers/cpufreq/imx8mq-cpufreq.c
> >
> > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> > index 179a1d3..9d8001c 100644
> > --- a/drivers/cpufreq/Kconfig.arm
> > +++ b/drivers/cpufreq/Kconfig.arm
> > @@ -92,6 +92,14 @@ config ARM_IMX6Q_CPUFREQ
> >
> > > If in doubt, say N.
> >
> > +config ARM_IMX8MQ_CPUFREQ
> > > + tristate "NXP i.MX8MQ cpufreq support"
> > > + select PM_OPP
> > > + help
> > > + This adds cpufreq driver support for NXP i.MX8MQ series SoCs.
> > +
> > > + If in doubt, say N.
> > +
> > config ARM_KIRKWOOD_CPUFREQ
> > > def_bool MACH_KIRKWOOD
> > > help
> > diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> > index 689b26c..fe5416c 100644
> > --- a/drivers/cpufreq/Makefile
> > +++ b/drivers/cpufreq/Makefile
> > > @@ -56,6 +56,7 @@ obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
> > > obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
> > > obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
> > > obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
> > > +obj-$(CONFIG_ARM_IMX8MQ_CPUFREQ) += imx8mq-cpufreq.o
> > > obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
> > > obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
> > > obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
> > diff --git a/drivers/cpufreq/imx8mq-cpufreq.c b/drivers/cpufreq/imx8mq-cpufreq.c
> > new file mode 100644
> > index 0000000..ee24fab
> > --- /dev/null
> > +++ b/drivers/cpufreq/imx8mq-cpufreq.c
> > @@ -0,0 +1,223 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019 NXP
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/cpu.h>
> > +#include <linux/cpufreq.h>
> > +#include <linux/err.h>
> > +#include <linux/module.h>
> > +#include <linux/slab.h>
> > +#include <linux/of.h>
> > +#include <linux/pm_opp.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/suspend.h>
> > +
> > +static struct device *cpu_dev;
> > +static bool free_opp;
> > +static struct cpufreq_frequency_table *freq_table;
> > +static struct mutex set_cpufreq_lock;
> > +static unsigned int transition_latency;
> > +static unsigned int suspend_freq;
> > +static struct clk *a53_clk;
> > +static struct clk *arm_a53_src_clk;
> > +static struct clk *arm_pll_clk;
> > +static struct clk *arm_pll_out_clk;
> > +static struct clk *sys1_pll_800m_clk;
> > +
> > +static int imx8mq_set_target(struct cpufreq_policy *policy, unsigned int index)
> > +{
> > > + struct dev_pm_opp *opp;
> > > + unsigned long freq_hz;
> > > + unsigned int old_freq, new_freq;
> > > + int ret;
> > +
> > > + mutex_lock(&set_cpufreq_lock);
> > +
> > > + new_freq = freq_table[index].frequency;
> > > + freq_hz = new_freq * 1000;
> > > + old_freq = policy->cur;
> > +
> > > + rcu_read_lock();
> > > + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
> > > + if (IS_ERR(opp)) {
> > > + rcu_read_unlock();
> > > + dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
> > > + mutex_unlock(&set_cpufreq_lock);
> > > + return PTR_ERR(opp);
> > > + }
> > > + rcu_read_unlock();
> > +
> > > + dev_dbg(cpu_dev, "%u MHz --> %u MHz\n",
> > > + old_freq / 1000, new_freq / 1000);
> > +
> > > + clk_set_parent(arm_a53_src_clk, sys1_pll_800m_clk);
> > > + clk_set_rate(arm_pll_clk, new_freq * 1000);
> > > + clk_set_parent(arm_a53_src_clk, arm_pll_out_clk);
> > +
> > > + /* Ensure the arm clock divider is what we expect */
> > > + ret = clk_set_rate(a53_clk, new_freq * 1000);
> > > + if (ret)
> > > + dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
> > +
> > > + mutex_unlock(&set_cpufreq_lock);
> > > + return ret;
> > +}
> > +
> > +static int imx8mq_cpufreq_init(struct cpufreq_policy *policy)
> > +{
> > > + int ret;
> > +
> > > + policy->clk = a53_clk;
> > > + policy->cur = clk_get_rate(a53_clk) / 1000;
> > > + policy->suspend_freq = suspend_freq;
> > +
> > > + ret = cpufreq_generic_init(policy, freq_table, transition_latency);
> > > + if (ret) {
> > > + dev_err(cpu_dev, "imx8mq cpufreq init failed!\n");
> > > + return ret;
> > > + }
> > +
> > > + return 0;
> > +}
> > +
> > +static struct cpufreq_driver imx8mq_cpufreq_driver = {
> > > + .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
> > > + .verify = cpufreq_generic_frequency_table_verify,
> > > + .target_index = imx8mq_set_target,
> > > + .get = cpufreq_generic_get,
> > > + .init = imx8mq_cpufreq_init,
> > > + .name = "imx8mq-cpufreq",
> > > + .attr = cpufreq_generic_attr,
> > +#ifdef CONFIG_PM
> > > + .suspend = cpufreq_generic_suspend,
> > +#endif
> > +};
> > +
> > +static int imx8mq_cpufreq_probe(struct platform_device *pdev)
> > +{
> > > + struct device_node *np;
> > > + int num, ret;
> > +
> > > + cpu_dev = get_cpu_device(0);
> > > + if (!cpu_dev) {
> > > + pr_err("failed to get cpu0 device\n");
> > > + return -ENODEV;
> > > + }
> > +
> > > + np = of_node_get(cpu_dev->of_node);
> > > + if (!np) {
> > > + dev_err(cpu_dev, "failed to find cpu0 node\n");
> > > + return -ENOENT;
> > > + }
> > +
> > > + a53_clk = clk_get(cpu_dev, "a53");
> > > + arm_a53_src_clk = clk_get(cpu_dev, "arm_a53_src");
> > > + arm_pll_clk = clk_get(cpu_dev, "arm_pll");
> > > + arm_pll_out_clk = clk_get(cpu_dev, "arm_pll_out");
> > > + sys1_pll_800m_clk = clk_get(cpu_dev, "sys1_pll_800m");
> > > + if (IS_ERR(a53_clk) || IS_ERR(arm_a53_src_clk)
> > > + || IS_ERR(arm_pll_out_clk) || IS_ERR(arm_pll_clk)
> > > + || IS_ERR(sys1_pll_800m_clk)) {
> > > + dev_err(cpu_dev, "failed to get clocks\n");
> > > + ret = -ENOENT;
> > > + goto put_clk;
> > > + }
> > +
> > > + /*
> > > + * We expect an OPP table supplied by platform.
> > > + * Just, incase the platform did not supply the OPP
> > > + * table, it will try to get it.
> > > + */
> > > + num = dev_pm_opp_get_opp_count(cpu_dev);
> > > + if (num < 0) {
> > > + ret = dev_pm_opp_of_add_table(cpu_dev);
> > > + if (ret < 0) {
> > > + dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
> > > + goto put_clk;
> > > + }
> > +
> > > + /* Because we have added the OPPs here, we must free them */
> > > + free_opp = true;
> > +
> > > + num = dev_pm_opp_get_opp_count(cpu_dev);
> > > + if (num < 0) {
> > > + ret = num;
> > > + dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
> > > + goto out_free_opp;
> > > + }
> > > + }
> > +
> > > + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
> > > + if (ret) {
> > > + dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
> > > + goto out_free_opp;
> > > + }
> > +
> > > + /* use MAX freq to suspend */
> > > + suspend_freq = freq_table[num - 1].frequency;
> > +
> > > + if (of_property_read_u32(np, "clock-latency", &transition_latency))
> > > + transition_latency = CPUFREQ_ETERNAL;
> > +
> > > + mutex_init(&set_cpufreq_lock);
> > +
> > > + ret = cpufreq_register_driver(&imx8mq_cpufreq_driver);
> > > + if (ret) {
> > > + dev_err(cpu_dev, "failed register driver: %d\n", ret);
> > > + goto free_freq_table;
> > > + }
> > +
> > > + of_node_put(np);
> > > + dev_info(cpu_dev, "registered imx8mq-cpufreq\n");
> > +
> > > + return 0;
> > +
> > +free_freq_table:
> > > + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
> > +out_free_opp:
> > > + if (free_opp)
> > > + dev_pm_opp_of_remove_table(cpu_dev);
> > +put_clk:
> > > + if (!IS_ERR(a53_clk))
> > > + clk_put(a53_clk);
> > > + if (!IS_ERR(arm_a53_src_clk))
> > > + clk_put(arm_a53_src_clk);
> > > + if (!IS_ERR(arm_pll_clk))
> > > + clk_put(arm_pll_clk);
> > > + if (!IS_ERR(arm_pll_out_clk))
> > > + clk_put(arm_pll_out_clk);
> > > + if (!IS_ERR(sys1_pll_800m_clk))
> > > + clk_put(sys1_pll_800m_clk);
> > > + of_node_put(np);
> > > + return ret;
> > +}
> > +
> > +static int imx8mq_cpufreq_remove(struct platform_device *pdev)
> > +{
> > > + cpufreq_unregister_driver(&imx8mq_cpufreq_driver);
> > > + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
> > > + if (free_opp)
> > > + dev_pm_opp_of_remove_table(cpu_dev);
> > > + clk_put(a53_clk);
> > > + clk_put(arm_a53_src_clk);
> > > + clk_put(arm_pll_clk);
> > > + clk_put(arm_pll_out_clk);
> > > + clk_put(sys1_pll_800m_clk);
> > +
> > > + return 0;
> > +}
> > +
> > +static struct platform_driver imx8mq_cpufreq_platdrv = {
> > > + .driver = {
> > > > + .name = "imx8mq-cpufreq",
> > > + },
> > > > + .probe = imx8mq_cpufreq_probe,
> > > > + .remove = imx8mq_cpufreq_remove,
> > +};
> > +module_platform_driver(imx8mq_cpufreq_platdrv);
> > +
> > > +MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
> > +MODULE_DESCRIPTION("Freescale i.MX8MQ cpufreq driver");
> > +MODULE_LICENSE("GPL");
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] soc: imx8: Add cpufreq registering and speed grading check for i.MX8MQ
2019-02-12 12:21 ` [PATCH 2/2] soc: imx8: Add cpufreq registering and speed grading check for i.MX8MQ Abel Vesa
@ 2019-02-12 12:44 ` Lucas Stach
0 siblings, 0 replies; 5+ messages in thread
From: Lucas Stach @ 2019-02-12 12:44 UTC (permalink / raw)
To: Abel Vesa, Anson Huang, Rafael J. Wysocki, Viresh Kumar,
Shawn Guo, Sascha Hauer
Cc: Rob Herring, linux-pm, Linux Kernel Mailing List, dl-linux-imx,
Fabio Estevam, linux-arm-kernel
Hi Abel,
Am Dienstag, den 12.02.2019, 12:21 +0000 schrieb Abel Vesa:
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Register cpu-freq platform driver for i.MX8.
> i.MX8MQ has different parts like consumer, industrial and auto etc.,
> different parts have different cpufreq set-points, this patch adds
> fuse check to select correct cpufreq set-points for each part. The
> default dtb has all set-points available, then kernel will check fuse
> to disable those unused set-points, definition as below:
>
> OCOTP offset 0x440, bit [7:6]
>
> '00' - Consumer 0C to 95C
> '01' - Ext. Consumer -20C to 105C
> '10' - Industrial -40C to 105C
> '11' - Automotive -40C to 125C
Shouldn't this read 0x440 [9:8] (SPEED_GRADING) instead? According to
the RM those 2 bits directly encode the maximum ARM core frequency, so
we don't need to guess from the target market.
Regards,
Lucas
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-02-12 12:45 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-12 12:21 [PATCH 1/2] cpufreq: Add i.mx8mq support Abel Vesa
2019-02-12 12:21 ` [PATCH 2/2] soc: imx8: Add cpufreq registering and speed grading check for i.MX8MQ Abel Vesa
2019-02-12 12:44 ` Lucas Stach
2019-02-12 12:36 ` [PATCH 1/2] cpufreq: Add i.mx8mq support Lucas Stach
2019-02-12 12:43 ` Abel Vesa
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