* [PATCH v6 01/12] dt-binding: gce: remove thread-num property
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 02/12] dt-binding: gce: add gce header file for mt8183 Bibby Hsieh
` (10 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
"thread-num" is an unused property so we remove it from example.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
index 7d72b21c9e94..cfe40b01d164 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -39,7 +39,6 @@ Example:
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_GCE>;
clock-names = "gce";
- thread-num = CMDQ_THR_MAX_COUNT;
#mbox-cells = <3>;
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 02/12] dt-binding: gce: add gce header file for mt8183
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 01/12] dt-binding: gce: remove thread-num property Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 03/12] dt-binding: gce: add binding for gce subsys property Bibby Hsieh
` (9 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
Add documentation for the mt8183 gce.
Add gce header file defined the gce hardware event,
subsys number and constant for mt8183.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/mailbox/mtk-gce.txt | 6 +-
include/dt-bindings/gce/mt8183-gce.h | 177 ++++++++++++++++++
2 files changed, 180 insertions(+), 3 deletions(-)
create mode 100644 include/dt-bindings/gce/mt8183-gce.h
diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
index cfe40b01d164..1f7f8f2a3f49 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to
mailbox.txt for generic information about mailbox device-tree bindings.
Required properties:
-- compatible: Must be "mediatek,mt8173-gce"
+- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
- reg: Address range of the GCE unit
- interrupts: The interrupt signal from the GCE block
- clock: Clocks according to the common clock binding
@@ -28,8 +28,8 @@ Required properties for a client device:
- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
to the register address.
-Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as
-sub-system ids, thread priority, event ids.
+Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
+or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
Example:
diff --git a/include/dt-bindings/gce/mt8183-gce.h b/include/dt-bindings/gce/mt8183-gce.h
new file mode 100644
index 000000000000..aeb95154fac2
--- /dev/null
+++ b/include/dt-bindings/gce/mt8183-gce.h
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Bibby Hsieh <bibby.hsieh@mediatek.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_GCE_MT8183_H
+#define _DT_BINDINGS_GCE_MT8183_H
+
+#define CMDQ_NO_TIMEOUT 0xffffffff
+
+#define CMDQ_THR_MAX_COUNT 24
+
+/* GCE HW thread priority */
+#define CMDQ_THR_PRIO_LOWEST 0
+#define CMDQ_THR_PRIO_HIGHEST 1
+
+/* GCE SUBSYS */
+#define SUBSYS_1300XXXX 0
+#define SUBSYS_1400XXXX 1
+#define SUBSYS_1401XXXX 2
+#define SUBSYS_1402XXXX 3
+#define SUBSYS_1502XXXX 4
+#define SUBSYS_1880XXXX 5
+#define SUBSYS_1881XXXX 6
+#define SUBSYS_1882XXXX 7
+#define SUBSYS_1883XXXX 8
+#define SUBSYS_1884XXXX 9
+#define SUBSYS_1000XXXX 10
+#define SUBSYS_1001XXXX 11
+#define SUBSYS_1002XXXX 12
+#define SUBSYS_1003XXXX 13
+#define SUBSYS_1004XXXX 14
+#define SUBSYS_1005XXXX 15
+#define SUBSYS_1020XXXX 16
+#define SUBSYS_1028XXXX 17
+#define SUBSYS_1700XXXX 18
+#define SUBSYS_1701XXXX 19
+#define SUBSYS_1702XXXX 20
+#define SUBSYS_1703XXXX 21
+#define SUBSYS_1800XXXX 22
+#define SUBSYS_1801XXXX 23
+#define SUBSYS_1802XXXX 24
+#define SUBSYS_1804XXXX 25
+#define SUBSYS_1805XXXX 26
+#define SUBSYS_1808XXXX 27
+#define SUBSYS_180aXXXX 28
+#define SUBSYS_180bXXXX 29
+
+#define CMDQ_EVENT_DISP_RDMA0_SOF 0
+#define CMDQ_EVENT_DISP_RDMA1_SOF 1
+#define CMDQ_EVENT_MDP_RDMA0_SOF 2
+#define CMDQ_EVENT_MDP_RSZ0_SOF 4
+#define CMDQ_EVENT_MDP_RSZ1_SOF 5
+#define CMDQ_EVENT_MDP_TDSHP_SOF 6
+#define CMDQ_EVENT_MDP_WROT0_SOF 7
+#define CMDQ_EVENT_MDP_WDMA0_SOF 8
+#define CMDQ_EVENT_DISP_OVL0_SOF 9
+#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10
+#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11
+#define CMDQ_EVENT_DISP_WDMA0_SOF 12
+#define CMDQ_EVENT_DISP_COLOR0_SOF 13
+#define CMDQ_EVENT_DISP_CCORR0_SOF 14
+#define CMDQ_EVENT_DISP_AAL0_SOF 15
+#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
+#define CMDQ_EVENT_DISP_DITHER0_SOF 17
+#define CMDQ_EVENT_DISP_PWM0_SOF 18
+#define CMDQ_EVENT_DISP_DSI0_SOF 19
+#define CMDQ_EVENT_DISP_DPI0_SOF 20
+#define CMDQ_EVENT_DISP_RSZ_SOF 22
+#define CMDQ_EVENT_MDP_AAL_SOF 23
+#define CMDQ_EVENT_MDP_CCORR_SOF 24
+#define CMDQ_EVENT_DISP_DBI_SOF 25
+#define CMDQ_EVENT_DISP_RDMA0_EOF 26
+#define CMDQ_EVENT_DISP_RDMA1_EOF 27
+#define CMDQ_EVENT_MDP_RDMA0_EOF 28
+#define CMDQ_EVENT_MDP_RSZ0_EOF 30
+#define CMDQ_EVENT_MDP_RSZ1_EOF 31
+#define CMDQ_EVENT_MDP_TDSHP_EOF 32
+#define CMDQ_EVENT_MDP_WROT0_EOF 33
+#define CMDQ_EVENT_MDP_WDMA0_EOF 34
+#define CMDQ_EVENT_DISP_OVL0_EOF 35
+#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36
+#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37
+#define CMDQ_EVENT_DISP_WDMA0_EOF 38
+#define CMDQ_EVENT_DISP_COLOR0_EOF 39
+#define CMDQ_EVENT_DISP_CCORR0_EOF 40
+#define CMDQ_EVENT_DISP_AAL0_EOF 41
+#define CMDQ_EVENT_DISP_GAMMA0_EOF 42
+#define CMDQ_EVENT_DISP_DITHER0_EOF 43
+#define CMDQ_EVENT_DSI0_EOF 44
+#define CMDQ_EVENT_DPI0_EOF 45
+#define CMDQ_EVENT_DISP_RSZ_EOF 47
+#define CMDQ_EVENT_MDP_AAL_EOF 48
+#define CMDQ_EVENT_MDP_CCORR_EOF 49
+#define CMDQ_EVENT_DBI_EOF 50
+#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130
+#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131
+#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132
+#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133
+#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134
+#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135
+#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136
+#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137
+#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138
+#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139
+#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140
+#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141
+#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142
+#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143
+#define CMDQ_EVENT_DSI0_TE_EVENT 144
+#define CMDQ_EVENT_DSI0_IRQ_EVENT 145
+#define CMDQ_EVENT_DSI0_DONE_EVENT 146
+#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150
+#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151
+#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152
+#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154
+#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155
+#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156
+#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274
+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275
+#define CMDQ_EVENT_AMD_FRAME_DONE 276
+#define CMDQ_EVENT_DVE_DONE 277
+#define CMDQ_EVENT_WMFE_DONE 278
+#define CMDQ_EVENT_RSC_DONE 279
+#define CMDQ_EVENT_MFB_DONE 280
+#define CMDQ_EVENT_WPE_A_DONE 281
+#define CMDQ_EVENT_SPE_B_DONE 282
+#define CMDQ_EVENT_OCC_DONE 283
+#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289
+#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290
+#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291
+#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292
+#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293
+#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
+#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
+#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323
+#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324
+#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325
+#define CMDQ_EVENT_TSF_DONE 326
+#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327
+#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328
+#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329
+#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330
+#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331
+#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332
+#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333
+#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334
+#define CMDQ_EVENT_IPU_CORE0_DONE0 353
+#define CMDQ_EVENT_IPU_CORE0_DONE1 354
+#define CMDQ_EVENT_IPU_CORE0_DONE2 355
+#define CMDQ_EVENT_IPU_CORE0_DONE3 356
+#define CMDQ_EVENT_IPU_CORE1_DONE0 385
+#define CMDQ_EVENT_IPU_CORE1_DONE1 386
+#define CMDQ_EVENT_IPU_CORE1_DONE2 387
+#define CMDQ_EVENT_IPU_CORE1_DONE3 388
+
+#endif
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 03/12] dt-binding: gce: add binding for gce subsys property
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 01/12] dt-binding: gce: remove thread-num property Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 02/12] dt-binding: gce: add gce header file for mt8183 Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-17 1:55 ` CK Hu
2019-05-16 9:02 ` [PATCH v6 04/12] dt-binding: gce: add binding for gce event property Bibby Hsieh
` (8 subsequent siblings)
11 siblings, 1 reply; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
tcmdq driver provide a function that get the relationship
of sub system number from device node for client.
add specification for #subsys-cells, mediatek,gce-subsys.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
.../devicetree/bindings/mailbox/mtk-gce.txt | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
index 1f7f8f2a3f49..dceab63ccd06 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -21,11 +21,19 @@ Required properties:
priority: Priority of GCE thread.
atomic_exec: GCE processing continuous packets of commands in atomic
way.
+- #subsys-cells: Should be 3.
+ <&phandle subsys_number start_offset size>
+ phandle: Label name of a gce node.
+ subsys_number: specify the sub-system id which is corresponding
+ to the register address.
+ start_offset: the start offset of register address that GCE can access.
+ size: the total size of register address that GCE can access.
Required properties for a client device:
- mboxes: Client use mailbox to communicate with GCE, it should have this
property and list of phandle, mailbox specifiers.
-- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
+Optional properties for a client device:
+- mediatek,gce-client-reg: u32, specify the sub-system id which is corresponding
to the register address.
Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
@@ -40,6 +48,7 @@ Example:
clocks = <&infracfg CLK_INFRA_GCE>;
clock-names = "gce";
#mbox-cells = <3>;
+ #subsys-cells = <3>;
};
Example for a client device:
@@ -48,9 +57,9 @@ Example for a client device:
compatible = "mediatek,mt8173-mmsys";
mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
<&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
- mediatek,gce-subsys = <SUBSYS_1400XXXX>;
mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
CMDQ_EVENT_MUTEX1_STREAM_EOF>;
-
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
+ <&gce SUBSYS_1401XXXX 0x2000 0x100>;
...
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v6 03/12] dt-binding: gce: add binding for gce subsys property
2019-05-16 9:02 ` [PATCH v6 03/12] dt-binding: gce: add binding for gce subsys property Bibby Hsieh
@ 2019-05-17 1:55 ` CK Hu
0 siblings, 0 replies; 18+ messages in thread
From: CK Hu @ 2019-05-17 1:55 UTC (permalink / raw)
To: Bibby Hsieh
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, Jassi Brar, linux-kernel,
Daniel Kurtz, Houlong Wei, YT Shen, Rob Herring, linux-mediatek,
Dennis-YC Hsieh, Sascha Hauer, Matthias Brugger, Jiaguang Zhang,
linux-arm-kernel, ginny.chen
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> tcmdq driver provide a function that get the relationship
What is 'tcmdq'?
> of sub system number from device node for client.
> add specification for #subsys-cells, mediatek,gce-subsys.
The property name is mediatek,gce-client-reg.
Regards,
CK
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> .../devicetree/bindings/mailbox/mtk-gce.txt | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> index 1f7f8f2a3f49..dceab63ccd06 100644
> --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> @@ -21,11 +21,19 @@ Required properties:
> priority: Priority of GCE thread.
> atomic_exec: GCE processing continuous packets of commands in atomic
> way.
> +- #subsys-cells: Should be 3.
> + <&phandle subsys_number start_offset size>
> + phandle: Label name of a gce node.
> + subsys_number: specify the sub-system id which is corresponding
> + to the register address.
> + start_offset: the start offset of register address that GCE can access.
> + size: the total size of register address that GCE can access.
>
> Required properties for a client device:
> - mboxes: Client use mailbox to communicate with GCE, it should have this
> property and list of phandle, mailbox specifiers.
> -- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
> +Optional properties for a client device:
> +- mediatek,gce-client-reg: u32, specify the sub-system id which is corresponding
> to the register address.
>
> Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
> @@ -40,6 +48,7 @@ Example:
> clocks = <&infracfg CLK_INFRA_GCE>;
> clock-names = "gce";
> #mbox-cells = <3>;
> + #subsys-cells = <3>;
> };
>
> Example for a client device:
> @@ -48,9 +57,9 @@ Example for a client device:
> compatible = "mediatek,mt8173-mmsys";
> mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
> <&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
> - mediatek,gce-subsys = <SUBSYS_1400XXXX>;
> mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
> CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> -
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
> + <&gce SUBSYS_1401XXXX 0x2000 0x100>;
> ...
> };
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 04/12] dt-binding: gce: add binding for gce event property
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (2 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 03/12] dt-binding: gce: add binding for gce subsys property Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-24 21:54 ` Rob Herring
2019-05-16 9:02 ` [PATCH v6 05/12] mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data Bibby Hsieh
` (7 subsequent siblings)
11 siblings, 1 reply; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
Client hardware would send event to GCE hardware,
mediatek,gce-event-names and mediatek,gce-events
can be used to present the event.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
index dceab63ccd06..265bb58da7bd 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -35,6 +35,8 @@ Required properties for a client device:
Optional properties for a client device:
- mediatek,gce-client-reg: u32, specify the sub-system id which is corresponding
to the register address.
+- mediatek,gce-events: u32, the event number defined in
+ 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'.
Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
@@ -57,8 +59,8 @@ Example for a client device:
compatible = "mediatek,mt8173-mmsys";
mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
<&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
- mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
- CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
<&gce SUBSYS_1401XXXX 0x2000 0x100>;
...
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v6 04/12] dt-binding: gce: add binding for gce event property
2019-05-16 9:02 ` [PATCH v6 04/12] dt-binding: gce: add binding for gce event property Bibby Hsieh
@ 2019-05-24 21:54 ` Rob Herring
0 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2019-05-24 21:54 UTC (permalink / raw)
To: Bibby Hsieh
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, Jassi Brar, linux-kernel,
Daniel Kurtz, Houlong Wei, YT Shen, CK HU, linux-mediatek,
Dennis-YC Hsieh, Sascha Hauer, Matthias Brugger, Jiaguang Zhang,
linux-arm-kernel, ginny.chen
On Thu, May 16, 2019 at 05:02:16PM +0800, Bibby Hsieh wrote:
> Client hardware would send event to GCE hardware,
> mediatek,gce-event-names and mediatek,gce-events
We removed mediatek,gce-event-names?
> can be used to present the event.
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> index dceab63ccd06..265bb58da7bd 100644
> --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> @@ -35,6 +35,8 @@ Required properties for a client device:
> Optional properties for a client device:
> - mediatek,gce-client-reg: u32, specify the sub-system id which is corresponding
> to the register address.
> +- mediatek,gce-events: u32, the event number defined in
> + 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'.
This and the example don't match. Is it an u32 or an array of u32? If
the latter, how many elements?
>
> Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
> or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
> @@ -57,8 +59,8 @@ Example for a client device:
> compatible = "mediatek,mt8173-mmsys";
> mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
> <&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
> - mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
> - CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
> + <CMDQ_EVENT_MDP_RSZ0_SOF>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
> <&gce SUBSYS_1401XXXX 0x2000 0x100>;
> ...
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 05/12] mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (3 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 04/12] dt-binding: gce: add binding for gce event property Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 06/12] mailbox: mediatek: cmdq: support mt8183 gce function Bibby Hsieh
` (6 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
The interrupt mask and thread number has positive correlation,
so we move the CMDQ_IRQ_MASK into cmdq driver data and calculate
it by thread number.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 22811784dc7d..87617dc7504d 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -17,7 +17,6 @@
#include <linux/of_device.h>
#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
-#define CMDQ_IRQ_MASK 0xffff
#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
#define CMDQ_CURR_IRQ_STATUS 0x10
@@ -71,6 +70,7 @@ struct cmdq {
void __iomem *base;
u32 irq;
u32 thread_nr;
+ u32 irq_mask;
struct cmdq_thread *thread;
struct clk *clock;
bool suspended;
@@ -284,11 +284,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev)
unsigned long irq_status, flags = 0L;
int bit;
- irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;
- if (!(irq_status ^ CMDQ_IRQ_MASK))
+ irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
+ if (!(irq_status ^ cmdq->irq_mask))
return IRQ_NONE;
- for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) {
+ for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
struct cmdq_thread *thread = &cmdq->thread[bit];
spin_lock_irqsave(&thread->chan->lock, flags);
@@ -472,6 +472,9 @@ static int cmdq_probe(struct platform_device *pdev)
dev_err(dev, "failed to get irq\n");
return -EINVAL;
}
+
+ cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
+ cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
"mtk_cmdq", cmdq);
if (err < 0) {
@@ -488,7 +491,6 @@ static int cmdq_probe(struct platform_device *pdev)
return PTR_ERR(cmdq->clock);
}
- cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
cmdq->mbox.dev = dev;
cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
sizeof(*cmdq->mbox.chans), GFP_KERNEL);
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 06/12] mailbox: mediatek: cmdq: support mt8183 gce function
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (4 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 05/12] mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 07/12] soc: mediatek: cmdq: clear the event in cmdq initial flow Bibby Hsieh
` (5 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
add mt8183 compatible name for supporting gce function
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 87617dc7504d..6db1e2dd2dea 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -538,6 +538,7 @@ static const struct dev_pm_ops cmdq_pm_ops = {
static const struct of_device_id cmdq_of_ids[] = {
{.compatible = "mediatek,mt8173-gce", .data = (void *)16},
+ {.compatible = "mediatek,mt8183-gce", .data = (void *)24},
{}
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 07/12] soc: mediatek: cmdq: clear the event in cmdq initial flow
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (5 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 06/12] mailbox: mediatek: cmdq: support mt8183 gce function Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 08/12] soc: mediatek: cmdq: define the instruction struct Bibby Hsieh
` (4 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
GCE hardware stored event information in own internal sysram,
if the initial value in those sysram is not zero value
it will cause a situation that gce can wait the event immediately
after client ask gce to wait event but not really trigger the
corresponding hardware.
In order to make sure that the wait event function is
exactly correct, we need to clear the sysram value in
cmdq initial flow.
Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver")
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 5 +++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++
include/linux/soc/mediatek/mtk-cmdq.h | 3 ---
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 6db1e2dd2dea..2c1b80d82c3a 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -20,6 +20,7 @@
#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
#define CMDQ_CURR_IRQ_STATUS 0x10
+#define CMDQ_SYNC_TOKEN_UPDATE 0x68
#define CMDQ_THR_SLOT_CYCLES 0x30
#define CMDQ_THR_BASE 0x100
#define CMDQ_THR_SIZE 0x80
@@ -103,8 +104,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread)
static void cmdq_init(struct cmdq *cmdq)
{
+ int i;
+
WARN_ON(clk_enable(cmdq->clock) < 0);
writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
+ for (i = 0; i <= CMDQ_MAX_EVENT; i++)
+ writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
clk_disable(cmdq->clock);
}
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index ccb73422c2fa..911475da7a53 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -19,6 +19,8 @@
#define CMDQ_WFE_UPDATE BIT(31)
#define CMDQ_WFE_WAIT BIT(15)
#define CMDQ_WFE_WAIT_VALUE 0x1
+/** cmdq event maximum */
+#define CMDQ_MAX_EVENT 0x3ff
/*
* CMDQ_CODE_MASK:
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 54ade13a9b15..4e8899972db4 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -13,9 +13,6 @@
#define CMDQ_NO_TIMEOUT 0xffffffffu
-/** cmdq event maximum */
-#define CMDQ_MAX_EVENT 0x3ff
-
struct cmdq_pkt;
struct cmdq_client {
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 08/12] soc: mediatek: cmdq: define the instruction struct
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (6 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 07/12] soc: mediatek: cmdq: clear the event in cmdq initial flow Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-17 3:32 ` CK Hu
2019-05-16 9:02 ` [PATCH v6 09/12] soc: mediatek: cmdq: add polling function Bibby Hsieh
` (3 subsequent siblings)
11 siblings, 1 reply; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
Define a instruction structure for gce driver to append command.
This structure can make the client's code more readability.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 113 +++++++++++++++--------
include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
include/linux/soc/mediatek/mtk-cmdq.h | 14 +--
3 files changed, 84 insertions(+), 45 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index ff9fef5a032b..17ee8196fb3d 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -9,12 +9,24 @@
#include <linux/mailbox_controller.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
-#define CMDQ_ARG_A_WRITE_MASK 0xffff
#define CMDQ_WRITE_ENABLE_MASK BIT(0)
#define CMDQ_EOC_IRQ_EN BIT(0)
#define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
<< 32 | CMDQ_EOC_IRQ_EN)
+struct cmdq_instruction {
+ union {
+ u32 value;
+ u32 mask;
+ };
+ union {
+ u16 offset;
+ u16 event;
+ };
+ u8 subsys;
+ u8 op;
+};
+
static void cmdq_client_timeout(struct timer_list *t)
{
struct cmdq_client *client = from_timer(client, t, timer);
@@ -110,10 +122,8 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
}
EXPORT_SYMBOL(cmdq_pkt_destroy);
-static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
- u32 arg_a, u32 arg_b)
+static struct cmdq_instruction *cmdq_pkt_append_command(struct cmdq_pkt *pkt)
{
- u64 *cmd_ptr;
if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
/*
@@ -127,81 +137,108 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
pkt->cmd_buf_size += CMDQ_INST_SIZE;
WARN_ONCE(1, "%s: buffer size %u is too small !\n",
__func__, (u32)pkt->buf_size);
- return -ENOMEM;
+ return NULL;
}
- cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
- (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
+
pkt->cmd_buf_size += CMDQ_INST_SIZE;
- return 0;
+ return pkt->va_base + pkt->cmd_buf_size - CMDQ_INST_SIZE;
}
-int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset)
+int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
{
- u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
- (subsys << CMDQ_SUBSYS_SHIFT);
+ struct cmdq_instruction *inst;
+
+ inst = cmdq_pkt_append_command(pkt);
+ if (!inst)
+ return -ENOMEM;
+
+ inst->op = CMDQ_CODE_WRITE;
+ inst->value = value;
+ inst->offset = offset;
+ inst->subsys = subsys;
- return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
+ return 0;
}
EXPORT_SYMBOL(cmdq_pkt_write);
-int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
- u32 subsys, u32 offset, u32 mask)
+int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset,
+ u32 value, u32 mask)
{
+ struct cmdq_instruction *inst;
u32 offset_mask = offset;
- int err = 0;
if (mask != 0xffffffff) {
- err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
+ inst = cmdq_pkt_append_command(pkt);
+ if (!inst)
+ return -ENOMEM;
+
+ inst->op = CMDQ_CODE_MASK;
+ inst->mask = ~mask;
offset_mask |= CMDQ_WRITE_ENABLE_MASK;
}
- err |= cmdq_pkt_write(pkt, value, subsys, offset_mask);
- return err;
+ return cmdq_pkt_write(pkt, subsys, offset_mask, value);
}
EXPORT_SYMBOL(cmdq_pkt_write_mask);
-int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event)
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
{
- u32 arg_b;
+ struct cmdq_instruction *inst;
if (event >= CMDQ_MAX_EVENT)
return -EINVAL;
- /*
- * WFE arg_b
- * bit 0-11: wait value
- * bit 15: 1 - wait, 0 - no wait
- * bit 16-27: update value
- * bit 31: 1 - update, 0 - no update
- */
- arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
+ inst = cmdq_pkt_append_command(pkt);
+ if (!inst)
+ return -ENOMEM;
+
+ inst->op = CMDQ_CODE_WFE;
+ inst->value = CMDQ_WFE_OPTION;
+ inst->event = event;
- return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, arg_b);
+ return 0;
}
EXPORT_SYMBOL(cmdq_pkt_wfe);
-int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event)
+int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
{
+ struct cmdq_instruction *inst;
+
if (event >= CMDQ_MAX_EVENT)
return -EINVAL;
- return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event,
- CMDQ_WFE_UPDATE);
+ inst = cmdq_pkt_append_command(pkt);
+ if (!inst)
+ return -ENOMEM;
+
+ inst->op = CMDQ_CODE_WFE;
+ inst->value = CMDQ_WFE_UPDATE;
+ inst->event = event;
+
+ return 0;
}
EXPORT_SYMBOL(cmdq_pkt_clear_event);
static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
{
- int err;
+ struct cmdq_instruction *inst;
+
+ inst = cmdq_pkt_append_command(pkt);
+ if (!inst)
+ return -ENOMEM;
- /* insert EOC and generate IRQ for each command iteration */
- err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN);
+ inst->op = CMDQ_CODE_EOC;
+ inst->value = CMDQ_EOC_IRQ_EN;
- /* JUMP to end */
- err |= cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS);
+ inst = cmdq_pkt_append_command(pkt);
+ if (!inst)
+ return -ENOMEM;
+
+ inst->op = CMDQ_CODE_JUMP;
+ inst->value = CMDQ_JUMP_PASS;
- return err;
+ return 0;
}
static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data)
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index 911475da7a53..f21801d32a3a 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -19,6 +19,8 @@
#define CMDQ_WFE_UPDATE BIT(31)
#define CMDQ_WFE_WAIT BIT(15)
#define CMDQ_WFE_WAIT_VALUE 0x1
+#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
+ CMDQ_WFE_WAIT_VALUE)
/** cmdq event maximum */
#define CMDQ_MAX_EVENT 0x3ff
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 4e8899972db4..52f69c8db8de 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -60,26 +60,26 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt);
/**
* cmdq_pkt_write() - append write command to the CMDQ packet
* @pkt: the CMDQ packet
- * @value: the specified target register value
* @subsys: the CMDQ sub system code
* @offset: register offset from CMDQ sub system
+ * @value: the specified target register value
*
* Return: 0 for success; else the error code is returned
*/
-int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset);
+int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
/**
* cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
* @pkt: the CMDQ packet
- * @value: the specified target register value
* @subsys: the CMDQ sub system code
* @offset: register offset from CMDQ sub system
+ * @value: the specified target register value
* @mask: the specified target register mask
*
* Return: 0 for success; else the error code is returned
*/
-int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
- u32 subsys, u32 offset, u32 mask);
+int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset,
+ u32 value, u32 mask);
/**
* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
@@ -88,7 +88,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
*
* Return: 0 for success; else the error code is returned
*/
-int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
/**
* cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
@@ -97,7 +97,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
*
* Return: 0 for success; else the error code is returned
*/
-int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event);
+int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
/**
* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v6 08/12] soc: mediatek: cmdq: define the instruction struct
2019-05-16 9:02 ` [PATCH v6 08/12] soc: mediatek: cmdq: define the instruction struct Bibby Hsieh
@ 2019-05-17 3:32 ` CK Hu
0 siblings, 0 replies; 18+ messages in thread
From: CK Hu @ 2019-05-17 3:32 UTC (permalink / raw)
To: Bibby Hsieh
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, Jassi Brar, linux-kernel,
Daniel Kurtz, Houlong Wei, YT Shen, Rob Herring, linux-mediatek,
Dennis-YC Hsieh, Sascha Hauer, Matthias Brugger, Jiaguang Zhang,
linux-arm-kernel, ginny.chen
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> Define a instruction structure for gce driver to append command.
> This structure can make the client's code more readability.
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 113 +++++++++++++++--------
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> include/linux/soc/mediatek/mtk-cmdq.h | 14 +--
> 3 files changed, 84 insertions(+), 45 deletions(-)
>
[snip]
>
> /**
> * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
> * @pkt: the CMDQ packet
> - * @value: the specified target register value
> * @subsys: the CMDQ sub system code
> * @offset: register offset from CMDQ sub system
> + * @value: the specified target register value
> * @mask: the specified target register mask
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
> - u32 subsys, u32 offset, u32 mask);
> +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset,
> + u32 value, u32 mask);
You have do two things for this interface: one is reordering the
parameter, another one is changing type of subsys from u32 to u8.
Define the instruction struct is not necessary to change the order and
type. I would like you to separate these two things to another patches.
So the patch sequence may be:
1. Reorder parameter of cmdq_pkt_write_mask()
2. Change subsys type to u8
3. define the instruction struct
Regards,
CK
>
> /**
> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
> @@ -88,7 +88,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
>
> /**
> * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
> @@ -97,7 +97,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event);
> +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
>
> /**
> * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 09/12] soc: mediatek: cmdq: add polling function
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (7 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 08/12] soc: mediatek: cmdq: define the instruction struct Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 10/12] soc: mediatek: cmdq: add cmdq_dev_get_subsys function Bibby Hsieh
` (2 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
add polling function in cmdq helper functions
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 28 ++++++++++++++++++++++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
include/linux/soc/mediatek/mtk-cmdq.h | 15 +++++++++++++
3 files changed, 44 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 17ee8196fb3d..a53cdd71cfc2 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -220,6 +220,34 @@ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
}
EXPORT_SYMBOL(cmdq_pkt_clear_event);
+int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
+ u16 offset, u32 value, u32 mask)
+{
+ struct cmdq_instruction *inst;
+
+ if (mask != 0xffffffff) {
+ inst = cmdq_pkt_append_command(pkt);
+ if (!inst)
+ return -ENOMEM;
+
+ inst->op = CMDQ_CODE_MASK;
+ inst->value = ~mask;
+ offset = offset | 0x1;
+ }
+
+ inst = cmdq_pkt_append_command(pkt);
+ if (!inst)
+ return -ENOMEM;
+
+ inst->op = CMDQ_CODE_POLL;
+ inst->value = value;
+ inst->offset = offset;
+ inst->subsys = subsys;
+
+ return 0;
+}
+EXPORT_SYMBOL(cmdq_pkt_poll);
+
static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
{
struct cmdq_instruction *inst;
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index f21801d32a3a..1dfd5ed5c8c5 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -46,6 +46,7 @@
enum cmdq_code {
CMDQ_CODE_MASK = 0x02,
CMDQ_CODE_WRITE = 0x04,
+ CMDQ_CODE_POLL = 0x08,
CMDQ_CODE_JUMP = 0x10,
CMDQ_CODE_WFE = 0x20,
CMDQ_CODE_EOC = 0x40,
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 52f69c8db8de..0651a0bffa54 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -99,6 +99,21 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
*/
int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
+/**
+ * cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to
+ * execute an instruction that wait for a specified hardware
+ * register to check for the value. All GCE hardware
+ * threads will be blocked by this instruction.
+ * @pkt: the CMDQ packet
+ * @subsys: the CMDQ sub system code
+ * @offset: register offset from CMDQ sub system
+ * @value: the specified target register value
+ * @mask: the specified target register mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
+ u16 offset, u32 value, u32 mask);
/**
* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
* packet and call back at the end of done packet
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v6 10/12] soc: mediatek: cmdq: add cmdq_dev_get_subsys function
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (8 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 09/12] soc: mediatek: cmdq: add polling function Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-17 1:43 ` CK Hu
2019-05-16 9:02 ` [PATCH v6 11/12] soc: mediatek: cmdq: add cmdq_dev_get_event function Bibby Hsieh
2019-05-16 9:02 ` [PATCH v6 12/12] arm64: dts: add gce node for mt8183 Bibby Hsieh
11 siblings, 1 reply; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
GCE cannot know the register base address, this function
can help cmdq client to get the relationship of subsys
and register base address.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 25 +++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 18 ++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index a53cdd71cfc2..a64060a34e01 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -27,6 +27,31 @@ struct cmdq_instruction {
u8 op;
};
+struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx)
+{
+ struct cmdq_subsys *subsys;
+ struct of_phandle_args spec;
+
+ subsys = devm_kzalloc(dev, sizeof(*subsys), GFP_KERNEL);
+ if (!subsys)
+ return NULL;
+
+ if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg",
+ "#subsys-cells", idx, &spec)) {
+ dev_err(dev, "can't parse gce-client-reg property");
+
+ return (struct cmdq_subsys *)-ENODEV;
+ }
+
+ subsys->id = spec.args[0];
+ subsys->offset = spec.args[1];
+ subsys->size = spec.args[2];
+ of_node_put(spec.np);
+
+ return subsys;
+}
+EXPORT_SYMBOL(cmdq_dev_get_subsys);
+
static void cmdq_client_timeout(struct timer_list *t)
{
struct cmdq_client *client = from_timer(client, t, timer);
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 0651a0bffa54..574006c5cd76 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -15,6 +15,12 @@
struct cmdq_pkt;
+struct cmdq_subsys {
+ u8 id;
+ u16 offset;
+ u16 size;
+};
+
struct cmdq_client {
spinlock_t lock;
u32 pkt_cnt;
@@ -142,4 +148,16 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
*/
int cmdq_pkt_flush(struct cmdq_pkt *pkt);
+/**
+ * cmdq_dev_get_subsys() - parse sub system from the device node of CMDQ client
+ * @dev: device of CMDQ mailbox client
+ * @idx: the index of desired subsys
+ *
+ * Return: CMDQ subsys pointer
+ *
+ * Help CMDQ client pasing the sub system number
+ * from the device node of CMDQ client.
+ */
+struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx);
+
#endif /* __MTK_CMDQ_H__ */
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v6 10/12] soc: mediatek: cmdq: add cmdq_dev_get_subsys function
2019-05-16 9:02 ` [PATCH v6 10/12] soc: mediatek: cmdq: add cmdq_dev_get_subsys function Bibby Hsieh
@ 2019-05-17 1:43 ` CK Hu
0 siblings, 0 replies; 18+ messages in thread
From: CK Hu @ 2019-05-17 1:43 UTC (permalink / raw)
To: Bibby Hsieh
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, Jassi Brar, linux-kernel,
Daniel Kurtz, Houlong Wei, YT Shen, Rob Herring, linux-mediatek,
Dennis-YC Hsieh, Sascha Hauer, Matthias Brugger, Jiaguang Zhang,
linux-arm-kernel, ginny.chen
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the relationship of subsys
> and register base address.
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 25 +++++++++++++++++++++++++
> include/linux/soc/mediatek/mtk-cmdq.h | 18 ++++++++++++++++++
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index a53cdd71cfc2..a64060a34e01 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -27,6 +27,31 @@ struct cmdq_instruction {
> u8 op;
> };
>
> +struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx)
> +{
> + struct cmdq_subsys *subsys;
> + struct of_phandle_args spec;
> +
> + subsys = devm_kzalloc(dev, sizeof(*subsys), GFP_KERNEL);
> + if (!subsys)
> + return NULL;
> +
> + if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg",
> + "#subsys-cells", idx, &spec)) {
> + dev_err(dev, "can't parse gce-client-reg property");
print the idx info.
> +
I think you should free the buffer you allocate. Don't expect this
function is called in caller's probe function.
> + return (struct cmdq_subsys *)-ENODEV;
Why not return NULL?
> + }
> +
> + subsys->id = spec.args[0];
> + subsys->offset = spec.args[1];
> + subsys->size = spec.args[2];
> + of_node_put(spec.np);
> +
> + return subsys;
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_subsys);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index 0651a0bffa54..574006c5cd76 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -15,6 +15,12 @@
>
> struct cmdq_pkt;
>
> +struct cmdq_subsys {
May be cmdq_client_reg.
> + u8 id;
May be subsys.
Regards,
CK
> + u16 offset;
> + u16 size;
> +};
> +
> struct cmdq_client {
> spinlock_t lock;
> u32 pkt_cnt;
> @@ -142,4 +148,16 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
> */
> int cmdq_pkt_flush(struct cmdq_pkt *pkt);
>
> +/**
> + * cmdq_dev_get_subsys() - parse sub system from the device node of CMDQ client
> + * @dev: device of CMDQ mailbox client
> + * @idx: the index of desired subsys
> + *
> + * Return: CMDQ subsys pointer
> + *
> + * Help CMDQ client pasing the sub system number
> + * from the device node of CMDQ client.
> + */
> +struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx);
> +
> #endif /* __MTK_CMDQ_H__ */
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 11/12] soc: mediatek: cmdq: add cmdq_dev_get_event function
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (9 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 10/12] soc: mediatek: cmdq: add cmdq_dev_get_subsys function Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
2019-05-16 10:27 ` CK Hu
2019-05-16 9:02 ` [PATCH v6 12/12] arm64: dts: add gce node for mt8183 Bibby Hsieh
11 siblings, 1 reply; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
When client ask gce to clear or wait for event,
client need to pass event number to the API.
We suggest client store the event information in device node,
so we provide an API for client parse the event property.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 18 ++++++++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 12 ++++++++++++
2 files changed, 30 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index a64060a34e01..e9658063c3d4 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -52,6 +52,24 @@ struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx)
}
EXPORT_SYMBOL(cmdq_dev_get_subsys);
+s32 cmdq_dev_get_event(struct device *dev, int index)
+{
+ s32 result;
+
+ if (!dev)
+ return -EINVAL;
+
+ if (of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+ index, &result)) {
+ dev_err(dev, "can't parse gce-events property");
+
+ return -ENODEV;
+ }
+
+ return result;
+}
+EXPORT_SYMBOL(cmdq_dev_get_event);
+
static void cmdq_client_timeout(struct timer_list *t)
{
struct cmdq_client *client = from_timer(client, t, timer);
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 574006c5cd76..525713bf79b5 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -160,4 +160,16 @@ int cmdq_pkt_flush(struct cmdq_pkt *pkt);
*/
struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx);
+/**
+ * cmdq_dev_get_event() - parse event from the device node of CMDQ client
+ * @dev: device of CMDQ mailbox client
+ * @index: the index of desired event
+ *
+ * Return: CMDQ event number
+ *
+ * Help CMDQ client pasing the event number
+ * from the device node of CMDQ client.
+ */
+s32 cmdq_dev_get_event(struct device *dev, int index);
+
#endif /* __MTK_CMDQ_H__ */
--
2.18.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v6 11/12] soc: mediatek: cmdq: add cmdq_dev_get_event function
2019-05-16 9:02 ` [PATCH v6 11/12] soc: mediatek: cmdq: add cmdq_dev_get_event function Bibby Hsieh
@ 2019-05-16 10:27 ` CK Hu
0 siblings, 0 replies; 18+ messages in thread
From: CK Hu @ 2019-05-16 10:27 UTC (permalink / raw)
To: Bibby Hsieh
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, Jassi Brar, linux-kernel,
Daniel Kurtz, Houlong Wei, YT Shen, Rob Herring, linux-mediatek,
Dennis-YC Hsieh, Sascha Hauer, Matthias Brugger, Jiaguang Zhang,
linux-arm-kernel, ginny.chen
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> When client ask gce to clear or wait for event,
> client need to pass event number to the API.
> We suggest client store the event information in device node,
> so we provide an API for client parse the event property.
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 18 ++++++++++++++++++
> include/linux/soc/mediatek/mtk-cmdq.h | 12 ++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index a64060a34e01..e9658063c3d4 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -52,6 +52,24 @@ struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx)
> }
> EXPORT_SYMBOL(cmdq_dev_get_subsys);
>
> +s32 cmdq_dev_get_event(struct device *dev, int index)
> +{
> + s32 result;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + if (of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
> + index, &result)) {
> + dev_err(dev, "can't parse gce-events property");
> +
> + return -ENODEV;
> + }
> +
> + return result;
This function just does one thing, so client driver could just directly
call of_property_read_u32_index().
Regards,
CK
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_event);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index 574006c5cd76..525713bf79b5 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -160,4 +160,16 @@ int cmdq_pkt_flush(struct cmdq_pkt *pkt);
> */
> struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx);
>
> +/**
> + * cmdq_dev_get_event() - parse event from the device node of CMDQ client
> + * @dev: device of CMDQ mailbox client
> + * @index: the index of desired event
> + *
> + * Return: CMDQ event number
> + *
> + * Help CMDQ client pasing the event number
> + * from the device node of CMDQ client.
> + */
> +s32 cmdq_dev_get_event(struct device *dev, int index);
> +
> #endif /* __MTK_CMDQ_H__ */
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 12/12] arm64: dts: add gce node for mt8183
2019-05-16 9:02 [PATCH v6 00/12] support gce on mt8183 platform Bibby Hsieh
` (10 preceding siblings ...)
2019-05-16 9:02 ` [PATCH v6 11/12] soc: mediatek: cmdq: add cmdq_dev_get_event function Bibby Hsieh
@ 2019-05-16 9:02 ` Bibby Hsieh
11 siblings, 0 replies; 18+ messages in thread
From: Bibby Hsieh @ 2019-05-16 9:02 UTC (permalink / raw)
To: Jassi Brar, Matthias Brugger, Rob Herring, CK HU
Cc: devicetree, Nicolas Boichat, Philipp Zabel, srv_heupstream,
Daoyuan Huang, Sascha Hauer, linux-kernel, Daniel Kurtz,
Houlong Wei, linux-mediatek, Dennis-YC Hsieh, Sascha Hauer,
YT Shen, Jiaguang Zhang, Bibby Hsieh, linux-arm-kernel,
ginny.chen
add gce device node for mt8183
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index b36e37fcdfe3..d6d26fa32dd7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/gce/mt8183-gce.h>
#include "mt8183-pinfunc.h"
/ {
compatible = "mediatek,mt8183";
@@ -293,6 +294,16 @@
clock-names = "spi", "wrap";
};
+ gce: gce@10238000 {
+ compatible = "mediatek,mt8183-gce";
+ reg = <0 0x10238000 0 0x4000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
+ #mbox-cells = <3>;
+ #subsys-cells = <3>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8183-uart",
"mediatek,mt6577-uart";
--
2.18.0
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