* [PATCH] ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA
@ 2019-06-28 0:19 Marek Vasut
2019-07-01 14:59 ` Dinh Nguyen
0 siblings, 1 reply; 2+ messages in thread
From: Marek Vasut @ 2019-06-28 0:19 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Marek Vasut, Dinh Nguyen
Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index 622cc7cc1471..a060718758b6 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -96,10 +96,14 @@
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1860>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1860>;
};
};
};
--
2.20.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA
2019-06-28 0:19 [PATCH] ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA Marek Vasut
@ 2019-07-01 14:59 ` Dinh Nguyen
0 siblings, 0 replies; 2+ messages in thread
From: Dinh Nguyen @ 2019-07-01 14:59 UTC (permalink / raw)
To: Marek Vasut, linux-arm-kernel
On 6/27/19 7:19 PM, Marek Vasut wrote:
> Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
> to minimum (-420 ps), to improve signal integrity.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> ---
> arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> index 622cc7cc1471..a060718758b6 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> @@ -96,10 +96,14 @@
Applied!
Thanks,
Dinh
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^ permalink raw reply [flat|nested] 2+ messages in thread
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2019-06-28 0:19 [PATCH] ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA Marek Vasut
2019-07-01 14:59 ` Dinh Nguyen
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