From: Will Deacon <will@kernel.org>
To: Julien Thierry <julien.thierry@arm.com>
Cc: mark.rutland@arm.com, peterz@infradead.org,
Catalin Marinas <catalin.marinas@arm.com>,
will.deacon@arm.com, acme@kernel.org,
alexander.shishkin@linux.intel.com, mingo@redhat.com,
namhyung@kernel.org, sthotton@marvell.com, jolsa@redhat.com,
linux-arm-kernel@lists.infradead.org, liwei391@huawei.com
Subject: Re: [PATCH v4 2/9] arm64: perf: Remove PMU locking
Date: Thu, 1 Aug 2019 13:58:22 +0100 [thread overview]
Message-ID: <20190801125821.23wt657bfs2k536f@willie-the-truck> (raw)
In-Reply-To: <1563351432-55652-3-git-send-email-julien.thierry@arm.com>
On Wed, Jul 17, 2019 at 09:17:05AM +0100, Julien Thierry wrote:
> Since the PMU driver uses direct registers for counter
> setup/manipulation, locking around these operations is no longer needed.
>
> For operations that can be called with interrupts enabled, preemption
> still needs to be disabled to ensure the programming of the PMU is
> done on the expected CPU and not migrated mid-programming.
>
> Signed-off-by: Julien Thierry <julien.thierry@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Cc: Jiri Olsa <jolsa@redhat.com>
> Cc: Namhyung Kim <namhyung@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
> arch/arm64/kernel/perf_event.c | 30 ++----------------------------
> 1 file changed, 2 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 838758f..0e2cf5d 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -673,15 +673,10 @@ static inline u32 armv8pmu_getreset_flags(void)
>
> static void armv8pmu_enable_event(struct perf_event *event)
> {
> - unsigned long flags;
> - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
> - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
> -
> /*
> * Enable counter and interrupt, and set the counter to count
> * the event that we're interested in.
> */
> - raw_spin_lock_irqsave(&events->pmu_lock, flags);
>
> /*
> * Disable counter
> @@ -702,21 +697,10 @@ static void armv8pmu_enable_event(struct perf_event *event)
> * Enable counter
> */
> armv8pmu_enable_event_counter(event);
> -
> - raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
> }
With the implicit ISBs now removed by virtue of addressing the counter
register directly, what prevents the programming of the evtype being
reordered with respect to disabling/enabling the counter?
> static void armv8pmu_disable_event(struct perf_event *event)
> {
> - unsigned long flags;
> - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
> - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
> -
> - /*
> - * Disable counter and interrupt
> - */
> - raw_spin_lock_irqsave(&events->pmu_lock, flags);
> -
> /*
> * Disable counter
> */
> @@ -726,30 +710,20 @@ static void armv8pmu_disable_event(struct perf_event *event)
> * Disable interrupt for this counter
> */
> armv8pmu_disable_event_irq(event);
> -
> - raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
> }
>
> static void armv8pmu_start(struct arm_pmu *cpu_pmu)
> {
> - unsigned long flags;
> - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
> -
> - raw_spin_lock_irqsave(&events->pmu_lock, flags);
> + WARN_ON_ONCE(preemptible());
> /* Enable all counters */
> armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
> - raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
> }
>
> static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
> {
> - unsigned long flags;
> - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
> -
> - raw_spin_lock_irqsave(&events->pmu_lock, flags);
> + WARN_ON_ONCE(preemptible());
I don't think we need these WARN_ONs -- these are very much per-CPU
operations from the context of the perf core, so we'll be ok.
Will
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next prev parent reply other threads:[~2019-08-01 12:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-17 8:17 [PATCH v4 0/9] arm_pmu: Use NMI for perf interrupt Julien Thierry
2019-07-17 8:17 ` [PATCH v4 1/9] arm64: perf: avoid PMXEV* indirection Julien Thierry
2019-07-17 8:17 ` [PATCH v4 2/9] arm64: perf: Remove PMU locking Julien Thierry
2019-08-01 12:58 ` Will Deacon [this message]
2019-08-02 14:26 ` Julien Thierry
2019-07-17 8:17 ` [PATCH v4 3/9] arm: perf: save/resore pmsel Julien Thierry
2019-08-01 13:01 ` Will Deacon
2019-08-02 14:34 ` Julien Thierry
2019-07-17 8:17 ` [PATCH v4 4/9] arm: perf: Remove Remove PMU locking Julien Thierry
2019-08-01 13:06 ` Will Deacon
2019-08-02 14:36 ` Julien Thierry
2019-07-17 8:17 ` [PATCH v4 5/9] perf/arm_pmu: Move PMU lock to ARMv6 events Julien Thierry
2019-07-17 8:17 ` [PATCH v4 6/9] arm64: perf: Do not call irq_work_run in NMI context Julien Thierry
2019-08-01 13:06 ` Will Deacon
2019-08-02 14:43 ` Julien Thierry
2019-07-17 8:17 ` [PATCH v4 7/9] arm/arm64: kvm: pmu: Make overflow handler NMI safe Julien Thierry
2019-07-17 8:17 ` [PATCH v4 8/9] arm_pmu: Introduce pmu_irq_ops Julien Thierry
2019-07-17 8:17 ` [PATCH v4 9/9] arm_pmu: Use NMIs for PMU Julien Thierry
2019-07-30 9:11 ` Russell King - ARM Linux admin
2019-07-30 9:18 ` Julien Thierry
2019-07-30 9:28 ` Russell King - ARM Linux admin
2019-07-30 14:06 ` Julien Thierry
2019-07-17 9:02 ` [PATCH v4 0/9] arm_pmu: Use NMI for perf interrupt Julien Thierry
2019-07-30 9:05 ` Julien Thierry
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