From: Leo Yan <leo.yan@linaro.org>
To: Mike Leach <mike.leach@linaro.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
mathieu.poirier@linaro.org
Subject: Re: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters
Date: Wed, 28 Aug 2019 10:53:13 +0800 [thread overview]
Message-ID: <20190828025313.GC26133@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <20190819205720.24457-4-mike.leach@linaro.org>
On Mon, Aug 19, 2019 at 09:57:15PM +0100, Mike Leach wrote:
> TRCACATRn registers have match bits for secure and non-secure exception
> levels which are not accessible by the sysfs API.
> This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.
>
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
> .../coresight/coresight-etm4x-sysfs.c | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index fa1d6a938f6c..7eab5d7d0b62 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev,
> }
> static DEVICE_ATTR_RW(addr_context);
>
> +static ssize_t addr_exlevel_s_ns_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + u8 idx;
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + spin_lock(&drvdata->spinlock);
> + idx = config->addr_idx;
> + val = BMVAL(config->addr_acc[idx], 14, 8);
> + spin_unlock(&drvdata->spinlock);
> + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + u8 idx;
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + if (kstrtoul(buf, 16, &val))
> + return -EINVAL;
> +
> + spin_lock(&drvdata->spinlock);
> + idx = config->addr_idx;
> + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */
> + config->addr_acc[idx] &= ~(GENMASK(14, 8));
> + config->addr_acc[idx] |= (val << 8);
I think it needs to check if 'val' is out of bound, which only can have
value which is less than 7 bits (finally set for bit 8 to bit 14).
Just curious, if the CPU runs in non-secure mode (e.g. NS-EL1 in
kernel mode), does it have permission to access EXLEVEL_S field? I
don't see the spec give info for this.
Thanks,
Leo Yan
> + spin_unlock(&drvdata->spinlock);
> + return size;
> +}
> +static DEVICE_ATTR_RW(addr_exlevel_s_ns);
> +
> static ssize_t seq_idx_show(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
> &dev_attr_addr_stop.attr,
> &dev_attr_addr_ctxtype.attr,
> &dev_attr_addr_context.attr,
> + &dev_attr_addr_exlevel_s_ns.attr,
> &dev_attr_seq_idx.attr,
> &dev_attr_seq_state.attr,
> &dev_attr_seq_event.attr,
> --
> 2.17.1
>
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight
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next prev parent reply other threads:[~2019-08-28 2:53 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-19 20:57 [PATCH 0/8] coresight: etm4x: Fixes and updates for sysfs API Mike Leach
2019-08-19 20:57 ` [PATCH 1/8] coresight: etm4x: Fixes for ETM v4.4 architecture updates Mike Leach
2019-08-26 21:47 ` Mathieu Poirier
2019-08-27 10:12 ` Mike Leach
2019-08-27 19:19 ` Mathieu Poirier
2019-08-28 1:52 ` Leo Yan
2019-08-19 20:57 ` [PATCH 2/8] coresight: etm4x: Fix input validation for sysfs Mike Leach
2019-08-26 22:29 ` Mathieu Poirier
2019-08-28 2:42 ` Leo Yan
2019-08-19 20:57 ` [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters Mike Leach
2019-08-26 22:59 ` Mathieu Poirier
2019-08-27 10:55 ` Mike Leach
2019-08-27 17:57 ` Mathieu Poirier
2019-08-28 2:53 ` Leo Yan [this message]
2019-08-28 12:10 ` Mike Leach
2019-08-19 20:57 ` [PATCH 4/8] coresight: etm4x: Fix issues with start-stop logic Mike Leach
2019-08-28 3:17 ` Leo Yan
2019-08-28 12:40 ` Mike Leach
2019-08-19 20:57 ` [PATCH 5/8] coresight: etm4x: Improve usability of sysfs API Mike Leach
2019-08-27 21:35 ` Mathieu Poirier
2019-08-28 3:36 ` Leo Yan
2019-08-28 12:56 ` Mike Leach
2019-08-19 20:57 ` [PATCH 6/8] coresight: etm4x: Add view comparator settings API to sysfs Mike Leach
2019-08-27 21:40 ` Mathieu Poirier
2019-08-28 4:00 ` Leo Yan
2019-08-19 20:57 ` [PATCH 7/8] coresight: etm4x: Add missing single-shot control " Mike Leach
2019-08-27 22:27 ` Mathieu Poirier
2019-08-28 14:15 ` Mike Leach
2019-08-28 5:18 ` Leo Yan
2019-08-28 14:15 ` Mike Leach
2019-08-19 20:57 ` [PATCH 8/8] coresight: etm4x: docs: Additional documentation for ETM4x Mike Leach
2019-08-27 22:32 ` Mathieu Poirier
2019-08-27 22:34 ` Mathieu Poirier
2019-08-28 14:20 ` Mike Leach
2019-08-28 16:36 ` Mathieu Poirier
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