[PATCH 0/7] Replace Tegra FUSE API by nvmem API

[PATCH 0/7] Replace Tegra FUSE API by nvmem API

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The nvmem API provides a generic API to retrieve the kind of information
currently retrieved using the custom Tegra FUSE API. Convert the Tegra
FUSE driver to be an nvmem provider and export cells used by existing
drivers.

The three non-SoC drivers included in this series are meant to serve as
examples for how to use this. I'm not Cc'ing them to the subsystem
maintainers because the idea is to first merge the soc/tegra patches and
after that convert the consumers. Once the first patches are applied, I
will send out the consumers conversion patches to the respective
subsystems.

What's not included in this series is a cleanup patch that finally
removes the custom Tegra FUSE API. I'll follow up with that once these
patches have been applied.

Thierry

Thierry Reding (7):
  soc/tegra: fuse: Restore base on sysfs failure
  soc/tegra: fuse: Implement nvmem device
  soc/tegra: fuse: Add cell information
  soc/tegra: fuse: Register cell lookups for compatibility
  drm/nouveau: tegra: Use nvmem API
  phy: tegra: xusb: Use nvmem API
  thermal: tegra: Use nvmem API

 .../gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c   |  12 +-
 drivers/phy/tegra/xusb-tegra124.c             |  10 +-
 drivers/phy/tegra/xusb-tegra186.c             |   7 +-
 drivers/phy/tegra/xusb-tegra210.c             |  10 +-
 drivers/soc/tegra/fuse/fuse-tegra.c           | 193 +++++++++++++-----
 drivers/soc/tegra/fuse/fuse-tegra30.c         | 154 ++++++++++++++
 drivers/soc/tegra/fuse/fuse.h                 |   8 +
 drivers/thermal/tegra/soctherm-fuse.c         |  19 +-
 drivers/thermal/tegra/soctherm.c              |   4 +-
 drivers/thermal/tegra/soctherm.h              |   9 +-
 drivers/thermal/tegra/tegra124-soctherm.c     |   8 -
 drivers/thermal/tegra/tegra132-soctherm.c     |   8 -
 drivers/thermal/tegra/tegra210-soctherm.c     |   8 -
 13 files changed, 344 insertions(+), 106 deletions(-)

-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 1/7] soc/tegra: fuse: Restore base on sysfs failure

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Make sure to also restore the register base address on sysfs
registration failure.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/soc/tegra/fuse/fuse-tegra.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index 3eb44e65b326..6617a4bd11bb 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -146,20 +146,24 @@ static int tegra_fuse_probe(struct platform_device *pdev)
 
 	if (fuse->soc->probe) {
 		err = fuse->soc->probe(fuse);
-		if (err < 0) {
-			fuse->base = base;
-			return err;
-		}
+		if (err < 0)
+			goto restore;
 	}
 
 	if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size,
-				    fuse->soc->info))
-		return -ENODEV;
+				    fuse->soc->info)) {
+		err = -ENODEV;
+		goto restore;
+	}
 
 	/* release the early I/O memory mapping */
 	iounmap(base);
 
 	return 0;
+
+restore:
+	fuse->base = base;
+	return err;
 }
 
 static struct platform_driver tegra_fuse_driver = {
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 2/7] soc/tegra: fuse: Implement nvmem device

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The nvmem framework provides a generic infrastructure and API to access
the type of information stored in fuses such as the Tegra FUSE block.

Implement an nvmem device that can be used to access the information in
a more generic way to decouple consumers from the custom Tegra API and
to add a more formal way of creating the dependency between the FUSE
device and the consumers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/soc/tegra/fuse/fuse-tegra.c | 82 ++++++++++++-----------------
 drivers/soc/tegra/fuse/fuse.h       |  3 ++
 2 files changed, 38 insertions(+), 47 deletions(-)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index 6617a4bd11bb..3ce2138b278b 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -8,6 +8,8 @@
 #include <linux/kobject.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/nvmem-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
@@ -31,50 +33,6 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
 	[TEGRA_REVISION_A04]     = "A04",
 };
 
-static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset)
-{
-	u32 val;
-
-	val = fuse->read(fuse, round_down(offset, 4));
-	val >>= (offset % 4) * 8;
-	val &= 0xff;
-
-	return val;
-}
-
-static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
-			 struct bin_attribute *attr, char *buf,
-			 loff_t pos, size_t size)
-{
-	struct device *dev = kobj_to_dev(kobj);
-	struct tegra_fuse *fuse = dev_get_drvdata(dev);
-	int i;
-
-	if (pos < 0 || pos >= attr->size)
-		return 0;
-
-	if (size > attr->size - pos)
-		size = attr->size - pos;
-
-	for (i = 0; i < size; i++)
-		buf[i] = fuse_readb(fuse, pos + i);
-
-	return i;
-}
-
-static struct bin_attribute fuse_bin_attr = {
-	.attr = { .name = "fuse", .mode = S_IRUGO, },
-	.read = fuse_read,
-};
-
-static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size,
-				   const struct tegra_fuse_info *info)
-{
-	fuse_bin_attr.size = size;
-
-	return device_create_bin_file(dev, &fuse_bin_attr);
-}
-
 static const struct of_device_id car_match[] __initconst = {
 	{ .compatible = "nvidia,tegra20-car", },
 	{ .compatible = "nvidia,tegra30-car", },
@@ -115,9 +73,23 @@ static const struct of_device_id tegra_fuse_match[] = {
 	{ /* sentinel */ }
 };
 
+static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
+			   size_t bytes)
+{
+	unsigned int count = bytes / 4, i;
+	struct tegra_fuse *fuse = priv;
+	u32 *buffer = value;
+
+	for (i = 0; i < count; i++)
+		buffer[i] = fuse->read(fuse, offset + i * 4);
+
+	return 0;
+}
+
 static int tegra_fuse_probe(struct platform_device *pdev)
 {
 	void __iomem *base = fuse->base;
+	struct nvmem_config nvmem;
 	struct resource *res;
 	int err;
 
@@ -150,9 +122,25 @@ static int tegra_fuse_probe(struct platform_device *pdev)
 			goto restore;
 	}
 
-	if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size,
-				    fuse->soc->info)) {
-		err = -ENODEV;
+	memset(&nvmem, 0, sizeof(nvmem));
+	nvmem.dev = &pdev->dev;
+	nvmem.name = "fuse";
+	nvmem.id = -1;
+	nvmem.owner = THIS_MODULE;
+	nvmem.type = NVMEM_TYPE_OTP;
+	nvmem.read_only = true;
+	nvmem.root_only = true;
+	nvmem.reg_read = tegra_fuse_read;
+	nvmem.size = fuse->soc->info->size;
+	nvmem.word_size = 4;
+	nvmem.stride = 4;
+	nvmem.priv = fuse;
+
+	fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
+	if (IS_ERR(fuse->nvmem)) {
+		err = PTR_ERR(fuse->nvmem);
+		dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
+			err);
 		goto restore;
 	}
 
diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h
index 7230cb330503..32bf6c070ae7 100644
--- a/drivers/soc/tegra/fuse/fuse.h
+++ b/drivers/soc/tegra/fuse/fuse.h
@@ -13,6 +13,7 @@
 #include <linux/dmaengine.h>
 #include <linux/types.h>
 
+struct nvmem_device;
 struct tegra_fuse;
 
 struct tegra_fuse_info {
@@ -48,6 +49,8 @@ struct tegra_fuse {
 		dma_addr_t phys;
 		u32 *virt;
 	} apbdma;
+
+	struct nvmem_device *nvmem;
 };
 
 void tegra_init_revision(void);
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/7] soc/tegra: fuse: Add cell information

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Create nvmem cells for all the fuses currently used by consumers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/soc/tegra/fuse/fuse-tegra.c | 90 +++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index 3ce2138b278b..c6c6a7746046 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -86,6 +86,94 @@ static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
 	return 0;
 }
 
+static const struct nvmem_cell_info tegra_fuse_cells[] = {
+	{
+		.name = "tsensor-cpu1",
+		.offset = 0x084,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "tsensor-cpu2",
+		.offset = 0x088,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "tsensor-cpu0",
+		.offset = 0x098,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "xusb-pad-calibration",
+		.offset = 0x0f0,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "tsensor-cpu3",
+		.offset = 0x12c,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "sata-calibration",
+		.offset = 0x124,
+		.bytes = 1,
+		.bit_offset = 0,
+		.nbits = 2,
+	}, {
+		.name = "tsensor-gpu",
+		.offset = 0x154,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "tsensor-mem0",
+		.offset = 0x158,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "tsensor-mem1",
+		.offset = 0x15c,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "tsensor-pllx",
+		.offset = 0x160,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "tsensor-common",
+		.offset = 0x180,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "tsensor-realignment",
+		.offset = 0x1fc,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "gpu-calibration",
+		.offset = 0x204,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "xusb-pad-calibration-ext",
+		.offset = 0x250,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	},
+};
+
 static int tegra_fuse_probe(struct platform_device *pdev)
 {
 	void __iomem *base = fuse->base;
@@ -127,6 +215,8 @@ static int tegra_fuse_probe(struct platform_device *pdev)
 	nvmem.name = "fuse";
 	nvmem.id = -1;
 	nvmem.owner = THIS_MODULE;
+	nvmem.cells = tegra_fuse_cells;
+	nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
 	nvmem.type = NVMEM_TYPE_OTP;
 	nvmem.read_only = true;
 	nvmem.root_only = true;
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 4/7] soc/tegra: fuse: Register cell lookups for compatibility

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Typically nvmem cells would be stored in device tree. However, for
compatibility with device trees that don't contain nvmem cell
definitions, register lookups for cells currently used by consumers.
This allows the consumers to use the same API to query cells from the
device tree or using the legacy mechanism.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/soc/tegra/fuse/fuse-tegra.c   |   9 ++
 drivers/soc/tegra/fuse/fuse-tegra30.c | 154 ++++++++++++++++++++++++++
 drivers/soc/tegra/fuse/fuse.h         |   5 +
 3 files changed, 168 insertions(+)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index c6c6a7746046..6a0e25103e1c 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -420,6 +420,15 @@ static int __init tegra_init_fuse(void)
 	pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
 		 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
 
+	if (fuse->soc->lookups) {
+		size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups;
+
+		fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL);
+		if (!fuse->lookups)
+			return -ENOMEM;
+
+		nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
+	}
 
 	return 0;
 }
diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
index be9424a87173..b8daaf5b7291 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra30.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
@@ -8,6 +8,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/of_device.h>
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
@@ -127,6 +128,70 @@ const struct tegra_fuse_soc tegra114_fuse_soc = {
 #endif
 
 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
+static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = {
+	{
+		.nvmem_name = "fuse",
+		.cell_name = "xusb-pad-calibration",
+		.dev_id = "7009f000.padctl",
+		.con_id = "calibration",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "sata-calibration",
+		.dev_id = "70020000.sata",
+		.con_id = "calibration",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-common",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "common",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-realignment",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "realignment",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-cpu0",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "cpu0",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-cpu1",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "cpu1",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-cpu2",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "cpu2",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-cpu3",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "cpu3",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-mem0",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "mem0",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-mem1",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "mem1",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-gpu",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "gpu",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-pllx",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "pllx",
+	},
+};
+
 static const struct tegra_fuse_info tegra124_fuse_info = {
 	.read = tegra30_fuse_read,
 	.size = 0x300,
@@ -137,10 +202,81 @@ const struct tegra_fuse_soc tegra124_fuse_soc = {
 	.init = tegra30_fuse_init,
 	.speedo_init = tegra124_init_speedo_data,
 	.info = &tegra124_fuse_info,
+	.lookups = tegra124_fuse_lookups,
+	.num_lookups = ARRAY_SIZE(tegra124_fuse_lookups),
 };
 #endif
 
 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
+static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = {
+	{
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-cpu1",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "cpu1",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-cpu2",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "cpu2",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-cpu0",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "cpu0",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "xusb-pad-calibration",
+		.dev_id = "7009f000.padctl",
+		.con_id = "calibration",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-cpu3",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "cpu3",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "sata-calibration",
+		.dev_id = "70020000.sata",
+		.con_id = "calibration",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-gpu",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "gpu",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-mem0",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "mem0",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-mem1",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "mem1",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-pllx",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "pllx",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "tsensor-common",
+		.dev_id = "700e2000.thermal-sensor",
+		.con_id = "common",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "gpu-calibration",
+		.dev_id = "57000000.gpu",
+		.con_id = "calibration",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "xusb-pad-calibration-ext",
+		.dev_id = "7009f000.padctl",
+		.con_id = "calibration-ext",
+	},
+};
+
 static const struct tegra_fuse_info tegra210_fuse_info = {
 	.read = tegra30_fuse_read,
 	.size = 0x300,
@@ -151,10 +287,26 @@ const struct tegra_fuse_soc tegra210_fuse_soc = {
 	.init = tegra30_fuse_init,
 	.speedo_init = tegra210_init_speedo_data,
 	.info = &tegra210_fuse_info,
+	.lookups = tegra210_fuse_lookups,
+	.num_lookups = ARRAY_SIZE(tegra210_fuse_lookups),
 };
 #endif
 
 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
+static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = {
+	{
+		.nvmem_name = "fuse",
+		.cell_name = "xusb-pad-calibration",
+		.dev_id = "3520000.padctl",
+		.con_id = "calibration",
+	}, {
+		.nvmem_name = "fuse",
+		.cell_name = "xusb-pad-calibration-ext",
+		.dev_id = "3520000.padctl",
+		.con_id = "calibration-ext",
+	},
+};
+
 static const struct tegra_fuse_info tegra186_fuse_info = {
 	.read = tegra30_fuse_read,
 	.size = 0x300,
@@ -164,5 +316,7 @@ static const struct tegra_fuse_info tegra186_fuse_info = {
 const struct tegra_fuse_soc tegra186_fuse_soc = {
 	.init = tegra30_fuse_init,
 	.info = &tegra186_fuse_info,
+	.lookups = tegra186_fuse_lookups,
+	.num_lookups = ARRAY_SIZE(tegra186_fuse_lookups),
 };
 #endif
diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h
index 32bf6c070ae7..0f74c2c34af0 100644
--- a/drivers/soc/tegra/fuse/fuse.h
+++ b/drivers/soc/tegra/fuse/fuse.h
@@ -13,6 +13,7 @@
 #include <linux/dmaengine.h>
 #include <linux/types.h>
 
+struct nvmem_cell_lookup;
 struct nvmem_device;
 struct tegra_fuse;
 
@@ -28,6 +29,9 @@ struct tegra_fuse_soc {
 	int (*probe)(struct tegra_fuse *fuse);
 
 	const struct tegra_fuse_info *info;
+
+	const struct nvmem_cell_lookup *lookups;
+	unsigned int num_lookups;
 };
 
 struct tegra_fuse {
@@ -51,6 +55,7 @@ struct tegra_fuse {
 	} apbdma;
 
 	struct nvmem_device *nvmem;
+	struct nvmem_cell_lookup *lookups;
 };
 
 void tegra_init_revision(void);
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 5/7] drm/nouveau: tegra: Use nvmem API

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Instead of using the custom Tegra FUSE API to read the calibration fuse
for the clock on GM20B, use the nvmem API. This makes the dependency
between the two devices more explicit and decouples the driver from one
another.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
index b284e949f732..096a8b4b9bb5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
@@ -20,6 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include <linux/nvmem-consumer.h>
+
 #include <subdev/clk.h>
 #include <subdev/volt.h>
 #include <subdev/timer.h>
@@ -929,7 +931,6 @@ gm20b_clk_new_speedo0(struct nvkm_device *device, int index,
 }
 
 /* FUSE register */
-#define FUSE_RESERVED_CALIB0	0x204
 #define FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_SHIFT	0
 #define FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_WIDTH	4
 #define FUSE_RESERVED_CALIB0_INTERCEPT_INT_SHIFT	4
@@ -945,14 +946,17 @@ static int
 gm20b_clk_init_fused_params(struct gm20b_clk *clk)
 {
 	struct nvkm_subdev *subdev = &clk->base.base.subdev;
+	struct nvkm_device *device = subdev->device;
 	u32 val = 0;
 	u32 rev = 0;
+	int ret;
+
+	ret = nvmem_cell_read_u32(device->dev, "calibration", &val);
+	if (ret < 0)
+		return ret;
 
-#if IS_ENABLED(CONFIG_ARCH_TEGRA)
-	tegra_fuse_readl(FUSE_RESERVED_CALIB0, &val);
 	rev = (val >> FUSE_RESERVED_CALIB0_FUSE_REV_SHIFT) &
 	      MASK(FUSE_RESERVED_CALIB0_FUSE_REV_WIDTH);
-#endif
 
 	/* No fused parameters, we will calibrate later */
 	if (rev == 0)
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 6/7] phy: tegra: xusb: Use nvmem API

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Instead of using the custom Tegra FUSE API to read the calibration fuses
for the UPHY, use the nvmem API. This makes the dependency between the
two devices more explicit and decouples the drivers from one another.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/phy/tegra/xusb-tegra124.c | 10 +++++-----
 drivers/phy/tegra/xusb-tegra186.c |  7 +++----
 drivers/phy/tegra/xusb-tegra210.c | 10 ++++++----
 3 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/phy/tegra/xusb-tegra124.c b/drivers/phy/tegra/xusb-tegra124.c
index 98d84920c676..f62905ea4ca5 100644
--- a/drivers/phy/tegra/xusb-tegra124.c
+++ b/drivers/phy/tegra/xusb-tegra124.c
@@ -7,6 +7,7 @@
 #include <linux/io.h>
 #include <linux/mailbox_client.h>
 #include <linux/module.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/of.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
@@ -14,8 +15,6 @@
 #include <linux/reset.h>
 #include <linux/slab.h>
 
-#include <soc/tegra/fuse.h>
-
 #include "xusb.h"
 
 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
@@ -1653,13 +1652,14 @@ static const struct tegra_xusb_port_ops tegra124_usb3_port_ops = {
 };
 
 static int
-tegra124_xusb_read_fuse_calibration(struct tegra124_xusb_fuse_calibration *fuse)
+tegra124_xusb_read_fuse_calibration(struct tegra124_xusb_padctl *padctl)
 {
+	struct tegra124_xusb_fuse_calibration *fuse = &padctl->fuse;
 	unsigned int i;
 	int err;
 	u32 value;
 
-	err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
+	err = nvmem_cell_read_u32(padctl->base.dev, "calibration", &value);
 	if (err < 0)
 		return err;
 
@@ -1695,7 +1695,7 @@ tegra124_xusb_padctl_probe(struct device *dev,
 	padctl->base.dev = dev;
 	padctl->base.soc = soc;
 
-	err = tegra124_xusb_read_fuse_calibration(&padctl->fuse);
+	err = tegra124_xusb_read_fuse_calibration(padctl);
 	if (err < 0)
 		return ERR_PTR(err);
 
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 6f3afaf9398f..0663ed00d748 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -6,6 +6,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/of.h>
 #include <linux/phy/phy.h>
 #include <linux/regulator/consumer.h>
@@ -13,8 +14,6 @@
 #include <linux/clk.h>
 #include <linux/slab.h>
 
-#include <soc/tegra/fuse.h>
-
 #include "xusb.h"
 
 /* FUSE USB_CALIB registers */
@@ -800,7 +799,7 @@ tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
 	if (!level)
 		return -ENOMEM;
 
-	err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
+	err = nvmem_cell_read_u32(dev, "calibration", &value);
 	if (err) {
 		dev_err(dev, "failed to read calibration fuse: %d\n", err);
 		return err;
@@ -819,7 +818,7 @@ tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
 	padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
 						HS_TERM_RANGE_ADJ_MASK;
 
-	err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
+	err = nvmem_cell_read_u32(dev, "calibration-ext", &value);
 	if (err) {
 		dev_err(dev, "failed to read calibration fuse: %d\n", err);
 		return err;
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index 0c0df6897a3b..659b62867012 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -10,6 +10,7 @@
 #include <linux/io.h>
 #include <linux/mailbox_client.h>
 #include <linux/module.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/of.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
@@ -1946,13 +1947,14 @@ static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = {
 };
 
 static int
-tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse)
+tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_padctl *padctl)
 {
+	struct tegra210_xusb_fuse_calibration *fuse = &padctl->fuse;
 	unsigned int i;
 	u32 value;
 	int err;
 
-	err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
+	err = nvmem_cell_read_u32(padctl->base.dev, "calibration", &value);
 	if (err < 0)
 		return err;
 
@@ -1966,7 +1968,7 @@ tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse)
 		(value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) &
 		FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK;
 
-	err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
+	err = nvmem_cell_read_u32(padctl->base.dev, "calibration-ext", &value);
 	if (err < 0)
 		return err;
 
@@ -1991,7 +1993,7 @@ tegra210_xusb_padctl_probe(struct device *dev,
 	padctl->base.dev = dev;
 	padctl->base.soc = soc;
 
-	err = tegra210_xusb_read_fuse_calibration(&padctl->fuse);
+	err = tegra210_xusb_read_fuse_calibration(padctl);
 	if (err < 0)
 		return ERR_PTR(err);
 
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 7/7] thermal: tegra: Use nvmem API

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Instead of using the custom Tegra FUSE API to read the fuses for TSENSOR
configuration, use the nvmem API. This makes the dependency between the
two devices more explicit and decouples the driver from one another.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/thermal/tegra/soctherm-fuse.c     | 19 ++++++++++---------
 drivers/thermal/tegra/soctherm.c          |  4 ++--
 drivers/thermal/tegra/soctherm.h          |  9 ++++++---
 drivers/thermal/tegra/tegra124-soctherm.c |  8 --------
 drivers/thermal/tegra/tegra132-soctherm.c |  8 --------
 drivers/thermal/tegra/tegra210-soctherm.c |  8 --------
 6 files changed, 18 insertions(+), 38 deletions(-)

diff --git a/drivers/thermal/tegra/soctherm-fuse.c b/drivers/thermal/tegra/soctherm-fuse.c
index 190f95280e0b..c63bef809004 100644
--- a/drivers/thermal/tegra/soctherm-fuse.c
+++ b/drivers/thermal/tegra/soctherm-fuse.c
@@ -4,6 +4,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/platform_device.h>
 #include <soc/tegra/fuse.h>
 
@@ -70,14 +71,15 @@ static s64 div64_s64_precise(s64 a, s32 b)
 	return r >> 16;
 }
 
-int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
+int tegra_calc_shared_calib(struct device *dev,
+			    const struct tegra_soctherm_fuse *tfuse,
 			    struct tsensor_shared_calib *shared)
 {
 	u32 val;
 	s32 shifted_cp, shifted_ft;
 	int err;
 
-	err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val);
+	err = nvmem_cell_read_u32(dev, "common", &val);
 	if (err)
 		return err;
 
@@ -90,11 +92,9 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
 		     tfuse->fuse_shift_ft_shift;
 	shifted_ft = sign_extend32(shifted_ft, 4);
 
-	if (tfuse->fuse_spare_realignment) {
-		err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val);
-		if (err)
-			return err;
-	}
+	err = nvmem_cell_read_u32(dev, "realignment", &val);
+	if (err != -ENOENT)
+		return err;
 
 	shifted_cp = sign_extend32(val, 5);
 
@@ -104,7 +104,8 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
 	return 0;
 }
 
-int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
+int tegra_calc_tsensor_calib(struct device *dev,
+			     const struct tegra_tsensor *sensor,
 			     const struct tsensor_shared_calib *shared,
 			     u32 *calibration)
 {
@@ -119,7 +120,7 @@ int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
 
 	sensor_group = sensor->group;
 
-	err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
+	err = nvmem_cell_read_u32(dev, sensor->name, &val);
 	if (err)
 		return err;
 
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index 43941eb734eb..e632888ff1ae 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -2180,13 +2180,13 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	/* calculate shared calibration data */
-	err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
+	err = tegra_calc_shared_calib(&pdev->dev, soc->tfuse, &shared_calib);
 	if (err)
 		return err;
 
 	/* calculate tsensor calibaration data */
 	for (i = 0; i < soc->num_tsensors; ++i) {
-		err = tegra_calc_tsensor_calib(&soc->tsensors[i],
+		err = tegra_calc_tsensor_calib(&pdev->dev, &soc->tsensors[i],
 					       &shared_calib,
 					       &tegra->calib[i]);
 		if (err)
diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h
index 70501e73d586..715b4f06e162 100644
--- a/drivers/thermal/tegra/soctherm.h
+++ b/drivers/thermal/tegra/soctherm.h
@@ -93,7 +93,6 @@ struct tegra_tsensor {
 	const char *name;
 	const u32 base;
 	const struct tegra_tsensor_configuration *config;
-	const u32 calib_fuse_offset;
 	/*
 	 * Correction values used to modify values read from
 	 * calibration fuses
@@ -131,9 +130,13 @@ struct tegra_soctherm_soc {
 	struct tsensor_group_thermtrips *thermtrips;
 };
 
-int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
+struct tegra_soctherm;
+
+int tegra_calc_shared_calib(struct device *dev,
+			    const struct tegra_soctherm_fuse *tfuse,
 			    struct tsensor_shared_calib *shared);
-int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
+int tegra_calc_tsensor_calib(struct device *dev,
+			     const struct tegra_tsensor *sensor,
 			     const struct tsensor_shared_calib *shared,
 			     u32 *calib);
 
diff --git a/drivers/thermal/tegra/tegra124-soctherm.c b/drivers/thermal/tegra/tegra124-soctherm.c
index 20ad27f4d1a1..e5bd080e3632 100644
--- a/drivers/thermal/tegra/tegra124-soctherm.c
+++ b/drivers/thermal/tegra/tegra124-soctherm.c
@@ -129,7 +129,6 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
 		.name = "cpu0",
 		.base = 0xc0,
 		.config = &tegra124_tsensor_config,
-		.calib_fuse_offset = 0x098,
 		.fuse_corr_alpha = 1135400,
 		.fuse_corr_beta = -6266900,
 		.group = &tegra124_tsensor_group_cpu,
@@ -137,7 +136,6 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
 		.name = "cpu1",
 		.base = 0xe0,
 		.config = &tegra124_tsensor_config,
-		.calib_fuse_offset = 0x084,
 		.fuse_corr_alpha = 1122220,
 		.fuse_corr_beta = -5700700,
 		.group = &tegra124_tsensor_group_cpu,
@@ -145,7 +143,6 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
 		.name = "cpu2",
 		.base = 0x100,
 		.config = &tegra124_tsensor_config,
-		.calib_fuse_offset = 0x088,
 		.fuse_corr_alpha = 1127000,
 		.fuse_corr_beta = -6768200,
 		.group = &tegra124_tsensor_group_cpu,
@@ -153,7 +150,6 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
 		.name = "cpu3",
 		.base = 0x120,
 		.config = &tegra124_tsensor_config,
-		.calib_fuse_offset = 0x12c,
 		.fuse_corr_alpha = 1110900,
 		.fuse_corr_beta = -6232000,
 		.group = &tegra124_tsensor_group_cpu,
@@ -161,7 +157,6 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
 		.name = "mem0",
 		.base = 0x140,
 		.config = &tegra124_tsensor_config,
-		.calib_fuse_offset = 0x158,
 		.fuse_corr_alpha = 1122300,
 		.fuse_corr_beta = -5936400,
 		.group = &tegra124_tsensor_group_mem,
@@ -169,7 +164,6 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
 		.name = "mem1",
 		.base = 0x160,
 		.config = &tegra124_tsensor_config,
-		.calib_fuse_offset = 0x15c,
 		.fuse_corr_alpha = 1145700,
 		.fuse_corr_beta = -7124600,
 		.group = &tegra124_tsensor_group_mem,
@@ -177,7 +171,6 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
 		.name = "gpu",
 		.base = 0x180,
 		.config = &tegra124_tsensor_config,
-		.calib_fuse_offset = 0x154,
 		.fuse_corr_alpha = 1120100,
 		.fuse_corr_beta = -6000500,
 		.group = &tegra124_tsensor_group_gpu,
@@ -185,7 +178,6 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
 		.name = "pllx",
 		.base = 0x1a0,
 		.config = &tegra124_tsensor_config,
-		.calib_fuse_offset = 0x160,
 		.fuse_corr_alpha = 1106500,
 		.fuse_corr_beta = -6729300,
 		.group = &tegra124_tsensor_group_pll,
diff --git a/drivers/thermal/tegra/tegra132-soctherm.c b/drivers/thermal/tegra/tegra132-soctherm.c
index b76308fdad9e..2f211ae4d6e8 100644
--- a/drivers/thermal/tegra/tegra132-soctherm.c
+++ b/drivers/thermal/tegra/tegra132-soctherm.c
@@ -129,7 +129,6 @@ static struct tegra_tsensor tegra132_tsensors[] = {
 		.name = "cpu0",
 		.base = 0xc0,
 		.config = &tegra132_tsensor_config,
-		.calib_fuse_offset = 0x098,
 		.fuse_corr_alpha = 1126600,
 		.fuse_corr_beta = -9433500,
 		.group = &tegra132_tsensor_group_cpu,
@@ -137,7 +136,6 @@ static struct tegra_tsensor tegra132_tsensors[] = {
 		.name = "cpu1",
 		.base = 0xe0,
 		.config = &tegra132_tsensor_config,
-		.calib_fuse_offset = 0x084,
 		.fuse_corr_alpha = 1110800,
 		.fuse_corr_beta = -7383000,
 		.group = &tegra132_tsensor_group_cpu,
@@ -145,7 +143,6 @@ static struct tegra_tsensor tegra132_tsensors[] = {
 		.name = "cpu2",
 		.base = 0x100,
 		.config = &tegra132_tsensor_config,
-		.calib_fuse_offset = 0x088,
 		.fuse_corr_alpha = 1113800,
 		.fuse_corr_beta = -6215200,
 		.group = &tegra132_tsensor_group_cpu,
@@ -153,7 +150,6 @@ static struct tegra_tsensor tegra132_tsensors[] = {
 		.name = "cpu3",
 		.base = 0x120,
 		.config = &tegra132_tsensor_config,
-		.calib_fuse_offset = 0x12c,
 		.fuse_corr_alpha = 1129600,
 		.fuse_corr_beta = -8196100,
 		.group = &tegra132_tsensor_group_cpu,
@@ -161,7 +157,6 @@ static struct tegra_tsensor tegra132_tsensors[] = {
 		.name = "mem0",
 		.base = 0x140,
 		.config = &tegra132_tsensor_config,
-		.calib_fuse_offset = 0x158,
 		.fuse_corr_alpha = 1132900,
 		.fuse_corr_beta = -6755300,
 		.group = &tegra132_tsensor_group_mem,
@@ -169,7 +164,6 @@ static struct tegra_tsensor tegra132_tsensors[] = {
 		.name = "mem1",
 		.base = 0x160,
 		.config = &tegra132_tsensor_config,
-		.calib_fuse_offset = 0x15c,
 		.fuse_corr_alpha = 1142300,
 		.fuse_corr_beta = -7374200,
 		.group = &tegra132_tsensor_group_mem,
@@ -177,7 +171,6 @@ static struct tegra_tsensor tegra132_tsensors[] = {
 		.name = "gpu",
 		.base = 0x180,
 		.config = &tegra132_tsensor_config,
-		.calib_fuse_offset = 0x154,
 		.fuse_corr_alpha = 1125100,
 		.fuse_corr_beta = -6350400,
 		.group = &tegra132_tsensor_group_gpu,
@@ -185,7 +178,6 @@ static struct tegra_tsensor tegra132_tsensors[] = {
 		.name = "pllx",
 		.base = 0x1a0,
 		.config = &tegra132_tsensor_config,
-		.calib_fuse_offset = 0x160,
 		.fuse_corr_alpha = 1118100,
 		.fuse_corr_beta = -8208800,
 		.group = &tegra132_tsensor_group_pll,
diff --git a/drivers/thermal/tegra/tegra210-soctherm.c b/drivers/thermal/tegra/tegra210-soctherm.c
index d0ff793f18c5..b2f3c775c1bb 100644
--- a/drivers/thermal/tegra/tegra210-soctherm.c
+++ b/drivers/thermal/tegra/tegra210-soctherm.c
@@ -130,7 +130,6 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
 		.name = "cpu0",
 		.base = 0xc0,
 		.config = &tegra210_tsensor_config,
-		.calib_fuse_offset = 0x098,
 		.fuse_corr_alpha = 1085000,
 		.fuse_corr_beta = 3244200,
 		.group = &tegra210_tsensor_group_cpu,
@@ -138,7 +137,6 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
 		.name = "cpu1",
 		.base = 0xe0,
 		.config = &tegra210_tsensor_config,
-		.calib_fuse_offset = 0x084,
 		.fuse_corr_alpha = 1126200,
 		.fuse_corr_beta = -67500,
 		.group = &tegra210_tsensor_group_cpu,
@@ -146,7 +144,6 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
 		.name = "cpu2",
 		.base = 0x100,
 		.config = &tegra210_tsensor_config,
-		.calib_fuse_offset = 0x088,
 		.fuse_corr_alpha = 1098400,
 		.fuse_corr_beta = 2251100,
 		.group = &tegra210_tsensor_group_cpu,
@@ -154,7 +151,6 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
 		.name = "cpu3",
 		.base = 0x120,
 		.config = &tegra210_tsensor_config,
-		.calib_fuse_offset = 0x12c,
 		.fuse_corr_alpha = 1108000,
 		.fuse_corr_beta = 602700,
 		.group = &tegra210_tsensor_group_cpu,
@@ -162,7 +158,6 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
 		.name = "mem0",
 		.base = 0x140,
 		.config = &tegra210_tsensor_config,
-		.calib_fuse_offset = 0x158,
 		.fuse_corr_alpha = 1069200,
 		.fuse_corr_beta = 3549900,
 		.group = &tegra210_tsensor_group_mem,
@@ -170,7 +165,6 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
 		.name = "mem1",
 		.base = 0x160,
 		.config = &tegra210_tsensor_config,
-		.calib_fuse_offset = 0x15c,
 		.fuse_corr_alpha = 1173700,
 		.fuse_corr_beta = -6263600,
 		.group = &tegra210_tsensor_group_mem,
@@ -178,7 +172,6 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
 		.name = "gpu",
 		.base = 0x180,
 		.config = &tegra210_tsensor_config,
-		.calib_fuse_offset = 0x154,
 		.fuse_corr_alpha = 1074300,
 		.fuse_corr_beta = 2734900,
 		.group = &tegra210_tsensor_group_gpu,
@@ -186,7 +179,6 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
 		.name = "pllx",
 		.base = 0x1a0,
 		.config = &tegra210_tsensor_config,
-		.calib_fuse_offset = 0x160,
 		.fuse_corr_alpha = 1039700,
 		.fuse_corr_beta = 6829100,
 		.group = &tegra210_tsensor_group_pll,
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel