* [PATCH] ARM: dts: dir685: Drop spi-cpol from the display
@ 2019-09-15 13:54 Linus Walleij
2019-09-16 14:31 ` Arnd Bergmann
0 siblings, 1 reply; 2+ messages in thread
From: Linus Walleij @ 2019-09-15 13:54 UTC (permalink / raw)
To: arm, soc; +Cc: Linus Walleij, Mark Brown, linux-arm-kernel
The D-Link DIR-685 had its clock polarity set as active
low using the special SPI "spi-cpol" property.
This is not correct: the datasheet clearly states:
"Fix SCL to GND level when not in use" which is
indicative that this line is active high.
After a recent fix making the GPIO-based SPI driver
force the clock line de-asserted at the beginning of
each SPI transaction this reared its ugly head: now
de-asserted was taken to mean the line should be
driven high, but it should be driven low.
Fix this up in the DTS file and the display works again.
Cc: Mark Brown <broonie@kernel.org>
Fixes: 2922d1cc1696 ("spi: gpio: Add SPI_MASTER_GPIO_SS flag")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ARM SoC folks: please apply this directly to fixes if
you're OK with the patch.
---
arch/arm/boot/dts/gemini-dlink-dir-685.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
index bfaa2de63a10..e2030ba16512 100644
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -72,7 +72,6 @@
reg = <0>;
/* 50 ns min period = 20 MHz */
spi-max-frequency = <20000000>;
- spi-cpol; /* Clock active low */
vcc-supply = <&vdisp>;
iovcc-supply = <&vdisp>;
vci-supply = <&vdisp>;
--
2.21.0
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] ARM: dts: dir685: Drop spi-cpol from the display
2019-09-15 13:54 [PATCH] ARM: dts: dir685: Drop spi-cpol from the display Linus Walleij
@ 2019-09-16 14:31 ` Arnd Bergmann
0 siblings, 0 replies; 2+ messages in thread
From: Arnd Bergmann @ 2019-09-16 14:31 UTC (permalink / raw)
To: Linus Walleij; +Cc: SoC Team, arm-soc, Mark Brown, Linux ARM
On Sun, Sep 15, 2019 at 3:55 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> The D-Link DIR-685 had its clock polarity set as active
> low using the special SPI "spi-cpol" property.
>
> This is not correct: the datasheet clearly states:
> "Fix SCL to GND level when not in use" which is
> indicative that this line is active high.
>
> After a recent fix making the GPIO-based SPI driver
> force the clock line de-asserted at the beginning of
> each SPI transaction this reared its ugly head: now
> de-asserted was taken to mean the line should be
> driven high, but it should be driven low.
>
> Fix this up in the DTS file and the display works again.
>
> Cc: Mark Brown <broonie@kernel.org>
> Fixes: 2922d1cc1696 ("spi: gpio: Add SPI_MASTER_GPIO_SS flag")
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ARM SoC folks: please apply this directly to fixes if
> you're OK with the patch.
As the merge window is now open, I just applied this to
the 'arm/late' branch.
Arnd
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