[PATCH 0/4] arm64/cpufeature: Fix + doc update

[PATCH 0/4] arm64/cpufeature: Fix + doc update

[Julien Grall]

Hi all,

This patch fix an issue related to exposing the FRINT capability to
userspace (see patch #1). The rest is documentation update.

Cheers,

Julien Grall (4):
  arm64: cpufeature: Effectively expose FRINT capability to userspace
  docs/arm64: elf_hwcaps: sort the HWCAP{,2} documentation by ascending
    value
  docs/arm64: elf_hwcaps: Document HWCAP_SB
  docs/arm64: cpu-feature-registers: Documents missing visible fields

 Documentation/arm64/cpu-feature-registers.rst |  4 ++
 Documentation/arm64/elf_hwcaps.rst            | 67 ++++++++++++++-------------
 arch/arm64/kernel/cpufeature.c                |  1 +
 3 files changed, 40 insertions(+), 32 deletions(-)

-- 
2.11.0


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[PATCH 1/4] arm64: cpufeature: Effectively expose FRINT capability to userspace

[Julien Grall]

The HWCAP framework will detect a new capability based on the sanitized
version of the ID registers.

Sanitization is based on a whitelist, so any field not described will end
up to be zeroed.

At the moment, ID_AA64ISAR1_EL1.FRINTTS is not described in
ftr_id_aa64isar1. This means the field will be zeroed and therefore the
userspace will not be able to see the HWCAP even if the hardware
supports the feature.

This can be fixed by describing the field in ftr_id_aa64isar1.

Fixes: ca9503fc9e98 ("arm64: Expose FRINT capabilities to userspace")
Signed-off-by: Julien Grall <julien.grall@arm.com>
Cc: mark.brown@arm.com
---
 arch/arm64/kernel/cpufeature.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9323bcc40a58..cabebf1a7976 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -136,6 +136,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 
 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
-- 
2.11.0


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Re: [PATCH 1/4] arm64: cpufeature: Effectively expose FRINT capability to userspace

[Will Deacon]

On Thu, Oct 03, 2019 at 12:12:08PM +0100, Julien Grall wrote:
> The HWCAP framework will detect a new capability based on the sanitized
> version of the ID registers.
> 
> Sanitization is based on a whitelist, so any field not described will end
> up to be zeroed.
> 
> At the moment, ID_AA64ISAR1_EL1.FRINTTS is not described in
> ftr_id_aa64isar1. This means the field will be zeroed and therefore the
> userspace will not be able to see the HWCAP even if the hardware
> supports the feature.
> 
> This can be fixed by describing the field in ftr_id_aa64isar1.
> 
> Fixes: ca9503fc9e98 ("arm64: Expose FRINT capabilities to userspace")
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> Cc: mark.brown@arm.com
> ---
>  arch/arm64/kernel/cpufeature.c | 1 +
>  1 file changed, 1 insertion(+)

D'oh, we should've caught this in testing. Queued as a fix.

Will

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[PATCH 2/4] docs/arm64: elf_hwcaps: sort the HWCAP{, 2} documentation by ascending value

[Julien Grall]

Part of the hardware capabilities documented in elf_hwcap.rst are
ordered following the definition in the header
arch/arm64/include/uapi/asm/hwcap.h but others seems to be documented
in random order.

To make easier to match against the definition in the header, they are
now sorted in the same order as they are defined in header. I.e.,
HWCAP first by ascending value, and then HWCAP2 in the similar fashion.

Signed-off-by: Julien Grall <julien.grall@arm.com>
---
 Documentation/arm64/elf_hwcaps.rst | 64 +++++++++++++++++++-------------------
 1 file changed, 32 insertions(+), 32 deletions(-)

diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
index 91f79529c58c..9ee7f8ff1fae 100644
--- a/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@ -119,10 +119,6 @@ HWCAP_LRCPC
 HWCAP_DCPOP
     Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.
 
-HWCAP2_DCPODP
-
-    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
-
 HWCAP_SHA3
     Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
 
@@ -141,30 +137,6 @@ HWCAP_SHA512
 HWCAP_SVE
     Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.
 
-HWCAP2_SVE2
-
-    Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.
-
-HWCAP2_SVEAES
-
-    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
-
-HWCAP2_SVEPMULL
-
-    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
-
-HWCAP2_SVEBITPERM
-
-    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
-
-HWCAP2_SVESHA3
-
-    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
-
-HWCAP2_SVESM4
-
-    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
-
 HWCAP_ASIMDFHM
    Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
 
@@ -180,10 +152,6 @@ HWCAP_ILRCPC
 HWCAP_FLAGM
     Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
 
-HWCAP2_FLAGM2
-
-    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
-
 HWCAP_SSBS
     Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
 
@@ -197,6 +165,38 @@ HWCAP_PACG
     ID_AA64ISAR1_EL1.GPI == 0b0001, as described by
     Documentation/arm64/pointer-authentication.rst.
 
+HWCAP2_DCPODP
+
+    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
+
+HWCAP2_SVE2
+
+    Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.
+
+HWCAP2_SVEAES
+
+    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
+
+HWCAP2_SVEPMULL
+
+    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
+
+HWCAP2_SVEBITPERM
+
+    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
+
+HWCAP2_SVESHA3
+
+    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
+
+HWCAP2_SVESM4
+
+    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
+
+HWCAP2_FLAGM2
+
+    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
+
 HWCAP2_FRINT
 
     Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
-- 
2.11.0


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[PATCH 3/4] docs/arm64: elf_hwcaps: Document HWCAP_SB

[Julien Grall]

All the hardware capabilities but HWCAP_SB is not documented in
elf_hwcaps.rst. So document it.

Signed-off-by: Julien Grall <julien.grall@arm.com>
---
 Documentation/arm64/elf_hwcaps.rst | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
index 9ee7f8ff1fae..7fa3d215ae6a 100644
--- a/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@ -155,6 +155,9 @@ HWCAP_FLAGM
 HWCAP_SSBS
     Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
 
+HWCAP_SB
+    Functionality implied by ID_AA64ISAR1_EL1.SB == 0b0001.
+
 HWCAP_PACA
     Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or
     ID_AA64ISAR1_EL1.API == 0b0001, as described by
-- 
2.11.0


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[PATCH 4/4] docs/arm64: cpu-feature-registers: Documents missing visible fields

[Julien Grall]

A couple of fields visible to userspace are not described in the
documentation. So update it.

Signed-off-by: Julien Grall <julien.grall@arm.com>
---
 Documentation/arm64/cpu-feature-registers.rst | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
index 2955287e9acc..ffcf4e2c71ef 100644
--- a/Documentation/arm64/cpu-feature-registers.rst
+++ b/Documentation/arm64/cpu-feature-registers.rst
@@ -193,6 +193,10 @@ infrastructure:
      +------------------------------+---------+---------+
      | Name                         |  bits   | visible |
      +------------------------------+---------+---------+
+     | SB                           | [36-39] |    y    |
+     +------------------------------+---------+---------+
+     | FRINTTS                      | [32-35] |    y    |
+     +------------------------------+---------+---------+
      | GPI                          | [31-28] |    y    |
      +------------------------------+---------+---------+
      | GPA                          | [27-24] |    y    |
-- 
2.11.0


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Re: [PATCH 4/4] docs/arm64: cpu-feature-registers: Documents missing visible fields

[Julien Grall]

Hi,

On 03/10/2019 12:12, Julien Grall wrote:
> A couple of fields visible to userspace are not described in the
> documentation. So update it.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
>   Documentation/arm64/cpu-feature-registers.rst | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
> index 2955287e9acc..ffcf4e2c71ef 100644
> --- a/Documentation/arm64/cpu-feature-registers.rst
> +++ b/Documentation/arm64/cpu-feature-registers.rst
> @@ -193,6 +193,10 @@ infrastructure:
>        +------------------------------+---------+---------+
>        | Name                         |  bits   | visible |
>        +------------------------------+---------+---------+
> +     | SB                           | [36-39] |    y    |
> +     +------------------------------+---------+---------+
> +     | FRINTTS                      | [32-35] |    y    |
> +     +------------------------------+---------+---------+

Will reported the bitfields were inconsistent (see [1]). Looking in more 
details, it seems that I messed up this patch when sending it (I honestly can't 
remember why I wrote like that :().

@Catalin, I saw you applied this patch to for-next/elf-hwcap-docs. Would you
mind to update the content of the patch? Or do you prefer a new version?

>        | GPI                          | [31-28] |    y    |
>        +------------------------------+---------+---------+
>        | GPA                          | [27-24] |    y    |
> 

Cheers,

[1] <20191029111517.GE11590@willie-the-truck>

-- 
Julien Grall

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Re: [PATCH 4/4] docs/arm64: cpu-feature-registers: Documents missing visible fields

[Catalin Marinas]

On Thu, Oct 31, 2019 at 04:48:18PM +0000, Julien Grall wrote:
> On 03/10/2019 12:12, Julien Grall wrote:
> > A couple of fields visible to userspace are not described in the
> > documentation. So update it.
> > 
> > Signed-off-by: Julien Grall <julien.grall@arm.com>
> > ---
> >   Documentation/arm64/cpu-feature-registers.rst | 4 ++++
> >   1 file changed, 4 insertions(+)
> > 
> > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
> > index 2955287e9acc..ffcf4e2c71ef 100644
> > --- a/Documentation/arm64/cpu-feature-registers.rst
> > +++ b/Documentation/arm64/cpu-feature-registers.rst
> > @@ -193,6 +193,10 @@ infrastructure:
> >        +------------------------------+---------+---------+
> >        | Name                         |  bits   | visible |
> >        +------------------------------+---------+---------+
> > +     | SB                           | [36-39] |    y    |
> > +     +------------------------------+---------+---------+
> > +     | FRINTTS                      | [32-35] |    y    |
> > +     +------------------------------+---------+---------+
> 
> Will reported the bitfields were inconsistent (see [1]). Looking in more
> details, it seems that I messed up this patch when sending it (I honestly
> can't remember why I wrote like that :().
> 
> @Catalin, I saw you applied this patch to for-next/elf-hwcap-docs. Would you
> mind to update the content of the patch? Or do you prefer a new version?

Please send a fix on top of the elf-hwcap-docs branch. I'd prefer not to
rebase it.

-- 
Catalin

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Re: [PATCH 0/4] arm64/cpufeature: Fix + doc update

[Will Deacon]

On Thu, Oct 03, 2019 at 12:12:07PM +0100, Julien Grall wrote:
> This patch fix an issue related to exposing the FRINT capability to
> userspace (see patch #1). The rest is documentation update.
>
For patches 2-4:

Acked-by: Will Deacon <will@kernel.org>

Catalin can take them for 5.5, since I don't think they're urgent.

Will

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Re: [PATCH 0/4] arm64/cpufeature: Fix + doc update

[Catalin Marinas]

On Fri, Oct 04, 2019 at 11:37:22AM +0100, Will Deacon wrote:
> On Thu, Oct 03, 2019 at 12:12:07PM +0100, Julien Grall wrote:
> > This patch fix an issue related to exposing the FRINT capability to
> > userspace (see patch #1). The rest is documentation update.
> >
> For patches 2-4:
> 
> Acked-by: Will Deacon <will@kernel.org>
> 
> Catalin can take them for 5.5, since I don't think they're urgent.

Queued. Thanks.

-- 
Catalin

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