* [PATCH] arm64: dts: qcom: msm8998: Disable coresight by default
@ 2019-10-03 6:44 Sai Prakash Ranjan
2019-10-03 12:53 ` Marc Gonzalez
0 siblings, 1 reply; 4+ messages in thread
From: Sai Prakash Ranjan @ 2019-10-03 6:44 UTC (permalink / raw)
To: Rob Herring, devicetree, Mathieu Poirier, Suzuki K Poulose,
Bjorn Andersson, Andy Gross, Jeffrey Hugo, David Brown,
Mark Rutland
Cc: linux-arm-msm, Sai Prakash Ranjan, linux-kernel, linux-arm-kernel
Boot failure has been reported on MSM8998 based laptop when
coresight is enabled. This is most likely due to lack of
firmware support for coresight on production device when
compared to debug device like MTP where this issue is not
observed. So disable coresight by default for MSM8998 and
enable it only for MSM8998 MTP.
Reported-and-tested-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Fixes: 783abfa2249a ("arm64: dts: qcom: msm8998: Add Coresight support")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 68 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8998.dtsi | 51 +++++++++++------
2 files changed, 102 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
index 108667ce4f31..8d15572d18e6 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
@@ -27,6 +27,66 @@
status = "okay";
};
+&etf {
+ status = "okay";
+};
+
+&etm1 {
+ status = "okay";
+};
+
+&etm2 {
+ status = "okay";
+};
+
+&etm3 {
+ status = "okay";
+};
+
+&etm4 {
+ status = "okay";
+};
+
+&etm5 {
+ status = "okay";
+};
+
+&etm6 {
+ status = "okay";
+};
+
+&etm7 {
+ status = "okay";
+};
+
+&etm8 {
+ status = "okay";
+};
+
+&etr {
+ status = "okay";
+};
+
+&funnel1 {
+ status = "okay";
+};
+
+&funnel2 {
+ status = "okay";
+};
+
+&funnel3 {
+ status = "okay";
+};
+
+&funnel4 {
+ status = "okay";
+};
+
+&funnel5 {
+ status = "okay";
+};
+
&pm8005_lsid1 {
pm8005-regulators {
compatible = "qcom,pm8005-regulators";
@@ -51,6 +111,10 @@
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
};
+&replicator1 {
+ status = "okay";
+};
+
&rpm_requests {
pm8998-regulators {
compatible = "qcom,rpm-pm8998-regulators";
@@ -249,6 +313,10 @@
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
};
+&stm {
+ status = "okay";
+};
+
&ufshc {
vcc-supply = <&vreg_l20a_2p95>;
vccq-supply = <&vreg_l26a_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index c6f81431983e..ffb64fc239ee 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -998,11 +998,12 @@
#interrupt-cells = <0x2>;
};
- stm@6002000 {
+ stm: stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x06002000 0x1000>,
<0x16280000 0x180000>;
reg-names = "stm-base", "stm-data-base";
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1016,9 +1017,10 @@
};
};
- funnel@6041000 {
+ funnel1: funnel@6041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x06041000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1045,9 +1047,10 @@
};
};
- funnel@6042000 {
+ funnel2: funnel@6042000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x06042000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1075,9 +1078,10 @@
};
};
- funnel@6045000 {
+ funnel3: funnel@6045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x06045000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1113,9 +1117,10 @@
};
};
- replicator@6046000 {
+ replicator1: replicator@6046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x06046000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1137,9 +1142,10 @@
};
};
- etf@6047000 {
+ etf: etf@6047000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x06047000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1163,9 +1169,10 @@
};
};
- etr@6048000 {
+ etr: etr@6048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x06048000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1181,9 +1188,10 @@
};
};
- etm@7840000 {
+ etm1: etm@7840000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07840000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1200,9 +1208,10 @@
};
};
- etm@7940000 {
+ etm2: etm@7940000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07940000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1219,9 +1228,10 @@
};
};
- etm@7a40000 {
+ etm3: etm@7a40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07a40000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1238,9 +1248,10 @@
};
};
- etm@7b40000 {
+ etm4: etm@7b40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07b40000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1257,9 +1268,10 @@
};
};
- funnel@7b60000 { /* APSS Funnel */
+ funnel4: funnel@7b60000 { /* APSS Funnel */
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07b60000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1343,9 +1355,10 @@
};
};
- funnel@7b70000 {
+ funnel5: funnel@7b70000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x07b70000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1369,9 +1382,10 @@
};
};
- etm@7c40000 {
+ etm5: etm@7c40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07c40000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1385,9 +1399,10 @@
};
};
- etm@7d40000 {
+ etm6: etm@7d40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07d40000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1401,9 +1416,10 @@
};
};
- etm@7e40000 {
+ etm7: etm@7e40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07e40000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
@@ -1417,9 +1433,10 @@
};
};
- etm@7f40000 {
+ etm8: etm@7f40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07f40000 0x1000>;
+ status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: qcom: msm8998: Disable coresight by default
2019-10-03 6:44 [PATCH] arm64: dts: qcom: msm8998: Disable coresight by default Sai Prakash Ranjan
@ 2019-10-03 12:53 ` Marc Gonzalez
2019-10-03 15:21 ` Sai Prakash Ranjan
2019-10-03 16:23 ` Bjorn Andersson
0 siblings, 2 replies; 4+ messages in thread
From: Marc Gonzalez @ 2019-10-03 12:53 UTC (permalink / raw)
To: Sai Prakash Ranjan, Jeffrey Hugo
Cc: Mark Rutland, DT, Mathieu Poirier, Suzuki K Poulose, MSM,
Andy Gross, Bjorn Andersson, Rob Herring, Linux ARM
On 03/10/2019 08:44, Sai Prakash Ranjan wrote:
> Boot failure has been reported on MSM8998 based laptop when
> coresight is enabled. This is most likely due to lack of
> firmware support for coresight on production device when
> compared to debug device like MTP where this issue is not
> observed. So disable coresight by default for MSM8998 and
> enable it only for MSM8998 MTP.
>
> Reported-and-tested-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
> Fixes: 783abfa2249a ("arm64: dts: qcom: msm8998: Add Coresight support")
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 68 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 51 +++++++++++------
> 2 files changed, 102 insertions(+), 17 deletions(-)
Just wanted to toss an alternative, based on Suzuki's suggestion
(i.e. move the coresight nodes to a separate file)
arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi | 439 ++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 1 +
arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 -----------------------
3 files changed, 440 insertions(+), 435 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi
new file mode 100644
index 000000000000..eabf4e4194fd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */
+
+&soc {
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x06002000 0x1000>,
+ <0x16280000 0x180000>;
+ reg-names = "stm-base", "stm-data-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x06041000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x06042000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ funnel1_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in1>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+ funnel1_in6: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x06045000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ merge_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel1_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x06046000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@6047000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x06047000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x06048000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ etm@7840000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07840000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU0>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7940000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07940000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU1>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7a40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07a40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU2>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7b40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07b40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU3>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@7b60000 { /* APSS Funnel */
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07b60000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7b70000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x07b70000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel1_in6>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint =
+ <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etm@7c40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07c40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU4>;
+
+ port{
+ etm4_out: endpoint {
+ remote-endpoint = <&apss_funnel_in4>;
+ };
+ };
+ };
+
+ etm@7d40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07d40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU5>;
+
+ port{
+ etm5_out: endpoint {
+ remote-endpoint = <&apss_funnel_in5>;
+ };
+ };
+ };
+
+ etm@7e40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07e40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU6>;
+
+ port{
+ etm6_out: endpoint {
+ remote-endpoint = <&apss_funnel_in6>;
+ };
+ };
+ };
+
+ etm@7f40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07f40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU7>;
+
+ port{
+ etm7_out: endpoint {
+ remote-endpoint = <&apss_funnel_in7>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
index 108667ce4f31..9b586b3206fc 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
@@ -5,6 +5,7 @@
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
#include "pm8005.dtsi"
+#include "msm8998-coresight.dtsi"
/ {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index c6f81431983e..4b66a1c588f8 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -998,441 +998,6 @@
#interrupt-cells = <0x2>;
};
- stm@6002000 {
- compatible = "arm,coresight-stm", "arm,primecell";
- reg = <0x06002000 0x1000>,
- <0x16280000 0x180000>;
- reg-names = "stm-base", "stm-data-base";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- stm_out: endpoint {
- remote-endpoint = <&funnel0_in7>;
- };
- };
- };
- };
-
- funnel@6041000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x06041000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- funnel0_out: endpoint {
- remote-endpoint =
- <&merge_funnel_in0>;
- };
- };
- };
-
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@7 {
- reg = <7>;
- funnel0_in7: endpoint {
- remote-endpoint = <&stm_out>;
- };
- };
- };
- };
-
- funnel@6042000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x06042000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- funnel1_out: endpoint {
- remote-endpoint =
- <&merge_funnel_in1>;
- };
- };
- };
-
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@6 {
- reg = <6>;
- funnel1_in6: endpoint {
- remote-endpoint =
- <&apss_merge_funnel_out>;
- };
- };
- };
- };
-
- funnel@6045000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x06045000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- merge_funnel_out: endpoint {
- remote-endpoint =
- <&etf_in>;
- };
- };
- };
-
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- merge_funnel_in0: endpoint {
- remote-endpoint =
- <&funnel0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- merge_funnel_in1: endpoint {
- remote-endpoint =
- <&funnel1_out>;
- };
- };
- };
- };
-
- replicator@6046000 {
- compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
- reg = <0x06046000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- replicator_out: endpoint {
- remote-endpoint = <&etr_in>;
- };
- };
- };
-
- in-ports {
- port {
- replicator_in: endpoint {
- remote-endpoint = <&etf_out>;
- };
- };
- };
- };
-
- etf@6047000 {
- compatible = "arm,coresight-tmc", "arm,primecell";
- reg = <0x06047000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- etf_out: endpoint {
- remote-endpoint =
- <&replicator_in>;
- };
- };
- };
-
- in-ports {
- port {
- etf_in: endpoint {
- remote-endpoint =
- <&merge_funnel_out>;
- };
- };
- };
- };
-
- etr@6048000 {
- compatible = "arm,coresight-tmc", "arm,primecell";
- reg = <0x06048000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
- arm,scatter-gather;
-
- in-ports {
- port {
- etr_in: endpoint {
- remote-endpoint =
- <&replicator_out>;
- };
- };
- };
- };
-
- etm@7840000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07840000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- cpu = <&CPU0>;
-
- out-ports {
- port {
- etm0_out: endpoint {
- remote-endpoint =
- <&apss_funnel_in0>;
- };
- };
- };
- };
-
- etm@7940000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07940000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- cpu = <&CPU1>;
-
- out-ports {
- port {
- etm1_out: endpoint {
- remote-endpoint =
- <&apss_funnel_in1>;
- };
- };
- };
- };
-
- etm@7a40000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07a40000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- cpu = <&CPU2>;
-
- out-ports {
- port {
- etm2_out: endpoint {
- remote-endpoint =
- <&apss_funnel_in2>;
- };
- };
- };
- };
-
- etm@7b40000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07b40000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- cpu = <&CPU3>;
-
- out-ports {
- port {
- etm3_out: endpoint {
- remote-endpoint =
- <&apss_funnel_in3>;
- };
- };
- };
- };
-
- funnel@7b60000 { /* APSS Funnel */
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07b60000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- apss_funnel_out: endpoint {
- remote-endpoint =
- <&apss_merge_funnel_in>;
- };
- };
- };
-
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- apss_funnel_in0: endpoint {
- remote-endpoint =
- <&etm0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- apss_funnel_in1: endpoint {
- remote-endpoint =
- <&etm1_out>;
- };
- };
-
- port@2 {
- reg = <2>;
- apss_funnel_in2: endpoint {
- remote-endpoint =
- <&etm2_out>;
- };
- };
-
- port@3 {
- reg = <3>;
- apss_funnel_in3: endpoint {
- remote-endpoint =
- <&etm3_out>;
- };
- };
-
- port@4 {
- reg = <4>;
- apss_funnel_in4: endpoint {
- remote-endpoint =
- <&etm4_out>;
- };
- };
-
- port@5 {
- reg = <5>;
- apss_funnel_in5: endpoint {
- remote-endpoint =
- <&etm5_out>;
- };
- };
-
- port@6 {
- reg = <6>;
- apss_funnel_in6: endpoint {
- remote-endpoint =
- <&etm6_out>;
- };
- };
-
- port@7 {
- reg = <7>;
- apss_funnel_in7: endpoint {
- remote-endpoint =
- <&etm7_out>;
- };
- };
- };
- };
-
- funnel@7b70000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x07b70000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- apss_merge_funnel_out: endpoint {
- remote-endpoint =
- <&funnel1_in6>;
- };
- };
- };
-
- in-ports {
- port {
- apss_merge_funnel_in: endpoint {
- remote-endpoint =
- <&apss_funnel_out>;
- };
- };
- };
- };
-
- etm@7c40000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07c40000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- cpu = <&CPU4>;
-
- port{
- etm4_out: endpoint {
- remote-endpoint = <&apss_funnel_in4>;
- };
- };
- };
-
- etm@7d40000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07d40000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- cpu = <&CPU5>;
-
- port{
- etm5_out: endpoint {
- remote-endpoint = <&apss_funnel_in5>;
- };
- };
- };
-
- etm@7e40000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07e40000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- cpu = <&CPU6>;
-
- port{
- etm6_out: endpoint {
- remote-endpoint = <&apss_funnel_in6>;
- };
- };
- };
-
- etm@7f40000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x07f40000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- cpu = <&CPU7>;
-
- port{
- etm7_out: endpoint {
- remote-endpoint = <&apss_funnel_in7>;
- };
- };
- };
-
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0800f000 0x1000>,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: qcom: msm8998: Disable coresight by default
2019-10-03 12:53 ` Marc Gonzalez
@ 2019-10-03 15:21 ` Sai Prakash Ranjan
2019-10-03 16:23 ` Bjorn Andersson
1 sibling, 0 replies; 4+ messages in thread
From: Sai Prakash Ranjan @ 2019-10-03 15:21 UTC (permalink / raw)
To: Marc Gonzalez
Cc: Mark Rutland, DT, Mathieu Poirier, Suzuki K Poulose, MSM,
Jeffrey Hugo, Andy Gross, Bjorn Andersson, Rob Herring,
Linux ARM
On 2019-10-03 18:23, Marc Gonzalez wrote:
> On 03/10/2019 08:44, Sai Prakash Ranjan wrote:
>
>> Boot failure has been reported on MSM8998 based laptop when
>> coresight is enabled. This is most likely due to lack of
>> firmware support for coresight on production device when
>> compared to debug device like MTP where this issue is not
>> observed. So disable coresight by default for MSM8998 and
>> enable it only for MSM8998 MTP.
>>
>> Reported-and-tested-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
>> Fixes: 783abfa2249a ("arm64: dts: qcom: msm8998: Add Coresight
>> support")
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 68
>> +++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/msm8998.dtsi | 51 +++++++++++------
>> 2 files changed, 102 insertions(+), 17 deletions(-)
>
> Just wanted to toss an alternative, based on Suzuki's suggestion
> (i.e. move the coresight nodes to a separate file)
>
>
I believe this is a better approach.
Initially I had coresight components in a separate file like this but
Bjorn had some concerns about having 2 separate files. If he is OK with
this,
Acked-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: qcom: msm8998: Disable coresight by default
2019-10-03 12:53 ` Marc Gonzalez
2019-10-03 15:21 ` Sai Prakash Ranjan
@ 2019-10-03 16:23 ` Bjorn Andersson
1 sibling, 0 replies; 4+ messages in thread
From: Bjorn Andersson @ 2019-10-03 16:23 UTC (permalink / raw)
To: Marc Gonzalez
Cc: Mark Rutland, DT, Sai Prakash Ranjan, Mathieu Poirier,
Suzuki K Poulose, MSM, Jeffrey Hugo, Andy Gross, Rob Herring,
Linux ARM
On Thu 03 Oct 05:53 PDT 2019, Marc Gonzalez wrote:
> On 03/10/2019 08:44, Sai Prakash Ranjan wrote:
>
> > Boot failure has been reported on MSM8998 based laptop when
> > coresight is enabled. This is most likely due to lack of
> > firmware support for coresight on production device when
> > compared to debug device like MTP where this issue is not
> > observed. So disable coresight by default for MSM8998 and
> > enable it only for MSM8998 MTP.
> >
> > Reported-and-tested-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
> > Fixes: 783abfa2249a ("arm64: dts: qcom: msm8998: Add Coresight support")
> > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> > ---
> > arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 68 +++++++++++++++++++++++
> > arch/arm64/boot/dts/qcom/msm8998.dtsi | 51 +++++++++++------
> > 2 files changed, 102 insertions(+), 17 deletions(-)
>
> Just wanted to toss an alternative, based on Suzuki's suggestion
> (i.e. move the coresight nodes to a separate file)
>
For the particular case this seems quite reasonable; the conditional
inclusion of this file would indeed allow us to enable all the nodes at
once.
But I find it hard to navigate the dts files when the information they
are spread out over multiple files and the current split has rather
clear rules of what goes where.
Further more this probably not going to be the only thing that differs
between engineering devices and production devices, but I don't think
this split would scale to the various other cases.
Regards,
Bjorn
>
> arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi | 439 ++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 1 +
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 -----------------------
> 3 files changed, 440 insertions(+), 435 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi
> new file mode 100644
> index 000000000000..eabf4e4194fd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi
> @@ -0,0 +1,439 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */
> +
> +&soc {
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x06002000 0x1000>,
> + <0x16280000 0x180000>;
> + reg-names = "stm-base", "stm-data-base";
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint = <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x06041000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6042000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x06042000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + funnel1_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in1>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@6 {
> + reg = <6>;
> + funnel1_in6: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x06045000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + merge_funnel_in1: endpoint {
> + remote-endpoint =
> + <&funnel1_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x06046000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6047000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06047000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint =
> + <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + etf_in: endpoint {
> + remote-endpoint =
> + <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06048000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint =
> + <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7840000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07840000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU0>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7940000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07940000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU1>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7a40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07a40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU2>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7b40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07b40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU3>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + funnel@7b60000 { /* APSS Funnel */
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07b60000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7b70000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x07b70000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel1_in6>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7c40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07c40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU4>;
> +
> + port{
> + etm4_out: endpoint {
> + remote-endpoint = <&apss_funnel_in4>;
> + };
> + };
> + };
> +
> + etm@7d40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07d40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU5>;
> +
> + port{
> + etm5_out: endpoint {
> + remote-endpoint = <&apss_funnel_in5>;
> + };
> + };
> + };
> +
> + etm@7e40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07e40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU6>;
> +
> + port{
> + etm6_out: endpoint {
> + remote-endpoint = <&apss_funnel_in6>;
> + };
> + };
> + };
> +
> + etm@7f40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07f40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU7>;
> +
> + port{
> + etm7_out: endpoint {
> + remote-endpoint = <&apss_funnel_in7>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> index 108667ce4f31..9b586b3206fc 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> @@ -5,6 +5,7 @@
> #include "pm8998.dtsi"
> #include "pmi8998.dtsi"
> #include "pm8005.dtsi"
> +#include "msm8998-coresight.dtsi"
>
> / {
> aliases {
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index c6f81431983e..4b66a1c588f8 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -998,441 +998,6 @@
> #interrupt-cells = <0x2>;
> };
>
> - stm@6002000 {
> - compatible = "arm,coresight-stm", "arm,primecell";
> - reg = <0x06002000 0x1000>,
> - <0x16280000 0x180000>;
> - reg-names = "stm-base", "stm-data-base";
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - out-ports {
> - port {
> - stm_out: endpoint {
> - remote-endpoint = <&funnel0_in7>;
> - };
> - };
> - };
> - };
> -
> - funnel@6041000 {
> - compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> - reg = <0x06041000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - out-ports {
> - port {
> - funnel0_out: endpoint {
> - remote-endpoint =
> - <&merge_funnel_in0>;
> - };
> - };
> - };
> -
> - in-ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@7 {
> - reg = <7>;
> - funnel0_in7: endpoint {
> - remote-endpoint = <&stm_out>;
> - };
> - };
> - };
> - };
> -
> - funnel@6042000 {
> - compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> - reg = <0x06042000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - out-ports {
> - port {
> - funnel1_out: endpoint {
> - remote-endpoint =
> - <&merge_funnel_in1>;
> - };
> - };
> - };
> -
> - in-ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@6 {
> - reg = <6>;
> - funnel1_in6: endpoint {
> - remote-endpoint =
> - <&apss_merge_funnel_out>;
> - };
> - };
> - };
> - };
> -
> - funnel@6045000 {
> - compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> - reg = <0x06045000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - out-ports {
> - port {
> - merge_funnel_out: endpoint {
> - remote-endpoint =
> - <&etf_in>;
> - };
> - };
> - };
> -
> - in-ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> - merge_funnel_in0: endpoint {
> - remote-endpoint =
> - <&funnel0_out>;
> - };
> - };
> -
> - port@1 {
> - reg = <1>;
> - merge_funnel_in1: endpoint {
> - remote-endpoint =
> - <&funnel1_out>;
> - };
> - };
> - };
> - };
> -
> - replicator@6046000 {
> - compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> - reg = <0x06046000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - out-ports {
> - port {
> - replicator_out: endpoint {
> - remote-endpoint = <&etr_in>;
> - };
> - };
> - };
> -
> - in-ports {
> - port {
> - replicator_in: endpoint {
> - remote-endpoint = <&etf_out>;
> - };
> - };
> - };
> - };
> -
> - etf@6047000 {
> - compatible = "arm,coresight-tmc", "arm,primecell";
> - reg = <0x06047000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - out-ports {
> - port {
> - etf_out: endpoint {
> - remote-endpoint =
> - <&replicator_in>;
> - };
> - };
> - };
> -
> - in-ports {
> - port {
> - etf_in: endpoint {
> - remote-endpoint =
> - <&merge_funnel_out>;
> - };
> - };
> - };
> - };
> -
> - etr@6048000 {
> - compatible = "arm,coresight-tmc", "arm,primecell";
> - reg = <0x06048000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> - arm,scatter-gather;
> -
> - in-ports {
> - port {
> - etr_in: endpoint {
> - remote-endpoint =
> - <&replicator_out>;
> - };
> - };
> - };
> - };
> -
> - etm@7840000 {
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07840000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - cpu = <&CPU0>;
> -
> - out-ports {
> - port {
> - etm0_out: endpoint {
> - remote-endpoint =
> - <&apss_funnel_in0>;
> - };
> - };
> - };
> - };
> -
> - etm@7940000 {
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07940000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - cpu = <&CPU1>;
> -
> - out-ports {
> - port {
> - etm1_out: endpoint {
> - remote-endpoint =
> - <&apss_funnel_in1>;
> - };
> - };
> - };
> - };
> -
> - etm@7a40000 {
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07a40000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - cpu = <&CPU2>;
> -
> - out-ports {
> - port {
> - etm2_out: endpoint {
> - remote-endpoint =
> - <&apss_funnel_in2>;
> - };
> - };
> - };
> - };
> -
> - etm@7b40000 {
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07b40000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - cpu = <&CPU3>;
> -
> - out-ports {
> - port {
> - etm3_out: endpoint {
> - remote-endpoint =
> - <&apss_funnel_in3>;
> - };
> - };
> - };
> - };
> -
> - funnel@7b60000 { /* APSS Funnel */
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07b60000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - out-ports {
> - port {
> - apss_funnel_out: endpoint {
> - remote-endpoint =
> - <&apss_merge_funnel_in>;
> - };
> - };
> - };
> -
> - in-ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> - apss_funnel_in0: endpoint {
> - remote-endpoint =
> - <&etm0_out>;
> - };
> - };
> -
> - port@1 {
> - reg = <1>;
> - apss_funnel_in1: endpoint {
> - remote-endpoint =
> - <&etm1_out>;
> - };
> - };
> -
> - port@2 {
> - reg = <2>;
> - apss_funnel_in2: endpoint {
> - remote-endpoint =
> - <&etm2_out>;
> - };
> - };
> -
> - port@3 {
> - reg = <3>;
> - apss_funnel_in3: endpoint {
> - remote-endpoint =
> - <&etm3_out>;
> - };
> - };
> -
> - port@4 {
> - reg = <4>;
> - apss_funnel_in4: endpoint {
> - remote-endpoint =
> - <&etm4_out>;
> - };
> - };
> -
> - port@5 {
> - reg = <5>;
> - apss_funnel_in5: endpoint {
> - remote-endpoint =
> - <&etm5_out>;
> - };
> - };
> -
> - port@6 {
> - reg = <6>;
> - apss_funnel_in6: endpoint {
> - remote-endpoint =
> - <&etm6_out>;
> - };
> - };
> -
> - port@7 {
> - reg = <7>;
> - apss_funnel_in7: endpoint {
> - remote-endpoint =
> - <&etm7_out>;
> - };
> - };
> - };
> - };
> -
> - funnel@7b70000 {
> - compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> - reg = <0x07b70000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - out-ports {
> - port {
> - apss_merge_funnel_out: endpoint {
> - remote-endpoint =
> - <&funnel1_in6>;
> - };
> - };
> - };
> -
> - in-ports {
> - port {
> - apss_merge_funnel_in: endpoint {
> - remote-endpoint =
> - <&apss_funnel_out>;
> - };
> - };
> - };
> - };
> -
> - etm@7c40000 {
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07c40000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - cpu = <&CPU4>;
> -
> - port{
> - etm4_out: endpoint {
> - remote-endpoint = <&apss_funnel_in4>;
> - };
> - };
> - };
> -
> - etm@7d40000 {
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07d40000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - cpu = <&CPU5>;
> -
> - port{
> - etm5_out: endpoint {
> - remote-endpoint = <&apss_funnel_in5>;
> - };
> - };
> - };
> -
> - etm@7e40000 {
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07e40000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - cpu = <&CPU6>;
> -
> - port{
> - etm6_out: endpoint {
> - remote-endpoint = <&apss_funnel_in6>;
> - };
> - };
> - };
> -
> - etm@7f40000 {
> - compatible = "arm,coresight-etm4x", "arm,primecell";
> - reg = <0x07f40000 0x1000>;
> -
> - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> - clock-names = "apb_pclk", "atclk";
> -
> - cpu = <&CPU7>;
> -
> - port{
> - etm7_out: endpoint {
> - remote-endpoint = <&apss_funnel_in7>;
> - };
> - };
> - };
> -
> spmi_bus: spmi@800f000 {
> compatible = "qcom,spmi-pmic-arb";
> reg = <0x0800f000 0x1000>,
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2019-10-03 6:44 [PATCH] arm64: dts: qcom: msm8998: Disable coresight by default Sai Prakash Ranjan
2019-10-03 12:53 ` Marc Gonzalez
2019-10-03 15:21 ` Sai Prakash Ranjan
2019-10-03 16:23 ` Bjorn Andersson
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