* [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add USB controller nodes
2019-10-28 9:37 [PATCH 0/2] [PATCH 0/2] arm64: dts: ti: k3-j721e: Add USB ports Roger Quadros
@ 2019-10-28 9:37 ` Roger Quadros
2019-10-28 9:37 ` [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports Roger Quadros
2019-10-29 11:34 ` [PATCH 0/2] [PATCH 0/2] arm64: dts: ti: k3-j721e: " Roger Quadros
2 siblings, 0 replies; 5+ messages in thread
From: Roger Quadros @ 2019-10-28 9:37 UTC (permalink / raw)
To: t-kristo, nm; +Cc: Sekhar Nori, linux-kernel, linux-arm-kernel, Roger Quadros
J721e has 2 USB super-speed controllers add them.
The USB2 PHY doesn't need any configuration.
USB3 PHY needs to be implemented using the Cadence
Sierra PHY. This support will be added later.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 60 +++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +
2 files changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 5dd2a69402e6..1e4c2b78d66d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -536,4 +536,64 @@
dma-coherent;
no-1-8-v;
};
+
+ usbss0: cdns_usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x4104000 0x00 0x100>;
+ dma-coherent;
+ power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x6000000 0x00 0x10000>,
+ <0x00 0x6010000 0x00 0x10000>,
+ <0x00 0x6020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ usbss1: cdns_usb@4114000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x4114000 0x00 0x100>;
+ dma-coherent;
+ power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ usb1: usb@6400000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x6400000 0x00 0x10000>,
+ <0x00 0x6410000 0x00 0x10000>,
+ <0x00 0x6420000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 43ea1ba97922..ee5470edb435 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -127,6 +127,8 @@
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
+ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
+ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports
2019-10-28 9:37 [PATCH 0/2] [PATCH 0/2] arm64: dts: ti: k3-j721e: Add USB ports Roger Quadros
2019-10-28 9:37 ` [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add USB controller nodes Roger Quadros
@ 2019-10-28 9:37 ` Roger Quadros
2019-10-29 11:34 ` [PATCH 0/2] [PATCH 0/2] arm64: dts: ti: k3-j721e: " Roger Quadros
2 siblings, 0 replies; 5+ messages in thread
From: Roger Quadros @ 2019-10-28 9:37 UTC (permalink / raw)
To: t-kristo, nm; +Cc: Sekhar Nori, linux-kernel, linux-arm-kernel, Roger Quadros
Add USB0 as otg port and USB1 as host port.
Although USB0 can be used at super-speed, limit the
speed to high-speed for now till SERDES PHY support
is added.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 57df79a815f0..2a3cd6174504 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -55,6 +55,18 @@
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
};
+
+ main_usbss0_pins_default: main_usbss0_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ >;
+ };
+
+ main_usbss1_pins_default: main_usbss1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+ >;
+ };
};
&wkup_pmx0 {
@@ -244,3 +256,26 @@
/* Unused */
status = "disabled";
};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,usb2-only;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default>;
+ ti,usb2-only;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+};
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 0/2] [PATCH 0/2] arm64: dts: ti: k3-j721e: Add USB ports
2019-10-28 9:37 [PATCH 0/2] [PATCH 0/2] arm64: dts: ti: k3-j721e: Add USB ports Roger Quadros
2019-10-28 9:37 ` [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add USB controller nodes Roger Quadros
2019-10-28 9:37 ` [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports Roger Quadros
@ 2019-10-29 11:34 ` Roger Quadros
2019-11-08 9:43 ` Tero Kristo
2 siblings, 1 reply; 5+ messages in thread
From: Roger Quadros @ 2019-10-29 11:34 UTC (permalink / raw)
To: t-kristo, nm; +Cc: linux-kernel, linux-arm-kernel
Tero,
On 28/10/2019 11:37, Roger Quadros wrote:
> Hi,
>
> This series enables USB 2.0 support on j721e-common-proc-board.
>
> The USB0 is available as a type-C port. Although it is super-speed
> capable, we limit it to high-speed for now till SERDES PHY
> support is added.
>
> USB1 is routed via on-board USB2.0 hub to 2 type-A ports. USB1
> is used as high-speed host.
>
> Controller side DT binding is approved [1]. Driver [2] is yet to be
> in USB tree. This series is safe to be picked for -next.
Driver is now in Maintainer's tree.
https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git/commit/?h=testing/next&id=387c359b84f71ca29c1a9fa24293c65a257f6bf5
>
> [1] https://lkml.org/lkml/2019/10/25/1036
> [2] https://lkml.org/lkml/2019/10/24/371
>
> Series is based on top of Tero's ti-k3-next branch.
>
> cheers,
> -roger
>
> Roger Quadros (2):
> arm64: dts: ti: k3-j721e-main: add USB controller nodes
> arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports
>
> .../dts/ti/k3-j721e-common-proc-board.dts | 35 +++++++++++
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 60 +++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +
> 3 files changed, 97 insertions(+)
>
--
cheers,
-roger
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply [flat|nested] 5+ messages in thread