* [PATCH] clk: zynqmp: Correct bit index for divider flag
@ 2019-11-07 9:01 Rajan Vaja
2019-11-07 17:01 ` Michael Tretter
0 siblings, 1 reply; 2+ messages in thread
From: Rajan Vaja @ 2019-11-07 9:01 UTC (permalink / raw)
To: mturquette, sboyd, michal.simek, m.tretter, jollys
Cc: Jolly Shah, Rajan Vaja, linux-clk, linux-arm-kernel, linux-kernel
Update divider flag bit index to match with firmware.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/clk/zynqmp/divider.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index d8f5b70d..9e60834 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC Divider support
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Adjustable divider clock implementation
*/
@@ -25,7 +25,7 @@
#define to_zynqmp_clk_divider(_hw) \
container_of(_hw, struct zynqmp_clk_divider, hw)
-#define CLK_FRAC BIT(13) /* has a fractional parent */
+#define CLK_FRAC BIT(8) /* has a fractional parent */
/**
* struct zynqmp_clk_divider - adjustable divider clock
--
2.7.4
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: zynqmp: Correct bit index for divider flag
2019-11-07 9:01 [PATCH] clk: zynqmp: Correct bit index for divider flag Rajan Vaja
@ 2019-11-07 17:01 ` Michael Tretter
0 siblings, 0 replies; 2+ messages in thread
From: Michael Tretter @ 2019-11-07 17:01 UTC (permalink / raw)
To: Rajan Vaja
Cc: sboyd, mturquette, michal.simek, linux-kernel, jollys, kernel,
Jolly Shah, linux-clk, linux-arm-kernel
On Thu, 07 Nov 2019 01:01:30 -0800, Rajan Vaja wrote:
> Update divider flag bit index to match with firmware.
>
> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> drivers/clk/zynqmp/divider.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> index d8f5b70d..9e60834 100644
> --- a/drivers/clk/zynqmp/divider.c
> +++ b/drivers/clk/zynqmp/divider.c
> @@ -2,7 +2,7 @@
> /*
> * Zynq UltraScale+ MPSoC Divider support
> *
> - * Copyright (C) 2016-2018 Xilinx
> + * Copyright (C) 2016-2019 Xilinx
> *
> * Adjustable divider clock implementation
> */
> @@ -25,7 +25,7 @@
> #define to_zynqmp_clk_divider(_hw) \
> container_of(_hw, struct zynqmp_clk_divider, hw)
>
> -#define CLK_FRAC BIT(13) /* has a fractional parent */
> +#define CLK_FRAC BIT(8) /* has a fractional parent */
NACK.
This breaks the compatibility with the older/upstream versions of the
TF-A. You have to at least make this dependent on the used version of
the TF-A.
>
> /**
> * struct zynqmp_clk_divider - adjustable divider clock
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