From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: "Mark Rutland" <mark.rutland@arm.com>,
"Paul Elliott" <paul.elliott@arm.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Andrew Jones" <drjones@redhat.com>,
"Amit Kachhap" <amit.kachhap@arm.com>,
"Vincenzo Frascino" <vincenzo.frascino@arm.com>,
linux-arch@vger.kernel.org, "Marc Zyngier" <maz@kernel.org>,
"Eugene Syromiatnikov" <esyr@redhat.com>,
"Szabolcs Nagy" <szabolcs.nagy@arm.com>,
"Dave Martin" <Dave.Martin@arm.com>,
"H.J. Lu" <hjl.tools@gmail.com>,
"Yu-cheng Yu" <yu-cheng.yu@intel.com>,
"Kees Cook" <keescook@chromium.org>,
"Arnd Bergmann" <arnd@arndb.de>, "Jann Horn" <jannh@google.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Kristina Martšenko" <kristina.martsenko@arm.com>,
"Mark Brown" <broonie@kernel.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org,
"Florian Weimer" <fweimer@redhat.com>,
linux-kernel@vger.kernel.org, "Sudakshina Das" <sudi.das@arm.com>
Subject: [PATCH v4 08/12] arm64: unify native/compat instruction skipping
Date: Wed, 11 Dec 2019 15:42:02 +0000 [thread overview]
Message-ID: <20191211154206.46260-9-broonie@kernel.org> (raw)
In-Reply-To: <20191211154206.46260-1-broonie@kernel.org>
From: Dave Martin <Dave.Martin@arm.com>
Skipping of an instruction on AArch32 works a bit differently from
AArch64, mainly due to the different CPSR/PSTATE semantics.
Currently arm64_skip_faulting_instruction() is only suitable for
AArch64, and arm64_compat_skip_faulting_instruction() handles the IT
state machine but is local to traps.c.
Since manual instruction skipping implies a trap, it's a relatively
slow path.
So, make arm64_skip_faulting_instruction() handle both compat and
native, and get rid of the arm64_compat_skip_faulting_instruction()
special case.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/kernel/traps.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 84c7a88dd617..de01e5041d4d 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -269,6 +269,8 @@ void arm64_notify_die(const char *str, struct pt_regs *regs,
}
}
+static void advance_itstate(struct pt_regs *regs);
+
void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
{
regs->pc += size;
@@ -279,6 +281,9 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
*/
if (user_mode(regs))
user_fastforward_single_step(current);
+
+ if (regs->pstate & PSR_MODE32_BIT)
+ advance_itstate(regs);
}
static LIST_HEAD(undef_hook);
@@ -641,19 +646,12 @@ static void advance_itstate(struct pt_regs *regs)
compat_set_it_state(regs, it);
}
-static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs,
- unsigned int sz)
-{
- advance_itstate(regs);
- arm64_skip_faulting_instruction(regs, sz);
-}
-
static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
{
int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
pt_regs_write_reg(regs, reg, arch_timer_get_rate());
- arm64_compat_skip_faulting_instruction(regs, 4);
+ arm64_skip_faulting_instruction(regs, 4);
}
static const struct sys64_hook cp15_32_hooks[] = {
@@ -673,7 +671,7 @@ static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
pt_regs_write_reg(regs, rt, lower_32_bits(val));
pt_regs_write_reg(regs, rt2, upper_32_bits(val));
- arm64_compat_skip_faulting_instruction(regs, 4);
+ arm64_skip_faulting_instruction(regs, 4);
}
static const struct sys64_hook cp15_64_hooks[] = {
@@ -694,7 +692,7 @@ void do_cp15instr(unsigned int esr, struct pt_regs *regs)
* There is no T16 variant of a CP access, so we
* always advance PC by 4 bytes.
*/
- arm64_compat_skip_faulting_instruction(regs, 4);
+ arm64_skip_faulting_instruction(regs, 4);
return;
}
--
2.20.1
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next prev parent reply other threads:[~2019-12-11 15:45 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-11 15:41 [PATCH v4 00/12] arm64: ARMv8.5-A: Branch Target Identification support Mark Brown
2019-12-11 15:41 ` [PATCH v4 01/12] ELF: UAPI and Kconfig additions for ELF program properties Mark Brown
2020-01-14 15:03 ` Catalin Marinas
2019-12-11 15:41 ` [PATCH v4 02/12] ELF: Add ELF program property parsing support Mark Brown
2020-01-14 16:34 ` Catalin Marinas
2020-01-14 17:28 ` Mark Brown
2019-12-11 15:41 ` [PATCH v4 03/12] mm: Reserve asm-generic prot flag 0x10 for arch use Mark Brown
2019-12-12 10:48 ` Catalin Marinas
2019-12-12 16:16 ` Mark Brown
2019-12-11 15:41 ` [PATCH v4 04/12] arm64: Basic Branch Target Identification support Mark Brown
2020-01-10 18:28 ` Catalin Marinas
2020-01-13 14:00 ` Mark Brown
2019-12-11 15:41 ` [PATCH v4 05/12] elf: Allow arch to tweak initial mmap prot flags Mark Brown
2020-01-14 16:38 ` Catalin Marinas
2019-12-11 15:42 ` [PATCH v4 06/12] arm64: elf: Enable BTI at exec based on ELF program properties Mark Brown
2020-01-14 17:33 ` Catalin Marinas
2019-12-11 15:42 ` [PATCH v4 07/12] arm64: BTI: Decode BYTPE bits when printing PSTATE Mark Brown
2020-01-14 17:34 ` Catalin Marinas
2019-12-11 15:42 ` Mark Brown [this message]
2020-01-13 16:43 ` [PATCH v4 08/12] arm64: unify native/compat instruction skipping Catalin Marinas
2019-12-11 15:42 ` [PATCH v4 09/12] arm64: traps: Shuffle code to eliminate forward declarations Mark Brown
2020-01-14 17:35 ` Catalin Marinas
2019-12-11 15:42 ` [PATCH v4 10/12] arm64: BTI: Reset BTYPE when skipping emulated instructions Mark Brown
2020-01-14 17:36 ` Catalin Marinas
2019-12-11 15:42 ` [PATCH v4 11/12] KVM: " Mark Brown
2020-01-14 17:36 ` Catalin Marinas
2019-12-11 15:42 ` [PATCH v4 12/12] arm64: mm: Display guarded pages in ptdump Mark Brown
2020-01-14 17:37 ` Catalin Marinas
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