* [arm:cex7 76/92] drivers/net/dsa/mt7530.c:1357:57: sparse: sparse: incorrect type in argument 2 (different base types)
@ 2019-12-16 21:46 kbuild test robot
0 siblings, 0 replies; only message in thread
From: kbuild test robot @ 2019-12-16 21:46 UTC (permalink / raw)
To: Andrew Lunn; +Cc: Russell King, kbuild-all, linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git cex7
head: 806fad3799599b8167b4b0d448da9a93342b92ae
commit: ec4c5cc56eccdb9f569494a91464835363a0f805 [76/92] net: of_get_phy_mode: Change API to solve int/unit warnings
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-104-gf934193-dirty
git checkout ec4c5cc56eccdb9f569494a91464835363a0f805
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/net/dsa/mt7530.c:1357:57: sparse: sparse: incorrect type in argument 2 (different base types)
drivers/net/dsa/mt7530.c:1357:57: sparse: expected unsigned int enum phy_interface_t [usertype] *interface
drivers/net/dsa/mt7530.c:1357:57: sparse: got unsigned int enum phy_interface_t [addressable] [assigned] [usertype] interface
drivers/net/dsa/mt7530.c:1357:57: sparse: sparse: non size-preserving integer to pointer cast
vim +1357 drivers/net/dsa/mt7530.c
1238
1239 static int
1240 mt7530_setup(struct dsa_switch *ds)
1241 {
1242 struct mt7530_priv *priv = ds->priv;
1243 struct device_node *phy_node;
1244 struct device_node *mac_np;
1245 struct mt7530_dummy_poll p;
1246 phy_interface_t interface;
1247 struct device_node *dn;
1248 u32 id, val;
1249 int ret, i;
1250
1251 /* The parent node of master netdev which holds the common system
1252 * controller also is the container for two GMACs nodes representing
1253 * as two netdev instances.
1254 */
1255 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;
1256
1257 if (priv->id == ID_MT7530) {
1258 priv->ethernet = syscon_node_to_regmap(dn);
1259 if (IS_ERR(priv->ethernet))
1260 return PTR_ERR(priv->ethernet);
1261
1262 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1263 ret = regulator_enable(priv->core_pwr);
1264 if (ret < 0) {
1265 dev_err(priv->dev,
1266 "Failed to enable core power: %d\n", ret);
1267 return ret;
1268 }
1269
1270 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1271 ret = regulator_enable(priv->io_pwr);
1272 if (ret < 0) {
1273 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1274 ret);
1275 return ret;
1276 }
1277 }
1278
1279 /* Reset whole chip through gpio pin or memory-mapped registers for
1280 * different type of hardware
1281 */
1282 if (priv->mcm) {
1283 reset_control_assert(priv->rstc);
1284 usleep_range(1000, 1100);
1285 reset_control_deassert(priv->rstc);
1286 } else {
1287 gpiod_set_value_cansleep(priv->reset, 0);
1288 usleep_range(1000, 1100);
1289 gpiod_set_value_cansleep(priv->reset, 1);
1290 }
1291
1292 /* Waiting for MT7530 got to stable */
1293 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1294 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1295 20, 1000000);
1296 if (ret < 0) {
1297 dev_err(priv->dev, "reset timeout\n");
1298 return ret;
1299 }
1300
1301 id = mt7530_read(priv, MT7530_CREV);
1302 id >>= CHIP_NAME_SHIFT;
1303 if (id != MT7530_ID) {
1304 dev_err(priv->dev, "chip %x can't be supported\n", id);
1305 return -ENODEV;
1306 }
1307
1308 /* Reset the switch through internal reset */
1309 mt7530_write(priv, MT7530_SYS_CTRL,
1310 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1311 SYS_CTRL_REG_RST);
1312
1313 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1314 val = mt7530_read(priv, MT7530_MHWTRAP);
1315 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1316 val |= MHWTRAP_MANUAL;
1317 mt7530_write(priv, MT7530_MHWTRAP, val);
1318
1319 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1320
1321 /* Enable and reset MIB counters */
1322 mt7530_mib_reset(ds);
1323
1324 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
1325
1326 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1327 /* Disable forwarding by default on all ports */
1328 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1329 PCR_MATRIX_CLR);
1330
1331 if (dsa_is_cpu_port(ds, i))
1332 mt7530_cpu_port_enable(priv, i);
1333 else
1334 mt7530_port_disable(ds, i);
1335 }
1336
1337 /* Setup port 5 */
1338 priv->p5_intf_sel = P5_DISABLED;
1339 interface = PHY_INTERFACE_MODE_NA;
1340
1341 if (!dsa_is_unused_port(ds, 5)) {
1342 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1343 of_get_phy_mode(ds->ports[5].dn, &interface);
1344 } else {
1345 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1346 for_each_child_of_node(dn, mac_np) {
1347 if (!of_device_is_compatible(mac_np,
1348 "mediatek,eth-mac"))
1349 continue;
1350
1351 ret = of_property_read_u32(mac_np, "reg", &id);
1352 if (ret < 0 || id != 1)
1353 continue;
1354
1355 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
1356 if (phy_node->parent == priv->dev->of_node->parent) {
> 1357 of_get_phy_mode(mac_np, interface);
1358 id = of_mdio_parse_addr(ds->dev, phy_node);
1359 if (id == 0)
1360 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1361 if (id == 4)
1362 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1363 }
1364 of_node_put(phy_node);
1365 break;
1366 }
1367 }
1368
1369 mt7530_setup_port5(ds, interface);
1370
1371 /* Flush the FDB table */
1372 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1373 if (ret < 0)
1374 return ret;
1375
1376 return 0;
1377 }
1378
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