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* [PATCH 0/2] Add clock support for Bitmain BM1880
@ 2020-01-14  4:03 Manivannan Sadhasivam
  2020-01-14  4:03 ` [PATCH 1/2] arm64: dts: bitmain: Add clock controller support for BM1880 SoC Manivannan Sadhasivam
  2020-01-14  4:03 ` [PATCH 2/2] arm64: dts: bitmain: Source common clock for UART controllers Manivannan Sadhasivam
  0 siblings, 2 replies; 3+ messages in thread
From: Manivannan Sadhasivam @ 2020-01-14  4:03 UTC (permalink / raw)
  To: soc; +Cc: sboyd, linux-arm-kernel, Manivannan Sadhasivam

Hi Arnd, Olof,

For 5.6 cycle, I have only couple of patches for Bitmain platform, hence
sending to list directly instead of a PR. These patches adds clock support
to the BM1880 SoC. The driver and binding patches are merged by the clock
maintainer for 5.5 cycle.

Please consider applying.

Thanks,
Mani

Manivannan Sadhasivam (2):
  arm64: dts: bitmain: Add clock controller support for BM1880 SoC
  arm64: dts: bitmain: Source common clock for UART controllers

 .../boot/dts/bitmain/bm1880-sophon-edge.dts   |  9 ------
 arch/arm64/boot/dts/bitmain/bm1880.dtsi       | 28 +++++++++++++++++++
 2 files changed, 28 insertions(+), 9 deletions(-)

-- 
2.17.1


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^ permalink raw reply	[flat|nested] 3+ messages in thread
* [PATCH 1/2] arm64: dts: bitmain: Add clock controller support for BM1880 SoC
  2020-01-14  4:03 [PATCH 0/2] Add clock support for Bitmain BM1880 Manivannan Sadhasivam
@ 2020-01-14  4:03 ` Manivannan Sadhasivam
  2020-01-14  4:03 ` [PATCH 2/2] arm64: dts: bitmain: Source common clock for UART controllers Manivannan Sadhasivam
  1 sibling, 0 replies; 3+ messages in thread
From: Manivannan Sadhasivam @ 2020-01-14  4:03 UTC (permalink / raw)
  To: soc; +Cc: sboyd, linux-arm-kernel, Manivannan Sadhasivam

Add clock controller support for Bitmain BM1880 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/bitmain/bm1880.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
index d65453f99a99..8471662413da 100644
--- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
@@ -4,6 +4,7 @@
  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  */
 
+#include <dt-bindings/clock/bm1880-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
 
@@ -66,6 +67,12 @@
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	osc: osc {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		#clock-cells = <0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -94,6 +101,15 @@
 				reg = <0x400 0x120>;
 			};
 
+			clk: clock-controller@e8 {
+				compatible = "bitmain,bm1880-clk";
+				reg = <0xe8 0x0c>, <0x800 0xb0>;
+				reg-names = "pll", "sys";
+				clocks = <&osc>;
+				clock-names = "osc";
+				#clock-cells = <1>;
+			};
+
 			rst: reset-controller@c00 {
 				compatible = "bitmain,bm1880-reset";
 				reg = <0xc00 0x8>;
-- 
2.17.1


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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* [PATCH 2/2] arm64: dts: bitmain: Source common clock for UART controllers
  2020-01-14  4:03 [PATCH 0/2] Add clock support for Bitmain BM1880 Manivannan Sadhasivam
  2020-01-14  4:03 ` [PATCH 1/2] arm64: dts: bitmain: Add clock controller support for BM1880 SoC Manivannan Sadhasivam
@ 2020-01-14  4:03 ` Manivannan Sadhasivam
  1 sibling, 0 replies; 3+ messages in thread
From: Manivannan Sadhasivam @ 2020-01-14  4:03 UTC (permalink / raw)
  To: soc; +Cc: sboyd, linux-arm-kernel, Manivannan Sadhasivam

Remove fixed clock and source common clock for UART controllers.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts |  9 ---------
 arch/arm64/boot/dts/bitmain/bm1880.dtsi            | 12 ++++++++++++
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
index 3e8c70778e24..7a2c7f9c2660 100644
--- a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
+++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
@@ -49,12 +49,6 @@
 		reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
 	};
 
-	uart_clk: uart-clk {
-		compatible = "fixed-clock";
-		clock-frequency = <500000000>;
-		#clock-cells = <0>;
-	};
-
 	soc {
 		gpio0: gpio@50027000 {
 			porta: gpio-controller@0 {
@@ -173,21 +167,18 @@
 
 &uart0 {
 	status = "okay";
-	clocks = <&uart_clk>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 &uart1 {
 	status = "okay";
-	clocks = <&uart_clk>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
 &uart2 {
 	status = "okay";
-	clocks = <&uart_clk>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2_default>;
 };
diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
index 8471662413da..fa6e6905f588 100644
--- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
@@ -174,6 +174,9 @@
 		uart0: serial@58018000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x58018000 0x0 0x2000>;
+			clocks = <&clk BM1880_CLK_UART_500M>,
+				 <&clk BM1880_CLK_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -184,6 +187,9 @@
 		uart1: serial@5801A000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x5801a000 0x0 0x2000>;
+			clocks = <&clk BM1880_CLK_UART_500M>,
+				 <&clk BM1880_CLK_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -194,6 +200,9 @@
 		uart2: serial@5801C000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x5801c000 0x0 0x2000>;
+			clocks = <&clk BM1880_CLK_UART_500M>,
+				 <&clk BM1880_CLK_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -204,6 +213,9 @@
 		uart3: serial@5801E000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x5801e000 0x0 0x2000>;
+			clocks = <&clk BM1880_CLK_UART_500M>,
+				 <&clk BM1880_CLK_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-- 
2.17.1


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^ permalink raw reply related	[flat|nested] 3+ messages in thread
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2020-01-14  4:03 [PATCH 0/2] Add clock support for Bitmain BM1880 Manivannan Sadhasivam
2020-01-14  4:03 ` [PATCH 1/2] arm64: dts: bitmain: Add clock controller support for BM1880 SoC Manivannan Sadhasivam
2020-01-14  4:03 ` [PATCH 2/2] arm64: dts: bitmain: Source common clock for UART controllers Manivannan Sadhasivam

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