From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <maxime@cerno.tech>,
Mark Rutland <Mark.Rutland@arm.com>,
Rob Herring <robh@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>,
linux-arm-kernel@lists.infradead.org,
Maxime Ripard <mripard@kernel.org>
Subject: Re: [PATCH 1/2] arm64: dts: allwinner: h5: Fix PMU compatible
Date: Fri, 14 Feb 2020 18:04:04 +0000 [thread overview]
Message-ID: <20200214180404.24d67f86@donnerap.cambridge.arm.com> (raw)
In-Reply-To: <20200210095600.77894-1-maxime@cerno.tech>
On Mon, 10 Feb 2020 10:55:59 +0100
Maxime Ripard <maxime@cerno.tech> wrote:
Hi,
> The commit c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node")
> introduced support for the PMU found on the Allwinner H5. However, the
> binding only allows for a single compatible, while the patch was adding
> two.
Maxime, thanks for bringing this up, was that found by some validation tool?
And while this is true, I wonder if this was intentional?
I see several other combinations of PMU compatibles in the tree.
Mark, Rob, can you shed any light on this?
Actually I am wondering why we would need the PMU type in the first place, isn't that discoverable via the MIDR?
And all we actually need from the DT is the interrupts and maybe some quirk info?
It looks like ACPI is always using the generic PMUv3 map, so wouldn't it actually be better to replace the compatible string matching with MIDR matching? Or are those core specific maps somewhat obsolete anyway? Since I don't see any newer cores in there?
Cheers,
Andre
> Make sure we follow the binding.
>
> Fixes: c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node")
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
> index 9893aa64dd0b..4462a68c0681 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
> @@ -38,8 +38,7 @@ cpu3: cpu@3 {
> };
>
> pmu {
> - compatible = "arm,cortex-a53-pmu",
> - "arm,armv8-pmuv3";
> + compatible = "arm,cortex-a53-pmu";
> interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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next prev parent reply other threads:[~2020-02-14 18:04 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-10 9:55 [PATCH 1/2] arm64: dts: allwinner: h5: Fix PMU compatible Maxime Ripard
2020-02-10 9:56 ` [PATCH 2/2] arm64: dts: allwinner: h6: " Maxime Ripard
2020-02-25 9:03 ` Maxime Ripard
2020-02-14 18:04 ` Andre Przywara [this message]
2020-02-14 18:18 ` [PATCH 1/2] arm64: dts: allwinner: h5: " Robin Murphy
2020-02-17 17:49 ` Maxime Ripard
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