* [PATCH 00/10] MMP2 CLK Update
@ 2020-02-19 7:33 Lubomir Rintel
2020-02-19 7:33 ` [PATCH 01/10] clk: mmp2: Remove a unused prototype Lubomir Rintel
` (9 more replies)
0 siblings, 10 replies; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Rob Herring, linux-clk, linux-arm-kernel
Hi,
please consider applying this patch series. Its goal is to ultimately
provide accurate clock sources from PLLs configured by firmware on MMP2 and
MMP3. Currently they are hardcoded to more or less wrong values, which
causes bad timings when they are use (e.g. to generate display clock).
It starts off with a handful of cleanups:
[PATCH 01/10] clk: mmp2: Remove a unused prototype
[PATCH 02/10] clk: mmp2: Constify some strings
[PATCH 03/10] dt-bindings: clock: Convert marvell,mmp2-clock to
The next patch adds the logic for calculating the rate of clock signals
coming from the PLLs dynamically, while not actually switching the
driver over to using it.
[PATCH 04/10] clk: mmp2: Add support for PLL clock sources
Then MMP2 is switched over:
[PATCH 05/10] clk: mmp2: Stop pretending PLL outputs are constant
Switching MMP3 requires some more work, because until now, the driver
has been the same for both versions of the SoC:
[PATCH 06/10] dt-bindings: clock: Add MMP3 compatible string
[PATCH 07/10] clk: mmp2: Check for MMP3
[PATCH 08/10] dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs
[PATCH 09/10] clk: mmp2: Add PLLs that are available on MMP3
[PATCH 10/10] ARM: dts: mmp3: Use the MMP3 compatible string for
The hardware vendor doesn't supply documentation, so this is best-effort
work based on the code dump from Marvell.
Tested on MMP2 and MMP3 based hardware I have; details in relevant
commit messages.
Thank you,
Lubo
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 01/10] clk: mmp2: Remove a unused prototype
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-19 7:33 ` [PATCH 02/10] clk: mmp2: Constify some strings Lubomir Rintel
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
There is no mmp_clk_register_pll2() routine.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/clk.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index 70bb73257647a..5bcbced3f458e 100644
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -124,9 +124,6 @@ extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
u32 val_disable, unsigned int gate_flags,
spinlock_t *lock);
-
-extern struct clk *mmp_clk_register_pll2(const char *name,
- const char *parent_name, unsigned long flags);
extern struct clk *mmp_clk_register_apbc(const char *name,
const char *parent_name, void __iomem *base,
unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 02/10] clk: mmp2: Constify some strings
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
2020-02-19 7:33 ` [PATCH 01/10] clk: mmp2: Remove a unused prototype Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-19 7:33 ` [PATCH 03/10] dt-bindings: clock: Convert marvell, mmp2-clock to json-schema Lubomir Rintel
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
All the parent clock names for the muxes are constant. Add const.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/clk-mix.c | 2 +-
drivers/clk/mmp/clk-of-mmp2.c | 13 +++++++------
drivers/clk/mmp/clk.h | 4 ++--
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
index d2cd36c54474f..7a351ec65564e 100644
--- a/drivers/clk/mmp/clk-mix.c
+++ b/drivers/clk/mmp/clk-mix.c
@@ -441,7 +441,7 @@ const struct clk_ops mmp_clk_mix_ops = {
struct clk *mmp_clk_register_mix(struct device *dev,
const char *name,
- const char **parent_names,
+ const char * const *parent_names,
u8 num_parents,
unsigned long flags,
struct mmp_clk_mix_config *config,
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index 6e71591e63a00..ee086d9714160 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -127,16 +127,16 @@ static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
static DEFINE_SPINLOCK(uart0_lock);
static DEFINE_SPINLOCK(uart1_lock);
static DEFINE_SPINLOCK(uart2_lock);
-static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
+static const char * const uart_parent_names[] = {"uart_pll", "vctcxo"};
static DEFINE_SPINLOCK(ssp0_lock);
static DEFINE_SPINLOCK(ssp1_lock);
static DEFINE_SPINLOCK(ssp2_lock);
static DEFINE_SPINLOCK(ssp3_lock);
-static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
+static const char * const ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
static DEFINE_SPINLOCK(timer_lock);
-static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
+static const char * const timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
static DEFINE_SPINLOCK(reset_lock);
@@ -190,7 +190,7 @@ static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
}
static DEFINE_SPINLOCK(sdh_lock);
-static const char *sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
+static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
static struct mmp_clk_mix_config sdh_mix_config = {
.reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
};
@@ -201,11 +201,12 @@ static DEFINE_SPINLOCK(usbhsic1_lock);
static DEFINE_SPINLOCK(disp0_lock);
static DEFINE_SPINLOCK(disp1_lock);
-static const char *disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
+static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
static DEFINE_SPINLOCK(ccic0_lock);
static DEFINE_SPINLOCK(ccic1_lock);
-static const char *ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
+static const char * const ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
+
static struct mmp_clk_mix_config ccic0_mix_config = {
.reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
};
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index 5bcbced3f458e..37d1e1d7b664c 100644
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -97,7 +97,7 @@ struct mmp_clk_mix {
extern const struct clk_ops mmp_clk_mix_ops;
extern struct clk *mmp_clk_register_mix(struct device *dev,
const char *name,
- const char **parent_names,
+ const char * const *parent_names,
u8 num_parents,
unsigned long flags,
struct mmp_clk_mix_config *config,
@@ -193,7 +193,7 @@ void mmp_register_gate_clks(struct mmp_clk_unit *unit,
struct mmp_param_mux_clk {
unsigned int id;
char *name;
- const char **parent_name;
+ const char * const *parent_name;
u8 num_parents;
unsigned long flags;
unsigned long offset;
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 03/10] dt-bindings: clock: Convert marvell, mmp2-clock to json-schema
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
2020-02-19 7:33 ` [PATCH 01/10] clk: mmp2: Remove a unused prototype Lubomir Rintel
2020-02-19 7:33 ` [PATCH 02/10] clk: mmp2: Constify some strings Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-26 15:28 ` [PATCH 03/10] dt-bindings: clock: Convert marvell,mmp2-clock " Rob Herring
2020-02-19 7:33 ` [PATCH 04/10] clk: mmp2: Add support for PLL clock sources Lubomir Rintel
` (6 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
Convert the fixed-factor-clock binding to DT schema format using
json-schema.
While at that, fix a couple of small errors: make the file base name
match the compatible string, add an example and document the reg-names
property.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
.../bindings/clock/marvell,mmp2-clock.yaml | 62 +++++++++++++++++++
.../bindings/clock/marvell,mmp2.txt | 21 -------
2 files changed, 62 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/marvell,mmp2.txt
diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml
new file mode 100644
index 0000000000000..c5fc2ad0236dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP2 Clock Controller
+
+maintainers:
+ - Lubomir Rintel <lkundrak@v3.sk>
+
+description: |
+ The MMP2 clock subsystem generates and supplies clock to various
+ controllers within the MMP2 SoC.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
+
+properties:
+ compatible:
+ const: marvell,mmp2-clock # controller compatible with MMP2 SoC
+
+ reg:
+ items:
+ - description: MPMU register region
+ - description: APMU register region
+ - description: APBC register region
+
+ reg-names:
+ items:
+ - const: mpmu
+ - const: apmu
+ - const: apbc
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@d4050000 {
+ compatible = "marvell,mmp2-clock";
+ reg = <0xd4050000 0x1000>,
+ <0xd4282800 0x400>,
+ <0xd4015000 0x1000>;
+ reg-names = "mpmu", "apmu", "apbc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt
deleted file mode 100644
index 23b52dc02266a..0000000000000
--- a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Marvell MMP2 Clock Controller
-
-The MMP2 clock subsystem generates and supplies clock to various
-controllers within the MMP2 SoC.
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
-
-- reg: physical base address of the clock subsystem and length of memory mapped
- region. There are 3 places in SOC has clock control logic:
- "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
-
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes use this identifier
-to specify the clock which they consume.
-
-All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 04/10] clk: mmp2: Add support for PLL clock sources
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
` (2 preceding siblings ...)
2020-02-19 7:33 ` [PATCH 03/10] dt-bindings: clock: Convert marvell, mmp2-clock to json-schema Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-19 7:33 ` [PATCH 05/10] clk: mmp2: Stop pretending PLL outputs are constant Lubomir Rintel
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are
constant, but in fact they are configurable.
Add logic for obtaining the actual clock rates on MMP2 as well as MMP3.
There is no documentation for either SoC, but the "systemsetting" drivers
from Marvell GPL code dump provide some clue as far as MPMU registers on
MMP2 [1] and MMP3 [2] go.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c
[2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c
A separate commit will adjust the clk-of-mmp2 driver.
Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC
XO-1.75 laptop.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-pll.c | 139 ++++++++++++++++++++++++++++++++++++++
drivers/clk/mmp/clk.c | 31 +++++++++
drivers/clk/mmp/clk.h | 24 +++++++
4 files changed, 195 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mmp/clk-pll.c
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index acc141adf087c..14dc8a8a9d087 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -8,7 +8,7 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
-obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o
+obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-pll.c b/drivers/clk/mmp/clk-pll.c
new file mode 100644
index 0000000000000..7077be2938711
--- /dev/null
+++ b/drivers/clk/mmp/clk-pll.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * MMP PLL clock rate calculation
+ *
+ * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+#include "clk.h"
+
+#define to_clk_mmp_pll(hw) container_of(hw, struct mmp_clk_pll, hw)
+
+struct mmp_clk_pll {
+ struct clk_hw hw;
+ unsigned long default_rate;
+ void __iomem *enable_reg;
+ u32 enable;
+ void __iomem *reg;
+ u8 shift;
+
+ unsigned long input_rate;
+ void __iomem *postdiv_reg;
+ u8 postdiv_shift;
+};
+
+static int mmp_clk_pll_is_enabled(struct clk_hw *hw)
+{
+ struct mmp_clk_pll *pll = to_clk_mmp_pll(hw);
+ u32 val;
+
+ val = readl_relaxed(pll->enable_reg);
+ if ((val & pll->enable) == pll->enable)
+ return 1;
+
+ /* Some PLLs, if not software controlled, output default clock. */
+ if (pll->default_rate > 0)
+ return 1;
+
+ return 0;
+}
+
+static unsigned long mmp_clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct mmp_clk_pll *pll = to_clk_mmp_pll(hw);
+ u32 fbdiv, refdiv, postdiv;
+ u64 rate;
+ u32 val;
+
+ val = readl_relaxed(pll->enable_reg);
+ if ((val & pll->enable) != pll->enable)
+ return pll->default_rate;
+
+ if (pll->reg) {
+ val = readl_relaxed(pll->reg);
+ fbdiv = (val >> pll->shift) & 0x1ff;
+ refdiv = (val >> (pll->shift + 9)) & 0x1f;
+ } else {
+ fbdiv = 2;
+ refdiv = 1;
+ }
+
+ if (pll->postdiv_reg) {
+ /* MMP3 clock rate calculation */
+ static const u8 postdivs[] = {2, 3, 4, 5, 6, 8, 10, 12, 16};
+
+ val = readl_relaxed(pll->postdiv_reg);
+ postdiv = (val >> pll->postdiv_shift) & 0x7;
+
+ rate = pll->input_rate;
+ rate *= 2 * fbdiv;
+ do_div(rate, refdiv);
+ do_div(rate, postdivs[postdiv]);
+ } else {
+ /* MMP2 clock rate calculation */
+ if (refdiv == 3) {
+ rate = 19200000;
+ } else if (refdiv == 4) {
+ rate = 26000000;
+ } else {
+ pr_err("bad refdiv: %d (0x%08x)\n", refdiv, val);
+ return 0;
+ }
+
+ rate *= fbdiv + 2;
+ do_div(rate, refdiv + 2);
+ }
+
+ return (unsigned long)rate;
+}
+
+static const struct clk_ops mmp_clk_pll_ops = {
+ .is_enabled = mmp_clk_pll_is_enabled,
+ .recalc_rate = mmp_clk_pll_recalc_rate,
+};
+
+struct clk *mmp_clk_register_pll(char *name,
+ unsigned long default_rate,
+ void __iomem *enable_reg, u32 enable,
+ void __iomem *reg, u8 shift,
+ unsigned long input_rate,
+ void __iomem *postdiv_reg, u8 postdiv_shift)
+{
+ struct mmp_clk_pll *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &mmp_clk_pll_ops;
+ init.flags = 0;
+ init.parent_names = NULL;
+ init.num_parents = 0;
+
+ pll->default_rate = default_rate;
+ pll->enable_reg = enable_reg;
+ pll->enable = enable;
+ pll->reg = reg;
+ pll->shift = shift;
+
+ pll->input_rate = input_rate;
+ pll->postdiv_reg = postdiv_reg;
+ pll->postdiv_shift = postdiv_shift;
+
+ pll->hw.init = &init;
+
+ clk = clk_register(NULL, &pll->hw);
+
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
diff --git a/drivers/clk/mmp/clk.c b/drivers/clk/mmp/clk.c
index ca7d37e2c7be6..317123641d1ed 100644
--- a/drivers/clk/mmp/clk.c
+++ b/drivers/clk/mmp/clk.c
@@ -176,6 +176,37 @@ void mmp_register_div_clks(struct mmp_clk_unit *unit,
}
}
+void mmp_register_pll_clks(struct mmp_clk_unit *unit,
+ struct mmp_param_pll_clk *clks,
+ void __iomem *base, int size)
+{
+ struct clk *clk;
+ int i;
+
+ for (i = 0; i < size; i++) {
+ void __iomem *reg = NULL;
+
+ if (clks[i].offset)
+ reg = base + clks[i].offset;
+
+ clk = mmp_clk_register_pll(clks[i].name,
+ clks[i].default_rate,
+ base + clks[i].enable_offset,
+ clks[i].enable,
+ reg, clks[i].shift,
+ clks[i].input_rate,
+ base + clks[i].postdiv_offset,
+ clks[i].postdiv_shift);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ if (clks[i].id)
+ unit->clk_table[clks[i].id] = clk;
+ }
+}
+
void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
struct clk *clk)
{
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index 37d1e1d7b664c..971b4d6d992fb 100644
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -221,6 +221,30 @@ void mmp_register_div_clks(struct mmp_clk_unit *unit,
struct mmp_param_div_clk *clks,
void __iomem *base, int size);
+struct mmp_param_pll_clk {
+ unsigned int id;
+ char *name;
+ unsigned long default_rate;
+ unsigned long enable_offset;
+ u32 enable;
+ unsigned long offset;
+ u8 shift;
+ /* MMP3 specific: */
+ unsigned long input_rate;
+ unsigned long postdiv_offset;
+ unsigned long postdiv_shift;
+};
+void mmp_register_pll_clks(struct mmp_clk_unit *unit,
+ struct mmp_param_pll_clk *clks,
+ void __iomem *base, int size);
+
+extern struct clk *mmp_clk_register_pll(char *name,
+ unsigned long default_rate,
+ void __iomem *enable_reg, u32 enable,
+ void __iomem *reg, u8 shift,
+ unsigned long input_rate,
+ void __iomem *postdiv_reg, u8 postdiv_shift);
+
#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
{ \
.width_div = (w_d), \
--
2.24.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 05/10] clk: mmp2: Stop pretending PLL outputs are constant
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
` (3 preceding siblings ...)
2020-02-19 7:33 ` [PATCH 04/10] clk: mmp2: Add support for PLL clock sources Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-19 7:33 ` [PATCH 06/10] dt-bindings: clock: Add MMP3 compatible string Lubomir Rintel
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly off -- it
defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default, but also
configurable.
Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various
values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and
set-pll2-988mhz Open Firmware words.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/clk-of-mmp2.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index ee086d9714160..251d8d0e78abb 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2012 Marvell
* Chao Xie <xiechao.mail@gmail.com>
+ * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
@@ -55,7 +56,11 @@
#define APMU_CCIC1 0xf4
#define APMU_USBHSIC0 0xf8
#define APMU_USBHSIC1 0xfc
+
+#define MPMU_FCCR 0x8
+#define MPMU_POSR 0x10
#define MPMU_UART_PLL 0x14
+#define MPMU_PLL2_CR 0x34
struct mmp2_clk_unit {
struct mmp_clk_unit unit;
@@ -67,11 +72,14 @@ struct mmp2_clk_unit {
static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
{MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
{MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
- {MMP2_CLK_PLL1, "pll1", NULL, 0, 800000000},
- {MMP2_CLK_PLL2, "pll2", NULL, 0, 960000000},
{MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
};
+static struct mmp_param_pll_clk pll_clks[] = {
+ {MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0},
+ {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
+};
+
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
{MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
{MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
@@ -113,6 +121,10 @@ static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
ARRAY_SIZE(fixed_rate_clks));
+ mmp_register_pll_clks(unit, pll_clks,
+ pxa_unit->mpmu_base,
+ ARRAY_SIZE(pll_clks));
+
mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
ARRAY_SIZE(fixed_factor_clks));
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 06/10] dt-bindings: clock: Add MMP3 compatible string
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
` (4 preceding siblings ...)
2020-02-19 7:33 ` [PATCH 05/10] clk: mmp2: Stop pretending PLL outputs are constant Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-26 15:28 ` Rob Herring
2020-02-19 7:33 ` [PATCH 07/10] clk: mmp2: Check for MMP3 Lubomir Rintel
` (3 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
This binding describes the PMUs that are found on MMP3 as well. Add the
compatible strings and adjust the description.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
.../devicetree/bindings/clock/marvell,mmp2-clock.yaml | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml
index c5fc2ad0236dd..e2b6ac96bbcb0 100644
--- a/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml
@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Marvell MMP2 Clock Controller
+title: Marvell MMP2 and MMP3 Clock Controller
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
description: |
- The MMP2 clock subsystem generates and supplies clock to various
- controllers within the MMP2 SoC.
+ The clock subsystem on MMP2 or MMP3 generates and supplies clock to various
+ controllers within the SoC.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
@@ -20,7 +20,9 @@ description: |
properties:
compatible:
- const: marvell,mmp2-clock # controller compatible with MMP2 SoC
+ enum:
+ - marvell,mmp2-clock # controller compatible with MMP2 SoC
+ - marvell,mmp3-clock # controller compatible with MMP3 SoC
reg:
items:
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 07/10] clk: mmp2: Check for MMP3
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
` (5 preceding siblings ...)
2020-02-19 7:33 ` [PATCH 06/10] dt-bindings: clock: Add MMP3 compatible string Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-19 7:33 ` [PATCH 08/10] dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs Lubomir Rintel
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
The MMP3's are similar enough to MMP2, but there are differencies, such
are more clocks available on the newer model. We want to tell which
platform are we on.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/clk-of-mmp2.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index 251d8d0e78abb..7594a8280b93a 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -62,8 +62,14 @@
#define MPMU_UART_PLL 0x14
#define MPMU_PLL2_CR 0x34
+enum mmp2_clk_model {
+ CLK_MODEL_MMP2,
+ CLK_MODEL_MMP3,
+};
+
struct mmp2_clk_unit {
struct mmp_clk_unit unit;
+ enum mmp2_clk_model model;
void __iomem *mpmu_base;
void __iomem *apmu_base;
void __iomem *apbc_base;
@@ -326,6 +332,11 @@ static void __init mmp2_clk_init(struct device_node *np)
if (!pxa_unit)
return;
+ if (of_device_is_compatible(np, "marvell,mmp3-clock"))
+ pxa_unit->model = CLK_MODEL_MMP3;
+ else
+ pxa_unit->model = CLK_MODEL_MMP2;
+
pxa_unit->mpmu_base = of_iomap(np, 0);
if (!pxa_unit->mpmu_base) {
pr_err("failed to map mpmu registers\n");
@@ -365,3 +376,4 @@ static void __init mmp2_clk_init(struct device_node *np)
}
CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
+CLK_OF_DECLARE(mmp3_clk, "marvell,mmp3-clock", mmp2_clk_init);
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 08/10] dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
` (6 preceding siblings ...)
2020-02-19 7:33 ` [PATCH 07/10] clk: mmp2: Check for MMP3 Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-26 15:29 ` Rob Herring
2020-02-19 7:33 ` [PATCH 09/10] clk: mmp2: Add PLLs that are available on MMP3 Lubomir Rintel
2020-02-19 7:33 ` [PATCH 10/10] ARM: dts: mmp3: Use the MMP3 compatible string for /clocks Lubomir Rintel
9 siblings, 1 reply; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
MMP3 variant provides some more clocks. Add respective IDs.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
include/dt-bindings/clock/marvell,mmp2.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
index 4b1a7724f20d7..22006392b411b 100644
--- a/include/dt-bindings/clock/marvell,mmp2.h
+++ b/include/dt-bindings/clock/marvell,mmp2.h
@@ -26,6 +26,9 @@
#define MMP2_CLK_VCTCXO_4 25
#define MMP2_CLK_UART_PLL 26
#define MMP2_CLK_USB_PLL 27
+#define MMP3_CLK_PLL1_P 28
+#define MMP3_CLK_PLL2_P 29
+#define MMP3_CLK_PLL3 30
/* apb periphrals */
#define MMP2_CLK_TWSI0 60
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 09/10] clk: mmp2: Add PLLs that are available on MMP3
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
` (7 preceding siblings ...)
2020-02-19 7:33 ` [PATCH 08/10] dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
2020-02-19 7:33 ` [PATCH 10/10] ARM: dts: mmp3: Use the MMP3 compatible string for /clocks Lubomir Rintel
9 siblings, 0 replies; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
There are more PLLs on MMP3 and are configured slightly differently.
Tested on a MMP3-based Dell Wyse 3020 machine.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/clk-of-mmp2.c | 34 +++++++++++++++++++++++++++-------
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index 7594a8280b93a..310d77855f03f 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -57,10 +57,16 @@
#define APMU_USBHSIC0 0xf8
#define APMU_USBHSIC1 0xfc
-#define MPMU_FCCR 0x8
-#define MPMU_POSR 0x10
-#define MPMU_UART_PLL 0x14
-#define MPMU_PLL2_CR 0x34
+#define MPMU_FCCR 0x8
+#define MPMU_POSR 0x10
+#define MPMU_UART_PLL 0x14
+#define MPMU_PLL2_CR 0x34
+/* MMP3 specific below */
+#define MPMU_PLL3_CR 0x50
+#define MPMU_PLL3_CTRL1 0x58
+#define MPMU_PLL1_CTRL 0x5c
+#define MPMU_PLL_DIFF_CTRL 0x68
+#define MPMU_PLL2_CTRL1 0x414
enum mmp2_clk_model {
CLK_MODEL_MMP2,
@@ -86,6 +92,14 @@ static struct mmp_param_pll_clk pll_clks[] = {
{MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
};
+static struct mmp_param_pll_clk mmp3_pll_clks[] = {
+ {MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000, MPMU_PLL1_CTRL, 25},
+ {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL2_CTRL1, 25},
+ {MMP3_CLK_PLL1_P, "pll1_p", 0, MPMU_PLL_DIFF_CTRL, 0x0010, 0, 0, 797330000, MPMU_PLL_DIFF_CTRL, 0},
+ {MMP3_CLK_PLL2_P, "pll2_p", 0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL_DIFF_CTRL, 5},
+ {MMP3_CLK_PLL3, "pll3", 0, MPMU_PLL3_CR, 0x0300, MPMU_PLL3_CR, 10, 26000000, MPMU_PLL3_CTRL1, 25},
+};
+
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
{MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
{MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
@@ -127,9 +141,15 @@ static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
ARRAY_SIZE(fixed_rate_clks));
- mmp_register_pll_clks(unit, pll_clks,
- pxa_unit->mpmu_base,
- ARRAY_SIZE(pll_clks));
+ if (pxa_unit->model == CLK_MODEL_MMP3) {
+ mmp_register_pll_clks(unit, mmp3_pll_clks,
+ pxa_unit->mpmu_base,
+ ARRAY_SIZE(mmp3_pll_clks));
+ } else {
+ mmp_register_pll_clks(unit, pll_clks,
+ pxa_unit->mpmu_base,
+ ARRAY_SIZE(pll_clks));
+ }
mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
ARRAY_SIZE(fixed_factor_clks));
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 10/10] ARM: dts: mmp3: Use the MMP3 compatible string for /clocks
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
` (8 preceding siblings ...)
2020-02-19 7:33 ` [PATCH 09/10] clk: mmp2: Add PLLs that are available on MMP3 Lubomir Rintel
@ 2020-02-19 7:33 ` Lubomir Rintel
9 siblings, 0 replies; 14+ messages in thread
From: Lubomir Rintel @ 2020-02-19 7:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, devicetree, Michael Turquette, linux-kernel,
Lubomir Rintel, Rob Herring, linux-clk, linux-arm-kernel
Clocks are in fact slightly different on MMP3. In particular, PLL2 is
fixed to a different frequency, there's an extra PLL3, and the GPU
clocks are configured differently.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
arch/arm/boot/dts/mmp3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi
index 59a108e49b41e..3e28f0dc9df41 100644
--- a/arch/arm/boot/dts/mmp3.dtsi
+++ b/arch/arm/boot/dts/mmp3.dtsi
@@ -531,7 +531,7 @@ l2: l2-cache-controller@d0020000 {
};
soc_clocks: clocks@d4050000 {
- compatible = "marvell,mmp2-clock";
+ compatible = "marvell,mmp3-clock";
reg = <0xd4050000 0x1000>,
<0xd4282800 0x400>,
<0xd4015000 0x1000>;
--
2.24.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 03/10] dt-bindings: clock: Convert marvell,mmp2-clock to json-schema
2020-02-19 7:33 ` [PATCH 03/10] dt-bindings: clock: Convert marvell, mmp2-clock to json-schema Lubomir Rintel
@ 2020-02-26 15:28 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2020-02-26 15:28 UTC (permalink / raw)
To: Lubomir Rintel
Cc: Mark Rutland, devicetree, Stephen Boyd, Michael Turquette,
linux-kernel, Lubomir Rintel, linux-clk, linux-arm-kernel
On Wed, 19 Feb 2020 08:33:46 +0100, Lubomir Rintel wrote:
>
> Convert the fixed-factor-clock binding to DT schema format using
> json-schema.
>
> While at that, fix a couple of small errors: make the file base name
> match the compatible string, add an example and document the reg-names
> property.
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---
> .../bindings/clock/marvell,mmp2-clock.yaml | 62 +++++++++++++++++++
> .../bindings/clock/marvell,mmp2.txt | 21 -------
> 2 files changed, 62 insertions(+), 21 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml
> delete mode 100644 Documentation/devicetree/bindings/clock/marvell,mmp2.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 06/10] dt-bindings: clock: Add MMP3 compatible string
2020-02-19 7:33 ` [PATCH 06/10] dt-bindings: clock: Add MMP3 compatible string Lubomir Rintel
@ 2020-02-26 15:28 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2020-02-26 15:28 UTC (permalink / raw)
To: Lubomir Rintel
Cc: Mark Rutland, devicetree, Stephen Boyd, Michael Turquette,
linux-kernel, Lubomir Rintel, linux-clk, linux-arm-kernel
On Wed, 19 Feb 2020 08:33:49 +0100, Lubomir Rintel wrote:
>
> This binding describes the PMUs that are found on MMP3 as well. Add the
> compatible strings and adjust the description.
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---
> .../devicetree/bindings/clock/marvell,mmp2-clock.yaml | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 08/10] dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs
2020-02-19 7:33 ` [PATCH 08/10] dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs Lubomir Rintel
@ 2020-02-26 15:29 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2020-02-26 15:29 UTC (permalink / raw)
To: Lubomir Rintel
Cc: Mark Rutland, devicetree, Stephen Boyd, Michael Turquette,
linux-kernel, Lubomir Rintel, linux-clk, linux-arm-kernel
On Wed, 19 Feb 2020 08:33:51 +0100, Lubomir Rintel wrote:
>
> MMP3 variant provides some more clocks. Add respective IDs.
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---
> include/dt-bindings/clock/marvell,mmp2.h | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-02-26 15:29 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-19 7:33 [PATCH 00/10] MMP2 CLK Update Lubomir Rintel
2020-02-19 7:33 ` [PATCH 01/10] clk: mmp2: Remove a unused prototype Lubomir Rintel
2020-02-19 7:33 ` [PATCH 02/10] clk: mmp2: Constify some strings Lubomir Rintel
2020-02-19 7:33 ` [PATCH 03/10] dt-bindings: clock: Convert marvell, mmp2-clock to json-schema Lubomir Rintel
2020-02-26 15:28 ` [PATCH 03/10] dt-bindings: clock: Convert marvell,mmp2-clock " Rob Herring
2020-02-19 7:33 ` [PATCH 04/10] clk: mmp2: Add support for PLL clock sources Lubomir Rintel
2020-02-19 7:33 ` [PATCH 05/10] clk: mmp2: Stop pretending PLL outputs are constant Lubomir Rintel
2020-02-19 7:33 ` [PATCH 06/10] dt-bindings: clock: Add MMP3 compatible string Lubomir Rintel
2020-02-26 15:28 ` Rob Herring
2020-02-19 7:33 ` [PATCH 07/10] clk: mmp2: Check for MMP3 Lubomir Rintel
2020-02-19 7:33 ` [PATCH 08/10] dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs Lubomir Rintel
2020-02-26 15:29 ` Rob Herring
2020-02-19 7:33 ` [PATCH 09/10] clk: mmp2: Add PLLs that are available on MMP3 Lubomir Rintel
2020-02-19 7:33 ` [PATCH 10/10] ARM: dts: mmp3: Use the MMP3 compatible string for /clocks Lubomir Rintel
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