[PATCH] ARM: dts: stm32: Enable HS200 on AV96

[PATCH] ARM: dts: stm32: Enable HS200 on AV96

[Marek Vasut]

Enable MMC HS200 mode on AV96. This needs PLL4P to run at 100 MHz,
as the PLL is limited to 130 MHz and the 100 MHz is most suitable
for dividing the clock down both to 50 MHz for DDR52 and 100 MHz
for HS200.

The performance figures are not that different between DDR52 and
HS200 though:

    $ cat /sys/kernel/debug/mmc2/ios
    clock:          52000000 Hz
    actual clock:   50000000 Hz
    vdd:            7 (1.65 - 1.95 V)
    bus mode:       2 (push-pull)
    chip select:    0 (don't care)
    power mode:     2 (on)
    bus width:      3 (8 bits)
    timing spec:    8 (mmc DDR52)
    signal voltage: 1 (1.80 V)
    driver type:    0 (driver type B)
    $ dd if=/dev/mmcblk2 of=/dev/null bs=128M count=16 conv=sync
    16+0 records in
    16+0 records out
    2147483648 bytes (2.1 GB, 2.0 GiB) copied, 26.3924 s, 81.4 MB/s

    $ cat /sys/kernel/debug/mmc2/ios
    clock:          100000000 Hz
    actual clock:   100000000 Hz
    vdd:            7 (1.65 - 1.95 V)
    bus mode:       2 (push-pull)
    chip select:    0 (don't care)
    power mode:     2 (on)
    bus width:      3 (8 bits)
    timing spec:    9 (mmc HS200)
    signal voltage: 1 (1.80 V)
    driver type:    0 (driver type B)
    $ dd if=/dev/mmcblk2 of=/dev/null bs=128M count=16 conv=sync
    16+0 records in
    16+0 records out
    2147483648 bytes (2.1 GB, 2.0 GiB) copied, 25.2144 s, 85.2 MB/s

Note that if there is a way to run the PLL4P at 200 MHz, this HS200
support might be far more interesting.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
 arch/arm/boot/dts/stm32mp157a-avenger96.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
index 5292d746ab0b..f44511abc6ee 100644
--- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
@@ -520,6 +520,7 @@ &sdmmc2 {
 	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>;
 	bus-width = <8>;
 	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
 	no-sd;
 	no-sdio;
 	non-removable;
-- 
2.25.1


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