Re: [RFC PATCH 0/4] net: mfd: AC200 Ethernet PHY

From: Andrew Lunn <andrew@lunn.ch>
To: Jernej Skrabec <jernej.skrabec@siol.net>
Cc: devicetree@vger.kernel.org, f.fainelli@gmail.com,
	netdev@vger.kernel.org, linux@armlinux.org.uk,
	mripard@kernel.org, linux-kernel@vger.kernel.org, wens@csie.org,
	robh+dt@kernel.org, lee.jones@linaro.org, davem@davemloft.net,
	linux-arm-kernel@lists.infradead.org, hkallweit1@gmail.com
Subject: Re: [RFC PATCH 0/4] net: mfd: AC200 Ethernet PHY
Date: Thu, 16 Apr 2020 23:54:12 +0200	[thread overview]
Message-ID: <20200416215412.GD744226@lunn.ch> (raw)
In-Reply-To: <20200416185758.1388148-1-jernej.skrabec@siol.net>

On Thu, Apr 16, 2020 at 08:57:54PM +0200, Jernej Skrabec wrote:
> This is attempt to support Ethernet PHY on AC200 MFD chip. I'm sending
> this as RFC because I stumbled on a problem how to properly describe it
> in DT. Proper DT documentation will be added later, once DT issue is
> solved.
> 
> Before Ethernet PHY can be actually used, few things must happen:
> 1. 24 MHz clock must be enabled and connected to input pin of this
>    chip. In this case, PWM is set to generate 24 MHz signal with 50%
>    duty cycle.
> 2. Chip must be put out of reset through I2C
> 3. Ethernet PHY must be enabled and configured through I2C

Hi Jernej

This is going to be interesting to describe in DT.

At what point does the PHY start responding to MDIO request? In
particular, you can read the ID registers 2 and 3? You list above what
is needed to make it usable. But we are also interested in what is
required to make is probe'able on the MDIO bus. We have more
flexibility if we can first probe it, and then later make it usable.

Thanks
	Andrew

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