* [PATCH v1] arm64: tlb: don't set the ttl value in flush_tlb_page_nosync
@ 2020-07-10 9:41 Zhenyu Ye
0 siblings, 0 replies; only message in thread
From: Zhenyu Ye @ 2020-07-10 9:41 UTC (permalink / raw)
To: catalin.marinas, will
Cc: linux-arch, yezhenyu2, linux-kernel, xiexiangyou, linux-mm, arm,
linux-arm-kernel
flush_tlb_page_nosync() may be called from pmd level, so we
can not set the ttl = 3 here.
The callstack is as follows:
pmdp_set_access_flags
ptep_set_access_flags
flush_tlb_fix_spurious_fault
flush_tlb_page
flush_tlb_page_nosync
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Fixes: e735b98a5fe0 ("arm64: Add tlbi_user_level TLB invalidation helper")
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/tlbflush.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index edfec8139ef8..7528c84a94ef 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -252,9 +252,8 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
dsb(ishst);
- /* This function is only called on a small page */
- __tlbi_level(vale1is, addr, 3);
- __tlbi_user_level(vale1is, addr, 3);
+ __tlbi(vale1is, addr);
+ __tlbi_user(vale1is, addr);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
--
2.19.1
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