* [PATCH v2 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines
2020-09-07 14:52 [PATCH v2 0/6] arm64: dts: ti: Add USB support for J7200 EVM Roger Quadros
@ 2020-09-07 14:52 ` Roger Quadros
2020-09-08 8:39 ` Roger Quadros
2020-09-07 14:52 ` [PATCH v2 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux Roger Quadros
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Roger Quadros @ 2020-09-07 14:52 UTC (permalink / raw)
To: t-kristo, nm
Cc: devicetree, nsekhar, linux-kernel, kishon, robh+dt,
linux-arm-kernel, Roger Quadros
Each SERDES lane mux can select upto 4 different IPs.
There are 4 lanes in each J7200 SERDES. Define all
the possible functions in this file.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
include/dt-bindings/mux/mux-j7200-wiz.h | 29 +++++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 include/dt-bindings/mux/mux-j7200-wiz.h
diff --git a/include/dt-bindings/mux/mux-j7200-wiz.h b/include/dt-bindings/mux/mux-j7200-wiz.h
new file mode 100644
index 000000000000..b091b1185a36
--- /dev/null
+++ b/include/dt-bindings/mux/mux-j7200-wiz.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for J7200 WIZ.
+ */
+
+#ifndef _DT_BINDINGS_J7200_WIZ
+#define _DT_BINDINGS_J7200_WIZ
+
+#define SERDES0_LANE0_QSGMII_LANE3 0x0
+#define SERDES0_LANE0_PCIE1_LANE0 0x1
+#define SERDES0_LANE0_IP3_UNUSED 0x2
+#define SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define SERDES0_LANE1_QSGMII_LANE4 0x0
+#define SERDES0_LANE1_PCIE1_LANE1 0x1
+#define SERDES0_LANE1_IP3_UNUSED 0x2
+#define SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define SERDES0_LANE2_QSGMII_LANE1 0x0
+#define SERDES0_LANE2_PCIE1_LANE2 0x1
+#define SERDES0_LANE2_IP3_UNUSED 0x2
+#define SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define SERDES0_LANE3_QSGMII_LANE2 0x0
+#define SERDES0_LANE3_PCIE1_LANE3 0x1
+#define SERDES0_LANE3_USB 0x2
+#define SERDES0_LANE3_IP4_UNUSED 0x3
+
+#endif /* _DT_BINDINGS_J7200_WIZ */
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines
2020-09-07 14:52 ` [PATCH v2 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines Roger Quadros
@ 2020-09-08 8:39 ` Roger Quadros
0 siblings, 0 replies; 10+ messages in thread
From: Roger Quadros @ 2020-09-08 8:39 UTC (permalink / raw)
To: t-kristo, nm, peda
Cc: devicetree, nsekhar, linux-kernel, kishon, robh+dt, linux-arm-kernel
+Peter
On 07/09/2020 17:52, Roger Quadros wrote:
> Each SERDES lane mux can select upto 4 different IPs.
> There are 4 lanes in each J7200 SERDES. Define all
> the possible functions in this file.
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> include/dt-bindings/mux/mux-j7200-wiz.h | 29 +++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 include/dt-bindings/mux/mux-j7200-wiz.h
>
> diff --git a/include/dt-bindings/mux/mux-j7200-wiz.h b/include/dt-bindings/mux/mux-j7200-wiz.h
> new file mode 100644
> index 000000000000..b091b1185a36
> --- /dev/null
> +++ b/include/dt-bindings/mux/mux-j7200-wiz.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for J7200 WIZ.
> + */
> +
> +#ifndef _DT_BINDINGS_J7200_WIZ
> +#define _DT_BINDINGS_J7200_WIZ
> +
> +#define SERDES0_LANE0_QSGMII_LANE3 0x0
> +#define SERDES0_LANE0_PCIE1_LANE0 0x1
> +#define SERDES0_LANE0_IP3_UNUSED 0x2
> +#define SERDES0_LANE0_IP4_UNUSED 0x3
> +
> +#define SERDES0_LANE1_QSGMII_LANE4 0x0
> +#define SERDES0_LANE1_PCIE1_LANE1 0x1
> +#define SERDES0_LANE1_IP3_UNUSED 0x2
> +#define SERDES0_LANE1_IP4_UNUSED 0x3
> +
> +#define SERDES0_LANE2_QSGMII_LANE1 0x0
> +#define SERDES0_LANE2_PCIE1_LANE2 0x1
> +#define SERDES0_LANE2_IP3_UNUSED 0x2
> +#define SERDES0_LANE2_IP4_UNUSED 0x3
> +
> +#define SERDES0_LANE3_QSGMII_LANE2 0x0
> +#define SERDES0_LANE3_PCIE1_LANE3 0x1
> +#define SERDES0_LANE3_USB 0x2
> +#define SERDES0_LANE3_IP4_UNUSED 0x3
> +
> +#endif /* _DT_BINDINGS_J7200_WIZ */
>
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
2020-09-07 14:52 [PATCH v2 0/6] arm64: dts: ti: Add USB support for J7200 EVM Roger Quadros
2020-09-07 14:52 ` [PATCH v2 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines Roger Quadros
@ 2020-09-07 14:52 ` Roger Quadros
2020-09-08 12:30 ` Nishanth Menon
2020-09-07 14:52 ` [PATCH v2 3/6] arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX Roger Quadros
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Roger Quadros @ 2020-09-07 14:52 UTC (permalink / raw)
To: t-kristo, nm
Cc: devicetree, nsekhar, linux-kernel, kishon, robh+dt,
linux-arm-kernel, Roger Quadros
The SERDES lane control mux registers are present in the
CTRLMMR space.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 1702ac0bbf40..e72c7a0ccad5 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -18,6 +18,21 @@
};
};
+ scm_conf: scm-conf@100000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0 0x00100000 0 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
2020-09-07 14:52 ` [PATCH v2 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux Roger Quadros
@ 2020-09-08 12:30 ` Nishanth Menon
0 siblings, 0 replies; 10+ messages in thread
From: Nishanth Menon @ 2020-09-08 12:30 UTC (permalink / raw)
To: Roger Quadros
Cc: devicetree, nsekhar, linux-kernel, kishon, t-kristo, robh+dt,
linux-arm-kernel
On 17:52-20200907, Roger Quadros wrote:
> The SERDES lane control mux registers are present in the
> CTRLMMR space.
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 1702ac0bbf40..e72c7a0ccad5 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -18,6 +18,21 @@
> };
> };
>
> + scm_conf: scm-conf@100000 {
> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
> + reg = <0 0x00100000 0 0x1c000>;
Just to stay consistent with j7200 stuff we are trying to keep clean:
reg = <0x00 0x00100000 0x00 0x1c000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x00100000 0x1c000>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
> +
> + serdes_ln_ctrl: serdes-ln-ctrl@4080 {
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
> + <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
> + };
> + };
> +
> gic500: interrupt-controller@1800000 {
> compatible = "arm,gic-v3";
> #address-cells = <2>;
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/6] arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
2020-09-07 14:52 [PATCH v2 0/6] arm64: dts: ti: Add USB support for J7200 EVM Roger Quadros
2020-09-07 14:52 ` [PATCH v2 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines Roger Quadros
2020-09-07 14:52 ` [PATCH v2 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux Roger Quadros
@ 2020-09-07 14:52 ` Roger Quadros
2020-09-07 14:52 ` [PATCH v2 4/6] arm64: dts: ti: k3-j7200-main: Add USB controller Roger Quadros
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Roger Quadros @ 2020-09-07 14:52 UTC (permalink / raw)
To: t-kristo, nm
Cc: devicetree, nsekhar, linux-kernel, kishon, robh+dt,
linux-arm-kernel, Roger Quadros
The USB controller can be connected to one of the 2 lanes
of SERDES0 using a MUX. Add a MUX controller node for that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index e72c7a0ccad5..af9e8e46b49e 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -31,6 +31,12 @@
mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
};
+
+ usb_serdes_mux: mux-controller@4000 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ };
};
gic500: interrupt-controller@1800000 {
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 4/6] arm64: dts: ti: k3-j7200-main: Add USB controller
2020-09-07 14:52 [PATCH v2 0/6] arm64: dts: ti: Add USB support for J7200 EVM Roger Quadros
` (2 preceding siblings ...)
2020-09-07 14:52 ` [PATCH v2 3/6] arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX Roger Quadros
@ 2020-09-07 14:52 ` Roger Quadros
2020-09-07 14:52 ` [PATCH v2 5/6] arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function Roger Quadros
2020-09-07 14:52 ` [PATCH v2 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Add USB support Roger Quadros
5 siblings, 0 replies; 10+ messages in thread
From: Roger Quadros @ 2020-09-07 14:52 UTC (permalink / raw)
To: t-kristo, nm
Cc: devicetree, nsekhar, linux-kernel, kishon, robh+dt,
linux-arm-kernel, Roger Quadros
j7200 has on USB controller instance. Add that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 30 +++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index af9e8e46b49e..c64bf652f0d2 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -331,4 +331,34 @@
no-1-8-v;
dma-coherent;
};
+
+ usbss0: cdns-usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x4104000 0x00 0x100>;
+ dma-coherent;
+ power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x6000000 0x00 0x10000>,
+ <0x00 0x6010000 0x00 0x10000>,
+ <0x00 0x6020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
};
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 5/6] arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
2020-09-07 14:52 [PATCH v2 0/6] arm64: dts: ti: Add USB support for J7200 EVM Roger Quadros
` (3 preceding siblings ...)
2020-09-07 14:52 ` [PATCH v2 4/6] arm64: dts: ti: k3-j7200-main: Add USB controller Roger Quadros
@ 2020-09-07 14:52 ` Roger Quadros
2020-09-07 14:52 ` [PATCH v2 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Add USB support Roger Quadros
5 siblings, 0 replies; 10+ messages in thread
From: Roger Quadros @ 2020-09-07 14:52 UTC (permalink / raw)
To: t-kristo, nm
Cc: devicetree, nsekhar, linux-kernel, kishon, robh+dt,
linux-arm-kernel, Roger Quadros
From: Kishon Vijay Abraham I <kishon@ti.com>
First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 8e534ef8a3f5..0ecaba600704 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "k3-j7200-som-p0.dtsi"
+#include <dt-bindings/mux/mux-j7200-wiz.h>
/ {
chosen {
@@ -139,3 +140,8 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
+
+&serdes_ln_ctrl {
+ idle-states = <SERDES0_LANE0_PCIE1_LANE0>, <SERDES0_LANE1_PCIE1_LANE1>,
+ <SERDES0_LANE2_QSGMII_LANE1>, <SERDES0_LANE3_IP4_UNUSED>;
+};
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
2020-09-07 14:52 [PATCH v2 0/6] arm64: dts: ti: Add USB support for J7200 EVM Roger Quadros
` (4 preceding siblings ...)
2020-09-07 14:52 ` [PATCH v2 5/6] arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function Roger Quadros
@ 2020-09-07 14:52 ` Roger Quadros
2020-09-08 12:36 ` Nishanth Menon
5 siblings, 1 reply; 10+ messages in thread
From: Roger Quadros @ 2020-09-07 14:52 UTC (permalink / raw)
To: t-kristo, nm
Cc: devicetree, nsekhar, linux-kernel, kishon, robh+dt,
linux-arm-kernel, Roger Quadros
Enable USB0 port in high-speed (2.0) mode.
The board uses lane 3 of SERDES for USB. Set the mux
accordingly.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
.../dts/ti/k3-j7200-common-proc-board.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 0ecaba600704..5ce3fddbd617 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -42,6 +42,12 @@
J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
+ >;
+ };
};
&wkup_uart0 {
@@ -145,3 +151,19 @@
idle-states = <SERDES0_LANE0_PCIE1_LANE0>, <SERDES0_LANE1_PCIE1_LANE1>,
<SERDES0_LANE2_QSGMII_LANE1>, <SERDES0_LANE3_IP4_UNUSED>;
};
+
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
2020-09-07 14:52 ` [PATCH v2 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Add USB support Roger Quadros
@ 2020-09-08 12:36 ` Nishanth Menon
0 siblings, 0 replies; 10+ messages in thread
From: Nishanth Menon @ 2020-09-08 12:36 UTC (permalink / raw)
To: Roger Quadros
Cc: devicetree, nsekhar, linux-kernel, kishon, t-kristo, robh+dt,
linux-arm-kernel
On 17:52-20200907, Roger Quadros wrote:
> Enable USB0 port in high-speed (2.0) mode.
Am I right that this is a choice forced by serdes mux configuration
selection? Might be good to document it (default speed is super-speed).
>
> The board uses lane 3 of SERDES for USB. Set the mux
> accordingly.
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> .../dts/ti/k3-j7200-common-proc-board.dts | 22 +++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 0ecaba600704..5ce3fddbd617 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -42,6 +42,12 @@
> J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
> >;
> };
> +
> + main_usbss0_pins_default: main-usbss0-pins-default {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
> + >;
> + };
> };
>
> &wkup_uart0 {
> @@ -145,3 +151,19 @@
> idle-states = <SERDES0_LANE0_PCIE1_LANE0>, <SERDES0_LANE1_PCIE1_LANE1>,
> <SERDES0_LANE2_QSGMII_LANE1>, <SERDES0_LANE3_IP4_UNUSED>;
> };
> +
> +&usb_serdes_mux {
> + idle-states = <1>; /* USB0 to SERDES lane 3 */
> +};
> +
> +&usbss0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_usbss0_pins_default>;
> + ti,vbus-divider;
> + ti,usb2-only;
> +};
> +
> +&usb0 {
> + dr_mode = "otg";
> + maximum-speed = "high-speed";
> +};
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread