* [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion
@ 2020-09-17 0:41 Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 01/11] ARM: imx27: Retrieve the SYSCTRL base address from devicetree Fabio Estevam
` (12 more replies)
0 siblings, 13 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
Now that i.MX has been converted to a devicetree-only platform, do
one more round of cleanups that consists mainly in using devicetree
to get the peripherals base addresses and get rid of unused clock driver
code.
Changes since v1:
- Do not introduce a sysctrl node to avoid breaking DT compatibility (Arnd)
- Remove unused definitions for base address, IRQ and DMA (Arnd)
Fabio Estevam (11):
ARM: imx27: Retrieve the SYSCTRL base address from devicetree
ARM: imx27: Retrieve the CCM base address from devicetree
ARM: imx31: Retrieve the IIM base address from devicetree
ARM: imx3: Retrieve the CCM base address from devicetree
ARM: imx3: Retrieve the AVIC base address from devicetree
ARM: imx35: Retrieve the IIM base address from devicetree
ARM: imx: Remove unused definitions
clk: imx: imx27: Remove mx27_clocks_init()
clk: imx: imx31: Remove mx31_clocks_init()
clk: imx: imx35: Remove mx35_clocks_init()
clk: imx: imx21: Remove clock driver
arch/arm/mach-imx/cpu-imx27.c | 10 +-
arch/arm/mach-imx/cpu-imx31.c | 9 +-
arch/arm/mach-imx/cpu-imx35.c | 9 +-
arch/arm/mach-imx/mm-imx3.c | 31 +++++-
arch/arm/mach-imx/mx27.h | 196 ----------------------------------
arch/arm/mach-imx/mx31.h | 179 -------------------------------
arch/arm/mach-imx/mx35.h | 173 ------------------------------
arch/arm/mach-imx/pm-imx27.c | 12 ++-
drivers/clk/imx/Kconfig | 4 -
drivers/clk/imx/Makefile | 1 -
drivers/clk/imx/clk-imx21.c | 171 -----------------------------
drivers/clk/imx/clk-imx27.c | 73 -------------
drivers/clk/imx/clk-imx31.c | 71 ------------
drivers/clk/imx/clk-imx35.c | 68 ------------
14 files changed, 62 insertions(+), 945 deletions(-)
delete mode 100644 drivers/clk/imx/clk-imx21.c
--
2.17.1
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 01/11] ARM: imx27: Retrieve the SYSCTRL base address from devicetree
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 02/11] ARM: imx27: Retrieve the CCM " Fabio Estevam
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
Now that imx27 has been converted to a devicetree-only platform,
retrieve the SYSCTRL base address from devicetree.
To keep devicetree compatibilty the SYSCTRL base address will be
retrieved from the CCM base address plus an 0x800 offset.
This is not a problem as the imx27.dtsi describes the CCM register
range as 0x1000.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- Do not introduce a sysctrl node to avoid breaking DT compatibility (Arnd)
arch/arm/mach-imx/cpu-imx27.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index a969aa71b60f..bf70e13bbe9e 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -9,6 +9,7 @@
*/
#include <linux/io.h>
+#include <linux/of_address.h>
#include <linux/module.h>
#include "hardware.h"
@@ -17,16 +18,23 @@ static int mx27_cpu_rev = -1;
static int mx27_cpu_partnumber;
#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
+#define SYSCTRL_OFFSET 0x800 /* Offset from CCM base address */
static int mx27_read_cpu_rev(void)
{
+ void __iomem *ccm_base;
+ struct device_node *np;
u32 val;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
+ ccm_base = of_iomap(np, 0);
+ BUG_ON(!ccm_base);
/*
* now we have access to the IO registers. As we need
* the silicon revision very early we read it here to
* avoid any further hooks
*/
- val = imx_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID));
+ val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID);
mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 02/11] ARM: imx27: Retrieve the CCM base address from devicetree
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 01/11] ARM: imx27: Retrieve the SYSCTRL base address from devicetree Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 03/11] ARM: imx31: Retrieve the IIM " Fabio Estevam
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
Now that imx27 has been converted to a devicetree-only platform,
retrieve the CCM base address from devicetree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
arch/arm/mach-imx/pm-imx27.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index d943535566c8..020e6deb67c8 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -7,6 +7,7 @@
* modify it under the terms of the GNU General Public License.
*/
+#include <linux/of_address.h>
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/io.h>
@@ -15,13 +16,20 @@
static int mx27_suspend_enter(suspend_state_t state)
{
+ void __iomem *ccm_base;
+ struct device_node *np;
u32 cscr;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
+ ccm_base = of_iomap(np, 0);
+ BUG_ON(!ccm_base);
+
switch (state) {
case PM_SUSPEND_MEM:
/* Clear MPEN and SPEN to disable MPLL/SPLL */
- cscr = imx_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+ cscr = imx_readl(ccm_base);
cscr &= 0xFFFFFFFC;
- imx_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+ imx_writel(cscr, ccm_base);
/* Executes WFI */
cpu_do_idle();
break;
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 03/11] ARM: imx31: Retrieve the IIM base address from devicetree
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 01/11] ARM: imx27: Retrieve the SYSCTRL base address from devicetree Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 02/11] ARM: imx27: Retrieve the CCM " Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 04/11] ARM: imx3: Retrieve the CCM " Fabio Estevam
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
Now that imx31 has been converted to a devicetree-only platform,
retrieve the IIM base address from devicetree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
arch/arm/mach-imx/cpu-imx31.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index 3ee684b71006..b9c24b851d1a 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -6,6 +6,7 @@
*/
#include <linux/module.h>
+#include <linux/of_address.h>
#include <linux/io.h>
#include "common.h"
@@ -32,10 +33,16 @@ static struct {
static int mx31_read_cpu_rev(void)
{
+ void __iomem *iim_base;
+ struct device_node *np;
u32 i, srev;
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
+ iim_base = of_iomap(np, 0);
+ BUG_ON(!iim_base);
+
/* read SREV register from IIM module */
- srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
+ srev = imx_readl(iim_base + MXC_IIMSREV);
srev &= 0xff;
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 04/11] ARM: imx3: Retrieve the CCM base address from devicetree
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (2 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 03/11] ARM: imx31: Retrieve the IIM " Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 05/11] ARM: imx3: Retrieve the AVIC " Fabio Estevam
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
Now that imx31 and imx35 has been converted to a devicetree-only platform,
retrieve the CCM base address from devicetree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
arch/arm/mach-imx/mm-imx3.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 4df7edc7ae7c..b7c5e15bb972 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>
#include <asm/system_misc.h>
@@ -99,10 +100,14 @@ static void imx31_idle(void)
void __init imx31_init_early(void)
{
+ struct device_node *np;
+
mxc_set_cpu_type(MXC_CPU_MX31);
arch_ioremap_caller = imx3_ioremap_caller;
arm_pm_idle = imx31_idle;
- mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
+ mx3_ccm_base = of_iomap(np, 0);
+ BUG_ON(!mx3_ccm_base);
}
void __init mx31_init_irq(void)
@@ -137,10 +142,14 @@ static void imx35_idle(void)
void __init imx35_init_early(void)
{
+ struct device_node *np;
+
mxc_set_cpu_type(MXC_CPU_MX35);
arm_pm_idle = imx35_idle;
arch_ioremap_caller = imx3_ioremap_caller;
- mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm");
+ mx3_ccm_base = of_iomap(np, 0);
+ BUG_ON(!mx3_ccm_base);
}
void __init mx35_init_irq(void)
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 05/11] ARM: imx3: Retrieve the AVIC base address from devicetree
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (3 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 04/11] ARM: imx3: Retrieve the CCM " Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 06/11] ARM: imx35: Retrieve the IIM " Fabio Estevam
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
Now that imx31 and imx35 has been converted to a devicetree-only platform,
retrieve the AVIC base address from devicetree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
arch/arm/mach-imx/mm-imx3.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index b7c5e15bb972..5056438e5b42 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -112,7 +112,14 @@ void __init imx31_init_early(void)
void __init mx31_init_irq(void)
{
- mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
+ void __iomem *avic_base;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx31-avic");
+ avic_base = of_iomap(np, 0);
+ BUG_ON(!avic_base);
+
+ mxc_init_irq(avic_base);
}
#endif /* ifdef CONFIG_SOC_IMX31 */
@@ -154,6 +161,13 @@ void __init imx35_init_early(void)
void __init mx35_init_irq(void)
{
- mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
+ void __iomem *avic_base;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx35-avic");
+ avic_base = of_iomap(np, 0);
+ BUG_ON(!avic_base);
+
+ mxc_init_irq(avic_base);
}
#endif /* ifdef CONFIG_SOC_IMX35 */
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 06/11] ARM: imx35: Retrieve the IIM base address from devicetree
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (4 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 05/11] ARM: imx3: Retrieve the AVIC " Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 07/11] ARM: imx: Remove unused definitions Fabio Estevam
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
Now that imx35 has been converted to a devicetree-only platform,
retrieve the IIM base address from devicetree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
arch/arm/mach-imx/cpu-imx35.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
index ebb3cdabd506..80e7d8ab9f1b 100644
--- a/arch/arm/mach-imx/cpu-imx35.c
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -5,6 +5,7 @@
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*/
#include <linux/module.h>
+#include <linux/of_address.h>
#include <linux/io.h>
#include "hardware.h"
@@ -14,9 +15,15 @@ static int mx35_cpu_rev = -1;
static int mx35_read_cpu_rev(void)
{
+ void __iomem *iim_base;
+ struct device_node *np;
u32 rev;
- rev = imx_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim");
+ iim_base = of_iomap(np, 0);
+ BUG_ON(!iim_base);
+
+ rev = imx_readl(iim_base + MXC_IIMSREV);
switch (rev) {
case 0x00:
return IMX_CHIP_REVISION_1_0;
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 07/11] ARM: imx: Remove unused definitions
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (5 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 06/11] ARM: imx35: Retrieve the IIM " Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 08/11] clk: imx: imx27: Remove mx27_clocks_init() Fabio Estevam
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
Most of the definitions for peripheral base addresses, interrupt and
DMA information is no longer used, so get rid of them.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- Remove unused definitions for base address, IRQ and DMA (Arnd)
arch/arm/mach-imx/mx27.h | 196 ---------------------------------------
arch/arm/mach-imx/mx31.h | 179 -----------------------------------
arch/arm/mach-imx/mx35.h | 173 ----------------------------------
3 files changed, 548 deletions(-)
diff --git a/arch/arm/mach-imx/mx27.h b/arch/arm/mach-imx/mx27.h
index c6f7aae02b67..241c04d706fe 100644
--- a/arch/arm/mach-imx/mx27.h
+++ b/arch/arm/mach-imx/mx27.h
@@ -13,209 +13,13 @@
#define MX27_AIPI_BASE_ADDR 0x10000000
#define MX27_AIPI_SIZE SZ_1M
-#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
-#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
-#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
-#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
-#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
-#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
-#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
-#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
-#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
-#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
-#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
-#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
-#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
-#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
-#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
-#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
-#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
-#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
-#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
-#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
-#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
-#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
-#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
-#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
-#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
-#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
-#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
-#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
-#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
-#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
-#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
-#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
-#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
-#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
-#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
-#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
-#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
-#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
-#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
-#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
-#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
-#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
-#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
-#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
-#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
-#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
-#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
-#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
-#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
-#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
-#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
-#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
-#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
-#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
-#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
-#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX27_AVIC_BASE_ADDR 0x10040000
-
-/* ROM patch */
-#define MX27_ROMP_BASE_ADDR 0x10041000
#define MX27_SAHB1_BASE_ADDR 0x80000000
#define MX27_SAHB1_SIZE SZ_1M
-#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
-#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
-
-/* Memory regions and CS */
-#define MX27_SDRAM_BASE_ADDR 0xa0000000
-#define MX27_CSD1_BASE_ADDR 0xb0000000
-#define MX27_CS0_BASE_ADDR 0xc0000000
-#define MX27_CS1_BASE_ADDR 0xc8000000
-#define MX27_CS2_BASE_ADDR 0xd0000000
-#define MX27_CS3_BASE_ADDR 0xd2000000
-#define MX27_CS4_BASE_ADDR 0xd4000000
-#define MX27_CS5_BASE_ADDR 0xd6000000
-
-/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
#define MX27_X_MEMC_BASE_ADDR 0xd8000000
#define MX27_X_MEMC_SIZE SZ_1M
-#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
-#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
-#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
-#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
-#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
-
-#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
-
-/* IRAM */
-#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
#define MX27_IO_P2V(x) IMX_IO_P2V(x)
-#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
-#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
-#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
-#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
-#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
-#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
-#define MX27_INT_MSHC (NR_IRQS_LEGACY + 7)
-#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
-#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
-#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
-#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
-#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
-#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
-#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
-#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
-#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
-#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
-#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
-#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
-#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
-#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
-#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
-#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
-#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
-#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
-#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
-#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
-#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
-#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
-#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
-#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
-#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
-#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
-#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
-#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
-#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
-#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
-#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
-#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
-#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
-#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
-#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
-#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
-#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
-#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
-#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
-#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
-#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
-#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
-#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
-#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
-#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
-#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
-#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
-#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
-#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
-#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
-#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
-#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
-#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
-#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
-#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
-
-/* fixed DMA request numbers */
-#define MX27_DMA_REQ_CSPI3_RX 1
-#define MX27_DMA_REQ_CSPI3_TX 2
-#define MX27_DMA_REQ_EXT 3
-#define MX27_DMA_REQ_MSHC 4
-#define MX27_DMA_REQ_SDHC2 6
-#define MX27_DMA_REQ_SDHC1 7
-#define MX27_DMA_REQ_SSI2_RX0 8
-#define MX27_DMA_REQ_SSI2_TX0 9
-#define MX27_DMA_REQ_SSI2_RX1 10
-#define MX27_DMA_REQ_SSI2_TX1 11
-#define MX27_DMA_REQ_SSI1_RX0 12
-#define MX27_DMA_REQ_SSI1_TX0 13
-#define MX27_DMA_REQ_SSI1_RX1 14
-#define MX27_DMA_REQ_SSI1_TX1 15
-#define MX27_DMA_REQ_CSPI2_RX 16
-#define MX27_DMA_REQ_CSPI2_TX 17
-#define MX27_DMA_REQ_CSPI1_RX 18
-#define MX27_DMA_REQ_CSPI1_TX 19
-#define MX27_DMA_REQ_UART4_RX 20
-#define MX27_DMA_REQ_UART4_TX 21
-#define MX27_DMA_REQ_UART3_RX 22
-#define MX27_DMA_REQ_UART3_TX 23
-#define MX27_DMA_REQ_UART2_RX 24
-#define MX27_DMA_REQ_UART2_TX 25
-#define MX27_DMA_REQ_UART1_RX 26
-#define MX27_DMA_REQ_UART1_TX 27
-#define MX27_DMA_REQ_ATA_TX 28
-#define MX27_DMA_REQ_ATA_RCV 29
-#define MX27_DMA_REQ_CSI_STAT 30
-#define MX27_DMA_REQ_CSI_RX 31
-#define MX27_DMA_REQ_UART5_TX 32
-#define MX27_DMA_REQ_UART5_RX 33
-#define MX27_DMA_REQ_UART6_TX 34
-#define MX27_DMA_REQ_UART6_RX 35
-#define MX27_DMA_REQ_SDHC3 36
-#define MX27_DMA_REQ_NFC 37
#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/mach-imx/mx31.h b/arch/arm/mach-imx/mx31.h
index d9574671ca5c..08a72e25c289 100644
--- a/arch/arm/mach-imx/mx31.h
+++ b/arch/arm/mach-imx/mx31.h
@@ -2,196 +2,17 @@
#ifndef __MACH_MX31_H__
#define __MACH_MX31_H__
-/*
- * IRAM
- */
-#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
-#define MX31_IRAM_SIZE SZ_16K
-
-#define MX31_L2CC_BASE_ADDR 0x30000000
-#define MX31_L2CC_SIZE SZ_1M
-
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define MX31_AIPS1_SIZE SZ_1M
-#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
-#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
-#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
-#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
-#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
-#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
-#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
-#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
-#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
-#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
-#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
-#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
-#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
-#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
-#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
-#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
-#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
-#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
-#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
-#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
-#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
-#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
-#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
-#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
-
#define MX31_SPBA0_BASE_ADDR 0x50000000
#define MX31_SPBA0_SIZE SZ_1M
-#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
-#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
-#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
-#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
-#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
-#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
-#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
-#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
-#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
-
#define MX31_AIPS2_BASE_ADDR 0x53f00000
#define MX31_AIPS2_SIZE SZ_1M
-#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
-#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
-#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
-#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
-#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
-#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
-#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
-#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
-#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
-#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
-#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
-#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
-#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
-#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
-#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
-#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
-#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
-#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
-#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
-#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
-#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
-
-#define MX31_ROMP_BASE_ADDR 0x60000000
-#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
-#define MX31_ROMP_SIZE SZ_1M
-
#define MX31_AVIC_BASE_ADDR 0x68000000
#define MX31_AVIC_SIZE SZ_1M
-
-#define MX31_IPU_MEM_BASE_ADDR 0x70000000
-#define MX31_CSD0_BASE_ADDR 0x80000000
-#define MX31_CSD1_BASE_ADDR 0x90000000
-
-#define MX31_CS0_BASE_ADDR 0xa0000000
-#define MX31_CS1_BASE_ADDR 0xa8000000
-#define MX31_CS2_BASE_ADDR 0xb0000000
-#define MX31_CS3_BASE_ADDR 0xb2000000
-
-#define MX31_CS4_BASE_ADDR 0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
-#define MX31_CS4_SIZE SZ_32M
-
-#define MX31_CS5_BASE_ADDR 0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
-#define MX31_CS5_SIZE SZ_32M
-
#define MX31_X_MEMC_BASE_ADDR 0xb8000000
#define MX31_X_MEMC_SIZE SZ_64K
-#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
-#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
-#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
-#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
-#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
-#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
-
-#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX31_IO_P2V(x) IMX_IO_P2V(x)
-#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
-#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
-#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
-#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
-#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
-#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
-#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
-#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
-#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
-#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
-#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
-#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
-#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
-#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
-#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
-#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
-#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
-#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
-#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
-#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
-#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
-#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
-#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
-#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
-#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
-#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
-#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
-#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
-#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
-#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
-#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
-#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
-#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
-#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
-#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
-#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
-#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
-#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
-#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
-#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
-#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
-#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
-#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
-#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
-#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
-#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
-#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
-#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
-#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
-#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
-#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
-#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
-#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
-#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
-#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
-
-#define MX31_DMA_REQ_SDHC1 20
-#define MX31_DMA_REQ_SDHC2 21
-#define MX31_DMA_REQ_SSI2_RX1 22
-#define MX31_DMA_REQ_SSI2_TX1 23
-#define MX31_DMA_REQ_SSI2_RX0 24
-#define MX31_DMA_REQ_SSI2_TX0 25
-#define MX31_DMA_REQ_SSI1_RX1 26
-#define MX31_DMA_REQ_SSI1_TX1 27
-#define MX31_DMA_REQ_SSI1_RX0 28
-#define MX31_DMA_REQ_SSI1_TX0 29
-
-#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/mach-imx/mx35.h b/arch/arm/mach-imx/mx35.h
index 760de6a0af7e..5a8a87a85c14 100644
--- a/arch/arm/mach-imx/mx35.h
+++ b/arch/arm/mach-imx/mx35.h
@@ -2,190 +2,17 @@
#ifndef __MACH_MX35_H__
#define __MACH_MX35_H__
-/*
- * IRAM
- */
-#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
-#define MX35_IRAM_SIZE SZ_128K
-
-#define MX35_L2CC_BASE_ADDR 0x30000000
-#define MX35_L2CC_SIZE SZ_1M
-
#define MX35_AIPS1_BASE_ADDR 0x43f00000
#define MX35_AIPS1_SIZE SZ_1M
-#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
-#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
-#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
-#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
-#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
-#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
-#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
-#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
-#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
-#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
-#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
-#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
-#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
-#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
-#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
-#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
-#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
-
#define MX35_SPBA0_BASE_ADDR 0x50000000
#define MX35_SPBA0_SIZE SZ_1M
-#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
-#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
-#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
-#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
-#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
-#define MX35_FEC_BASE_ADDR 0x50038000
-#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
-
#define MX35_AIPS2_BASE_ADDR 0x53f00000
#define MX35_AIPS2_SIZE SZ_1M
-#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
-#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
-#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
-#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
-#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
-#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
-#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
-#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
-#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
-#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
-#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
-#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
-#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
-#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
-#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
-#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
-#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
-#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
-#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
-#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
-#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
-#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
-#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
-#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
-/*
- * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
- * HS. When host support was implemented only a preliminary document was
- * available, which told 0x400. This works fine.
- */
-#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
-
-#define MX35_ROMP_BASE_ADDR 0x60000000
-#define MX35_ROMP_SIZE SZ_1M
-
#define MX35_AVIC_BASE_ADDR 0x68000000
#define MX35_AVIC_SIZE SZ_1M
-
-/*
- * Memory regions and CS
- */
-#define MX35_IPU_MEM_BASE_ADDR 0x70000000
-#define MX35_CSD0_BASE_ADDR 0x80000000
-#define MX35_CSD1_BASE_ADDR 0x90000000
-
-#define MX35_CS0_BASE_ADDR 0xa0000000
-#define MX35_CS1_BASE_ADDR 0xa8000000
-#define MX35_CS2_BASE_ADDR 0xb0000000
-#define MX35_CS3_BASE_ADDR 0xb2000000
-
-#define MX35_CS4_BASE_ADDR 0xb4000000
-#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
-#define MX35_CS4_SIZE SZ_32M
-
-#define MX35_CS5_BASE_ADDR 0xb6000000
-#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
-#define MX35_CS5_SIZE SZ_32M
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
#define MX35_X_MEMC_BASE_ADDR 0xb8000000
#define MX35_X_MEMC_SIZE SZ_64K
-#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
-#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
-#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
-#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
-#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
-
-#define MX35_NFC_BASE_ADDR 0xbb000000
-#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX35_IO_P2V(x) IMX_IO_P2V(x)
-#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
-#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
-#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
-#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
-#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
-#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
-#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
-#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
-#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
-#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
-#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
-#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
-#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
-#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
-#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
-#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
-#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
-#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
-#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
-#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
-#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
-#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
-#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
-#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
-#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
-#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
-#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
-#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
-#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
-#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
-#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
-#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
-#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
-#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
-#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
-#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
-#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
-#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
-#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
-#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
-#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
-#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
-#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
-#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
-#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
-#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
-#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
-#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
-#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
-#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
-#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
-#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
-
-#define MX35_DMA_REQ_SSI2_RX1 22
-#define MX35_DMA_REQ_SSI2_TX1 23
-#define MX35_DMA_REQ_SSI2_RX0 24
-#define MX35_DMA_REQ_SSI2_TX0 25
-#define MX35_DMA_REQ_SSI1_RX1 26
-#define MX35_DMA_REQ_SSI1_TX1 27
-#define MX35_DMA_REQ_SSI1_RX0 28
-#define MX35_DMA_REQ_SSI1_TX0 29
-
-#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
#endif /* ifndef __MACH_MX35_H__ */
--
2.17.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 08/11] clk: imx: imx27: Remove mx27_clocks_init()
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (6 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 07/11] ARM: imx: Remove unused definitions Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 09/11] clk: imx: imx31: Remove mx31_clocks_init() Fabio Estevam
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
mx27_clocks_init() has been used to register clocks on i.MX27
non-devicetree platforms.
Now that i.MX is a devicetree-only platform, it is safe to
remove mx27_clocks_init() as there are no more users.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
drivers/clk/imx/clk-imx27.c | 73 -------------------------------------
1 file changed, 73 deletions(-)
diff --git a/drivers/clk/imx/clk-imx27.c b/drivers/clk/imx/clk-imx27.c
index a3753067fc12..5585ded8b8c6 100644
--- a/drivers/clk/imx/clk-imx27.c
+++ b/drivers/clk/imx/clk-imx27.c
@@ -181,79 +181,6 @@ static void __init _mx27_clocks_init(unsigned long fref)
imx_print_silicon_rev("i.MX27", mx27_revision());
}
-int __init mx27_clocks_init(unsigned long fref)
-{
- ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
-
- _mx27_clocks_init(fref);
-
- clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
- clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");
- clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
- clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");
- clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
- clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");
- clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
- clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");
- clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
- clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");
- clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");
- clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");
- clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
- clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");
- clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");
- clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");
- clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");
- clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");
- clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");
- clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");
- clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");
- clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");
- clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");
- clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");
- clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");
- clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");
- clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");
- clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
- clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");
- clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");
- clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");
- clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");
- clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");
- clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");
- clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");
- clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");
- clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");
- clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");
- clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");
- clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");
- clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");
- clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");
- clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");
- clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
- clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
- clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");
- clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");
- clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");
- clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");
- clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");
- clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");
- clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");
- clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");
- clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");
- clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");
- clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0");
- clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");
- clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");
- clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");
- clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
- clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
-
- mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1, GPT_TYPE_IMX21);
-
- return 0;
-}
-
static void __init mx27_clocks_init_dt(struct device_node *np)
{
struct device_node *refnp;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 09/11] clk: imx: imx31: Remove mx31_clocks_init()
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (7 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 08/11] clk: imx: imx27: Remove mx27_clocks_init() Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 10/11] clk: imx: imx35: Remove mx35_clocks_init() Fabio Estevam
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
mx31_clocks_init() has been used to register clocks on i.MX31
non-devicetree platforms.
Now that i.MX is a devicetree-only platform, it is safe to
remove mx31_clocks_init() as there are no more users.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
drivers/clk/imx/clk-imx31.c | 71 -------------------------------------
1 file changed, 71 deletions(-)
diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c
index 4bb05e440cdd..7b13fb57d842 100644
--- a/drivers/clk/imx/clk-imx31.c
+++ b/drivers/clk/imx/clk-imx31.c
@@ -132,77 +132,6 @@ static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
clk_disable_unprepare(clk[iim_gate]);
}
-int __init mx31_clocks_init(unsigned long fref)
-{
- void __iomem *base;
-
- base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
- if (!base)
- panic("%s: failed to map registers\n", __func__);
-
- _mx31_clocks_init(base, fref);
-
- clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
- clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
- clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
- clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
- clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
- clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
- clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
- clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");
- clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
- clk_register_clkdev(clk[epit1_gate], "epit", NULL);
- clk_register_clkdev(clk[epit2_gate], "epit", NULL);
- clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
- clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
- clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
- clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
- clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
- clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
- clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
- clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
- clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
- clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
- clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
- clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
- clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
- clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
- /* i.mx31 has the i.mx21 type uart */
- clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
- clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
- clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
- clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
- clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
- clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
- clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
- clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
- clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
- clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");
- clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");
- clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
- clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
- clk_register_clkdev(clk[firi_gate], "firi", NULL);
- clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
- clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
- clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
- clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
- clk_register_clkdev(clk[iim_gate], "iim", NULL);
-
-
- imx_register_uart_clocks(uart_clks);
- mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
-
- return 0;
-}
-
static void __init mx31_clocks_init_dt(struct device_node *np)
{
struct device_node *osc_np;
--
2.17.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 10/11] clk: imx: imx35: Remove mx35_clocks_init()
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (8 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 09/11] clk: imx: imx31: Remove mx31_clocks_init() Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 11/11] clk: imx: imx21: Remove clock driver Fabio Estevam
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
mx35_clocks_init() has been used to register clocks on i.MX35
non-devicetree platforms.
Now that i.MX is a devicetree-only platform, it is safe to
remove mx35_clocks_init() as there are no more users.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
drivers/clk/imx/clk-imx35.c | 68 -------------------------------------
1 file changed, 68 deletions(-)
diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c
index e595f559907f..c1df03665c09 100644
--- a/drivers/clk/imx/clk-imx35.c
+++ b/drivers/clk/imx/clk-imx35.c
@@ -248,74 +248,6 @@ static void __init _mx35_clocks_init(void)
imx_print_silicon_rev("i.MX35", mx35_revision());
}
-int __init mx35_clocks_init(void)
-{
- _mx35_clocks_init();
-
- clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
- clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
- clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
- clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
- clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
- clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1");
- clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1");
- clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0");
- clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1");
- clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0");
- clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0");
- clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0");
- clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1");
- clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1");
- clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1");
- clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
- clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
- clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
- /* i.mx35 has the i.mx27 type fec */
- clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
- clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
- clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
- clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
- clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
- clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
- clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
- clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
- clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
- clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
- clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
- clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
- clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
- /* i.mx35 has the i.mx21 type uart */
- clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
- clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
- clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
- /* i.mx35 has the i.mx21 type rtc */
- clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");
- clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
- clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
- clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");
- clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
- clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1");
- clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
- clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
- clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
- clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
- clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27");
- clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
- clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
- clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
- clk_register_clkdev(clk[admux_gate], "audmux", NULL);
-
- mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);
-
- return 0;
-}
-
static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
{
_mx35_clocks_init();
--
2.17.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 11/11] clk: imx: imx21: Remove clock driver
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (9 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 10/11] clk: imx: imx35: Remove mx35_clocks_init() Fabio Estevam
@ 2020-09-17 0:41 ` Fabio Estevam
2020-09-17 8:12 ` [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Arnd Bergmann
2020-09-22 6:09 ` Shawn Guo
12 siblings, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2020-09-17 0:41 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, arnd, linux-imx, kernel
As i.MX21 support has been removed, get rid of its clock driver too.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Chamges since v1:
- None
drivers/clk/imx/Kconfig | 4 -
drivers/clk/imx/Makefile | 1 -
drivers/clk/imx/clk-imx21.c | 171 ------------------------------------
3 files changed, 176 deletions(-)
delete mode 100644 drivers/clk/imx/clk-imx21.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index e7defbac0936..3b393cb07295 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -13,10 +13,6 @@ config CLK_IMX1
def_bool SOC_IMX1
select MXC_CLK
-config CLK_IMX21
- def_bool SOC_IMX21
- select MXC_CLK
-
config CLK_IMX25
def_bool SOC_IMX25
select MXC_CLK
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 79e53f2257c1..dd6a737d060b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -31,7 +31,6 @@ clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
obj-$(CONFIG_CLK_IMX1) += clk-imx1.o
-obj-$(CONFIG_CLK_IMX21) += clk-imx21.o
obj-$(CONFIG_CLK_IMX25) += clk-imx25.o
obj-$(CONFIG_CLK_IMX27) += clk-imx27.o
obj-$(CONFIG_CLK_IMX31) += clk-imx31.o
diff --git a/drivers/clk/imx/clk-imx21.c b/drivers/clk/imx/clk-imx21.c
deleted file mode 100644
index 077b4a7123ce..000000000000
--- a/drivers/clk/imx/clk-imx21.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <dt-bindings/clock/imx21-clock.h>
-#include <soc/imx/timer.h>
-#include <asm/irq.h>
-
-#include "clk.h"
-
-#define MX21_CCM_BASE_ADDR 0x10027000
-#define MX21_GPT1_BASE_ADDR 0x10003000
-#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
-
-static void __iomem *ccm __initdata;
-
-/* Register offsets */
-#define CCM_CSCR (ccm + 0x00)
-#define CCM_MPCTL0 (ccm + 0x04)
-#define CCM_SPCTL0 (ccm + 0x0c)
-#define CCM_PCDR0 (ccm + 0x18)
-#define CCM_PCDR1 (ccm + 0x1c)
-#define CCM_PCCR0 (ccm + 0x20)
-#define CCM_PCCR1 (ccm + 0x24)
-
-static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
-static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
-static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
-static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };
-
-static struct clk *clk[IMX21_CLK_MAX];
-static struct clk_onecell_data clk_data;
-
-static void __init _mx21_clocks_init(unsigned long lref, unsigned long href)
-{
- BUG_ON(!ccm);
-
- clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
- clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref);
- clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href);
- clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
- clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
-
- clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
- clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
- clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
- clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
- clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
- clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
- clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
- clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
- clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
- clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
- clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
- clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
- clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);
-
- clk[IMX21_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "mpll", "mpll_sel", CCM_MPCTL0);
-
- clk[IMX21_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "spll", "spll_sel", CCM_SPCTL0);
-
- clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
- clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
- clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
-
- clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
- clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
- clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
- clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);
-
- clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
- clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
- clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
- clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
- clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
- clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
- clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
- clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
- clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
- clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
- clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
- clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
- clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
- clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
- clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
- clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
- clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
- clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
- clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
- clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
- clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
- clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
- clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
- clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
- clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
- clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
- clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
- clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
- clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
-
- clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
- clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
- clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
- clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
- clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
- clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
- clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
- clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
- clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
-
- imx_check_clocks(clk, ARRAY_SIZE(clk));
-}
-
-int __init mx21_clocks_init(unsigned long lref, unsigned long href)
-{
- ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K);
-
- _mx21_clocks_init(lref, href);
-
- clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0");
- clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
- clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1");
- clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
- clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2");
- clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
- clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3");
- clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
- clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
- clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0");
- clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0");
- clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0");
- clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1");
- clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1");
- clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2");
- clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2");
- clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0");
- clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
- clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0");
- clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0");
- clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0");
- clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0");
- clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma");
- clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma");
- clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0");
- clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");
- clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0");
-
- mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1, GPT_TYPE_IMX21);
-
- return 0;
-}
-
-static void __init mx21_clocks_init_dt(struct device_node *np)
-{
- ccm = of_iomap(np, 0);
-
- _mx21_clocks_init(32768, 26000000);
-
- clk_data.clks = clk;
- clk_data.clk_num = ARRAY_SIZE(clk);
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (10 preceding siblings ...)
2020-09-17 0:41 ` [PATCH v2 11/11] clk: imx: imx21: Remove clock driver Fabio Estevam
@ 2020-09-17 8:12 ` Arnd Bergmann
2020-09-22 6:09 ` Shawn Guo
12 siblings, 0 replies; 14+ messages in thread
From: Arnd Bergmann @ 2020-09-17 8:12 UTC (permalink / raw)
To: Fabio Estevam; +Cc: Linux ARM, Shawn Guo, NXP Linux Team, Sascha Hauer
On Thu, Sep 17, 2020 at 2:42 AM Fabio Estevam <festevam@gmail.com> wrote:
>
> Now that i.MX has been converted to a devicetree-only platform, do
> one more round of cleanups that consists mainly in using devicetree
> to get the peripherals base addresses and get rid of unused clock driver
> code.
>
> Changes since v1:
>
> - Do not introduce a sysctrl node to avoid breaking DT compatibility (Arnd)
> - Remove unused definitions for base address, IRQ and DMA (Arnd)
Whole series:
Acked-by: Arnd Bergmann <arnd@arndb.de>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
` (11 preceding siblings ...)
2020-09-17 8:12 ` [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Arnd Bergmann
@ 2020-09-22 6:09 ` Shawn Guo
12 siblings, 0 replies; 14+ messages in thread
From: Shawn Guo @ 2020-09-22 6:09 UTC (permalink / raw)
To: Fabio Estevam; +Cc: linux-arm-kernel, arnd, linux-imx, kernel
On Wed, Sep 16, 2020 at 09:41:14PM -0300, Fabio Estevam wrote:
> Now that i.MX has been converted to a devicetree-only platform, do
> one more round of cleanups that consists mainly in using devicetree
> to get the peripherals base addresses and get rid of unused clock driver
> code.
>
> Changes since v1:
>
> - Do not introduce a sysctrl node to avoid breaking DT compatibility (Arnd)
> - Remove unused definitions for base address, IRQ and DMA (Arnd)
>
> Fabio Estevam (11):
> ARM: imx27: Retrieve the SYSCTRL base address from devicetree
> ARM: imx27: Retrieve the CCM base address from devicetree
> ARM: imx31: Retrieve the IIM base address from devicetree
> ARM: imx3: Retrieve the CCM base address from devicetree
> ARM: imx3: Retrieve the AVIC base address from devicetree
> ARM: imx35: Retrieve the IIM base address from devicetree
> ARM: imx: Remove unused definitions
> clk: imx: imx27: Remove mx27_clocks_init()
> clk: imx: imx31: Remove mx31_clocks_init()
> clk: imx: imx35: Remove mx35_clocks_init()
> clk: imx: imx21: Remove clock driver
Applied all, thanks.
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-09-22 6:11 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-17 0:41 [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 01/11] ARM: imx27: Retrieve the SYSCTRL base address from devicetree Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 02/11] ARM: imx27: Retrieve the CCM " Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 03/11] ARM: imx31: Retrieve the IIM " Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 04/11] ARM: imx3: Retrieve the CCM " Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 05/11] ARM: imx3: Retrieve the AVIC " Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 06/11] ARM: imx35: Retrieve the IIM " Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 07/11] ARM: imx: Remove unused definitions Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 08/11] clk: imx: imx27: Remove mx27_clocks_init() Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 09/11] clk: imx: imx31: Remove mx31_clocks_init() Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 10/11] clk: imx: imx35: Remove mx35_clocks_init() Fabio Estevam
2020-09-17 0:41 ` [PATCH v2 11/11] clk: imx: imx21: Remove clock driver Fabio Estevam
2020-09-17 8:12 ` [PATCH v2 00/11] ARM: imx: Further cleanups due to dt-only conversion Arnd Bergmann
2020-09-22 6:09 ` Shawn Guo
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